ata-all.h revision 93882
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 93882 2002-04-05 13:13:56Z sos $ 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ 37#define ATA_E_IDNF 0x10 /* ID not found */ 38#define ATA_E_MC 0x20 /* media changed */ 39#define ATA_E_UNC 0x40 /* uncorrectable data */ 40#define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42#define ATA_FEATURE 0x01 /* (W) feature register */ 43#define ATA_F_DMA 0x01 /* enable DMA */ 44#define ATA_F_OVL 0x02 /* enable overlap */ 45 46#define ATA_COUNT 0x02 /* (W) sector count */ 47#define ATA_IREASON 0x02 /* (R) interrupt reason */ 48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49#define ATA_I_IN 0x02 /* read (1) | write (0) */ 50#define ATA_I_RELEASE 0x04 /* released bus (1) */ 51#define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53#define ATA_SECTOR 0x03 /* sector # */ 54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57#define ATA_D_LBA 0x40 /* use LBA addressing */ 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */ 61#define ATA_C_NOP 0x00 /* NOP command */ 62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */ 63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */ 64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 65#define ATA_C_READ 0x20 /* read command */ 66#define ATA_C_READ48 0x24 /* read command */ 67#define ATA_C_READ_DMA48 0x25 /* read w/DMA command */ 68#define ATA_C_READ_DMA_QUEUED48 0x26 /* read w/DMA QUEUED command */ 69#define ATA_C_READ_MUL48 0x29 /* read multi command */ 70#define ATA_C_WRITE 0x30 /* write command */ 71#define ATA_C_WRITE48 0x34 /* write command */ 72#define ATA_C_WRITE_DMA48 0x35 /* write w/DMA command */ 73#define ATA_C_WRITE_DMA_QUEUED48 0x36 /* write w/DMA QUEUED command */ 74#define ATA_C_WRITE_MUL48 0x39 /* write multi command */ 75#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 76#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 77#define ATA_C_SERVICE 0xa2 /* service command */ 78#define ATA_C_READ_MUL 0xc4 /* read multi command */ 79#define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 80#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 81#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */ 82#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 83#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 84#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */ 85#define ATA_C_SLEEP 0xe6 /* sleep command */ 86#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */ 87#define ATA_C_FLUSHCACHE48 0xea /* flush cache to disk */ 88#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 89#define ATA_C_SETFEATURES 0xef /* features command */ 90#define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 91#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 92#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */ 93#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 94#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */ 95#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */ 96#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */ 97#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */ 98#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */ 99 100#define ATA_STATUS 0x07 /* status register */ 101#define ATA_S_ERROR 0x01 /* error */ 102#define ATA_S_INDEX 0x02 /* index */ 103#define ATA_S_CORR 0x04 /* data corrected */ 104#define ATA_S_DRQ 0x08 /* data request */ 105#define ATA_S_DSC 0x10 /* drive seek completed */ 106#define ATA_S_SERVICE 0x10 /* drive needs service */ 107#define ATA_S_DWF 0x20 /* drive write fault */ 108#define ATA_S_DMA 0x20 /* DMA ready */ 109#define ATA_S_READY 0x40 /* drive ready */ 110#define ATA_S_BUSY 0x80 /* busy */ 111 112#define ATA_ALTSTAT 0x00 /* alternate status register */ 113#define ATA_ALTOFFSET 0x206 /* alternate registers offset */ 114#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ 115#define ATA_A_IDS 0x02 /* disable interrupts */ 116#define ATA_A_RESET 0x04 /* RESET controller */ 117#define ATA_A_4BIT 0x08 /* 4 head bits */ 118 119/* misc defines */ 120#define ATA_PRIMARY 0x1f0 121#define ATA_SECONDARY 0x170 122#define ATA_IOSIZE 0x08 123#define ATA_ALTIOSIZE 0x01 124#define ATA_BMIOSIZE 0x08 125#define ATA_OP_FINISHED 0x00 126#define ATA_OP_CONTINUES 0x01 127#define ATA_IOADDR_RID 0 128#define ATA_ALTADDR_RID 1 129#define ATA_BMADDR_RID 2 130#define ATA_IRQ_RID 0 131#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 132 133/* busmaster DMA related defines */ 134#define ATA_DMA_ENTRIES 256 135#define ATA_DMA_EOT 0x80000000 136 137#define ATA_BMCMD_PORT 0x00 138#define ATA_BMCMD_START_STOP 0x01 139#define ATA_BMCMD_WRITE_READ 0x08 140 141#define ATA_BMDEVSPEC_0 0x01 142 143#define ATA_BMSTAT_PORT 0x02 144#define ATA_BMSTAT_ACTIVE 0x01 145#define ATA_BMSTAT_ERROR 0x02 146#define ATA_BMSTAT_INTERRUPT 0x04 147#define ATA_BMSTAT_MASK 0x07 148#define ATA_BMSTAT_DMA_MASTER 0x20 149#define ATA_BMSTAT_DMA_SLAVE 0x40 150#define ATA_BMSTAT_DMA_SIMPLEX 0x80 151 152#define ATA_BMDEVSPEC_1 0x03 153#define ATA_BMDTP_PORT 0x04 154 155/* structure for holding DMA address data */ 156struct ata_dmaentry { 157 u_int32_t base; 158 u_int32_t count; 159}; 160 161struct ata_dmastate { 162 bus_dma_tag_t ddmatag; /* data DMA tag */ 163 bus_dmamap_t ddmamap; /* data DMA map */ 164 bus_dma_tag_t cdmatag; /* control DMA tag */ 165 bus_dmamap_t cdmamap; /* control DMA map */ 166 struct ata_dmaentry *dmatab; /* DMA transfer table */ 167 bus_addr_t mdmatab; /* bus address of dmatab */ 168 int flags; /* debugging */ 169#define ATA_DS_ACTIVE 0x01 /* debugging */ 170#define ATA_DS_READ 0x02 /* transaction is a read */ 171}; 172 173/* structure describing an ATA/ATAPI device */ 174struct ata_device { 175 struct ata_channel *channel; 176 int unit; /* unit number */ 177#define ATA_MASTER 0x00 178#define ATA_SLAVE 0x10 179 180 char *name; /* device name */ 181 struct ata_params *param; /* ata param structure */ 182 void *driver; /* ptr to driver for device */ 183 int flags; 184#define ATA_D_USE_CHS 0x0001 185#define ATA_D_DETACHING 0x0002 186#define ATA_D_MEDIA_CHANGED 0x0004 187 188 int mode; /* transfermode */ 189 int cmd; /* last cmd executed */ 190 void *result; /* misc data */ 191 struct ata_dmastate dmastate; /* dma state */ 192}; 193 194/* structure describing an ATA channel */ 195struct ata_channel { 196 struct device *dev; /* device handle */ 197 int unit; /* channel number */ 198 struct resource *r_io; /* io addr resource handle */ 199 struct resource *r_altio; /* altio addr resource handle */ 200 struct resource *r_bmio; /* bmio addr resource handle */ 201 bus_dma_tag_t dmatag; /* parent dma tag */ 202 struct resource *r_irq; /* interrupt of this channel */ 203 void *ih; /* interrupt handle */ 204 int (*intr_func)(struct ata_channel *); /* interrupt function */ 205 u_int32_t chiptype; /* pciid of controller chip */ 206 u_int32_t alignment; /* dma engine min alignment */ 207 int flags; /* controller flags */ 208#define ATA_NO_SLAVE 0x01 209#define ATA_USE_16BIT 0x02 210#define ATA_ATAPI_DMA_RO 0x04 211#define ATA_QUEUED 0x08 212#define ATA_DMA_ACTIVE 0x10 213 214 struct ata_device device[2]; /* devices on this channel */ 215#define MASTER 0x00 216#define SLAVE 0x01 217 218 int devices; /* what is present */ 219#define ATA_ATA_MASTER 0x01 220#define ATA_ATA_SLAVE 0x02 221#define ATA_ATAPI_MASTER 0x04 222#define ATA_ATAPI_SLAVE 0x08 223 224 u_int8_t status; /* last controller status */ 225 u_int8_t error; /* last controller error */ 226 int active; /* active processing request */ 227#define ATA_IDLE 0x0000 228#define ATA_IMMEDIATE 0x0001 229#define ATA_WAIT_INTR 0x0002 230#define ATA_WAIT_READY 0x0004 231#define ATA_WAIT_MASK 0x0007 232#define ATA_ACTIVE 0x0010 233#define ATA_ACTIVE_ATA 0x0020 234#define ATA_ACTIVE_ATAPI 0x0040 235#define ATA_CONTROL 0x0080 236 237 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 238 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 239 void *running; /* currently running request */ 240}; 241 242/* disk bay/drawer related */ 243#define ATA_LED_OFF 0x00 244#define ATA_LED_RED 0x01 245#define ATA_LED_GREEN 0x02 246#define ATA_LED_ORANGE 0x03 247 248/* externs */ 249extern devclass_t ata_devclass; 250 251/* public prototypes */ 252int ata_probe(device_t); 253int ata_attach(device_t); 254int ata_detach(device_t); 255int ata_resume(device_t); 256 257void ata_start(struct ata_channel *); 258void ata_reset(struct ata_channel *); 259int ata_reinit(struct ata_channel *); 260int ata_wait(struct ata_device *, u_int8_t); 261int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int8_t, int); 262void ata_drawerleds(struct ata_device *, u_int8_t); 263int ata_printf(struct ata_channel *, int, const char *, ...) __printflike(3, 4); 264int ata_prtdev(struct ata_device *, const char *, ...) __printflike(2, 3); 265void ata_set_name(struct ata_device *, char *, int); 266void ata_free_name(struct ata_device *); 267int ata_get_lun(u_int32_t *); 268int ata_test_lun(u_int32_t *, int); 269void ata_free_lun(u_int32_t *, int); 270char *ata_mode2str(int); 271int ata_pmode(struct ata_params *); 272int ata_wmode(struct ata_params *); 273int ata_umode(struct ata_params *); 274int ata_find_dev(device_t, u_int32_t, u_int32_t); 275 276int ata_dmaalloc(struct ata_device *); 277void ata_dmafree(struct ata_device *); 278void ata_dmafreetags(struct ata_channel *); 279void ata_dmainit(struct ata_device *, int, int, int); 280int ata_dmasetup(struct ata_device *, caddr_t, int32_t); 281void ata_dmastart(struct ata_device *, int); 282int ata_dmastatus(struct ata_channel *); 283int ata_dmadone(struct ata_device *); 284 285/* macros for locking a channel */ 286#define ATA_LOCK_CH(ch, value)\ 287 atomic_cmpset_int(&(ch)->active, ATA_IDLE, (value)) 288 289#define ATA_SLEEPLOCK_CH(ch, value)\ 290 while (!atomic_cmpset_int(&(ch)->active, ATA_IDLE, (value)))\ 291 tsleep((caddr_t)&(ch), PRIBIO, "atalck", 1); 292 293#define ATA_FORCELOCK_CH(ch, value)\ 294 (ch)->active = value; 295 296#define ATA_UNLOCK_CH(ch)\ 297 (ch)->active = ATA_IDLE 298 299/* macros to hide busspace uglyness */ 300#define ATA_INB(res, offset) \ 301 bus_space_read_1(rman_get_bustag((res)), \ 302 rman_get_bushandle((res)), (offset)) 303#define ATA_INW(res, offset) \ 304 bus_space_read_2(rman_get_bustag((res)), \ 305 rman_get_bushandle((res)), (offset)) 306#define ATA_INL(res, offset) \ 307 bus_space_read_4(rman_get_bustag((res)), \ 308 rman_get_bushandle((res)), (offset)) 309#define ATA_INSW(res, offset, addr, count) \ 310 bus_space_read_multi_2(rman_get_bustag((res)), \ 311 rman_get_bushandle((res)), \ 312 (offset), (addr), (count)) 313#define ATA_INSW_STRM(res, offset, addr, count) \ 314 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 315 rman_get_bushandle((res)), \ 316 (offset), (addr), (count)) 317#define ATA_INSL(res, offset, addr, count) \ 318 bus_space_read_multi_4(rman_get_bustag((res)), \ 319 rman_get_bushandle((res)), \ 320 (offset), (addr), (count)) 321#define ATA_INSL_STRM(res, offset, addr, count) \ 322 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 323 rman_get_bushandle((res)), \ 324 (offset), (addr), (count)) 325#define ATA_OUTB(res, offset, value) \ 326 bus_space_write_1(rman_get_bustag((res)), \ 327 rman_get_bushandle((res)), (offset), (value)) 328#define ATA_OUTW(res, offset, value) \ 329 bus_space_write_2(rman_get_bustag((res)), \ 330 rman_get_bushandle((res)), (offset), (value)) 331#define ATA_OUTL(res, offset, value) \ 332 bus_space_write_4(rman_get_bustag((res)), \ 333 rman_get_bushandle((res)), (offset), (value)) 334#define ATA_OUTSW(res, offset, addr, count) \ 335 bus_space_write_multi_2(rman_get_bustag((res)), \ 336 rman_get_bushandle((res)), \ 337 (offset), (addr), (count)) 338#define ATA_OUTSW_STRM(res, offset, addr, count) \ 339 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 340 rman_get_bushandle((res)), \ 341 (offset), (addr), (count)) 342#define ATA_OUTSL(res, offset, addr, count) \ 343 bus_space_write_multi_4(rman_get_bustag((res)), \ 344 rman_get_bushandle((res)), \ 345 (offset), (addr), (count)) 346#define ATA_OUTSL_STRM(res, offset, addr, count) \ 347 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 348 rman_get_bushandle((res)), \ 349 (offset), (addr), (count)) 350