ata-all.h revision 175059
1/*- 2 * Copyright (c) 1998 - 2007 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ata/ata-all.h 175059 2008-01-02 20:31:14Z phk $ 27 */ 28 29/* ATA register defines */ 30#define ATA_DATA 0 /* (RW) data */ 31 32#define ATA_FEATURE 1 /* (W) feature */ 33#define ATA_F_DMA 0x01 /* enable DMA */ 34#define ATA_F_OVL 0x02 /* enable overlap */ 35 36#define ATA_COUNT 2 /* (W) sector count */ 37 38#define ATA_SECTOR 3 /* (RW) sector # */ 39#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 40#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 41#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 42#define ATA_D_LBA 0x40 /* use LBA addressing */ 43#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 44 45#define ATA_COMMAND 7 /* (W) command */ 46 47#define ATA_ERROR 8 /* (R) error */ 48#define ATA_E_ILI 0x01 /* illegal length */ 49#define ATA_E_NM 0x02 /* no media */ 50#define ATA_E_ABORT 0x04 /* command aborted */ 51#define ATA_E_MCR 0x08 /* media change request */ 52#define ATA_E_IDNF 0x10 /* ID not found */ 53#define ATA_E_MC 0x20 /* media changed */ 54#define ATA_E_UNC 0x40 /* uncorrectable data */ 55#define ATA_E_ICRC 0x80 /* UDMA crc error */ 56#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 57 58#define ATA_IREASON 9 /* (R) interrupt reason */ 59#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 60#define ATA_I_IN 0x02 /* read (1) | write (0) */ 61#define ATA_I_RELEASE 0x04 /* released bus (1) */ 62#define ATA_I_TAGMASK 0xf8 /* tag mask */ 63 64#define ATA_STATUS 10 /* (R) status */ 65#define ATA_ALTSTAT 11 /* (R) alternate status */ 66#define ATA_S_ERROR 0x01 /* error */ 67#define ATA_S_INDEX 0x02 /* index */ 68#define ATA_S_CORR 0x04 /* data corrected */ 69#define ATA_S_DRQ 0x08 /* data request */ 70#define ATA_S_DSC 0x10 /* drive seek completed */ 71#define ATA_S_SERVICE 0x10 /* drive needs service */ 72#define ATA_S_DWF 0x20 /* drive write fault */ 73#define ATA_S_DMA 0x20 /* DMA ready */ 74#define ATA_S_READY 0x40 /* drive ready */ 75#define ATA_S_BUSY 0x80 /* busy */ 76 77#define ATA_CONTROL 12 /* (W) control */ 78 79#define ATA_CTLOFFSET 0x206 /* control register offset */ 80#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 81#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 82#define ATA_A_IDS 0x02 /* disable interrupts */ 83#define ATA_A_RESET 0x04 /* RESET controller */ 84#define ATA_A_4BIT 0x08 /* 4 head bits */ 85#define ATA_A_HOB 0x80 /* High Order Byte enable */ 86 87/* SATA register defines */ 88#define ATA_SSTATUS 13 89#define ATA_SS_DET_MASK 0x0000000f 90#define ATA_SS_DET_NO_DEVICE 0x00000000 91#define ATA_SS_DET_DEV_PRESENT 0x00000001 92#define ATA_SS_DET_PHY_ONLINE 0x00000003 93#define ATA_SS_DET_PHY_OFFLINE 0x00000004 94 95#define ATA_SS_SPD_MASK 0x000000f0 96#define ATA_SS_SPD_NO_SPEED 0x00000000 97#define ATA_SS_SPD_GEN1 0x00000010 98#define ATA_SS_SPD_GEN2 0x00000020 99 100#define ATA_SS_IPM_MASK 0x00000f00 101#define ATA_SS_IPM_NO_DEVICE 0x00000000 102#define ATA_SS_IPM_ACTIVE 0x00000100 103#define ATA_SS_IPM_PARTIAL 0x00000200 104#define ATA_SS_IPM_SLUMBER 0x00000600 105 106#define ATA_SS_CONWELL_MASK \ 107 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 108#define ATA_SS_CONWELL_GEN1 \ 109 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 110#define ATA_SS_CONWELL_GEN2 \ 111 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 112 113#define ATA_SERROR 14 114#define ATA_SE_DATA_CORRECTED 0x00000001 115#define ATA_SE_COMM_CORRECTED 0x00000002 116#define ATA_SE_DATA_ERR 0x00000100 117#define ATA_SE_COMM_ERR 0x00000200 118#define ATA_SE_PROT_ERR 0x00000400 119#define ATA_SE_HOST_ERR 0x00000800 120#define ATA_SE_PHY_CHANGED 0x00010000 121#define ATA_SE_PHY_IERROR 0x00020000 122#define ATA_SE_COMM_WAKE 0x00040000 123#define ATA_SE_DECODE_ERR 0x00080000 124#define ATA_SE_PARITY_ERR 0x00100000 125#define ATA_SE_CRC_ERR 0x00200000 126#define ATA_SE_HANDSHAKE_ERR 0x00400000 127#define ATA_SE_LINKSEQ_ERR 0x00800000 128#define ATA_SE_TRANSPORT_ERR 0x01000000 129#define ATA_SE_UNKNOWN_FIS 0x02000000 130 131#define ATA_SCONTROL 15 132#define ATA_SC_DET_MASK 0x0000000f 133#define ATA_SC_DET_IDLE 0x00000000 134#define ATA_SC_DET_RESET 0x00000001 135#define ATA_SC_DET_DISABLE 0x00000004 136 137#define ATA_SC_SPD_MASK 0x000000f0 138#define ATA_SC_SPD_NO_SPEED 0x00000000 139#define ATA_SC_SPD_SPEED_GEN1 0x00000010 140#define ATA_SC_SPD_SPEED_GEN2 0x00000020 141 142#define ATA_SC_IPM_MASK 0x00000f00 143#define ATA_SC_IPM_NONE 0x00000000 144#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 145#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 146 147#define ATA_SACTIVE 16 148 149/* SATA AHCI v1.0 register defines */ 150#define ATA_AHCI_CAP 0x00 151#define ATA_AHCI_NPMASK 0x1f 152#define ATA_AHCI_CAP_CLO 0x01000000 153#define ATA_AHCI_CAP_64BIT 0x80000000 154 155#define ATA_AHCI_GHC 0x04 156#define ATA_AHCI_GHC_AE 0x80000000 157#define ATA_AHCI_GHC_IE 0x00000002 158#define ATA_AHCI_GHC_HR 0x00000001 159 160#define ATA_AHCI_IS 0x08 161#define ATA_AHCI_PI 0x0c 162#define ATA_AHCI_VS 0x10 163 164#define ATA_AHCI_OFFSET 0x80 165 166#define ATA_AHCI_P_CLB 0x100 167#define ATA_AHCI_P_CLBU 0x104 168#define ATA_AHCI_P_FB 0x108 169#define ATA_AHCI_P_FBU 0x10c 170#define ATA_AHCI_P_IS 0x110 171#define ATA_AHCI_P_IE 0x114 172#define ATA_AHCI_P_IX_DHR 0x00000001 173#define ATA_AHCI_P_IX_PS 0x00000002 174#define ATA_AHCI_P_IX_DS 0x00000004 175#define ATA_AHCI_P_IX_SDB 0x00000008 176#define ATA_AHCI_P_IX_UF 0x00000010 177#define ATA_AHCI_P_IX_DP 0x00000020 178#define ATA_AHCI_P_IX_PC 0x00000040 179#define ATA_AHCI_P_IX_DI 0x00000080 180 181#define ATA_AHCI_P_IX_PRC 0x00400000 182#define ATA_AHCI_P_IX_IPM 0x00800000 183#define ATA_AHCI_P_IX_OF 0x01000000 184#define ATA_AHCI_P_IX_INF 0x04000000 185#define ATA_AHCI_P_IX_IF 0x08000000 186#define ATA_AHCI_P_IX_HBD 0x10000000 187#define ATA_AHCI_P_IX_HBF 0x20000000 188#define ATA_AHCI_P_IX_TFE 0x40000000 189#define ATA_AHCI_P_IX_CPD 0x80000000 190 191#define ATA_AHCI_P_CMD 0x118 192#define ATA_AHCI_P_CMD_ST 0x00000001 193#define ATA_AHCI_P_CMD_SUD 0x00000002 194#define ATA_AHCI_P_CMD_POD 0x00000004 195#define ATA_AHCI_P_CMD_CLO 0x00000008 196#define ATA_AHCI_P_CMD_FRE 0x00000010 197#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 198#define ATA_AHCI_P_CMD_ISS 0x00002000 199#define ATA_AHCI_P_CMD_FR 0x00004000 200#define ATA_AHCI_P_CMD_CR 0x00008000 201#define ATA_AHCI_P_CMD_CPS 0x00010000 202#define ATA_AHCI_P_CMD_PMA 0x00020000 203#define ATA_AHCI_P_CMD_HPCP 0x00040000 204#define ATA_AHCI_P_CMD_ISP 0x00080000 205#define ATA_AHCI_P_CMD_CPD 0x00100000 206#define ATA_AHCI_P_CMD_ATAPI 0x01000000 207#define ATA_AHCI_P_CMD_DLAE 0x02000000 208#define ATA_AHCI_P_CMD_ALPE 0x04000000 209#define ATA_AHCI_P_CMD_ASP 0x08000000 210#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 211#define ATA_AHCI_P_CMD_NOOP 0x00000000 212#define ATA_AHCI_P_CMD_ACTIVE 0x10000000 213#define ATA_AHCI_P_CMD_PARTIAL 0x20000000 214#define ATA_AHCI_P_CMD_SLUMPER 0x60000000 215 216#define ATA_AHCI_P_TFD 0x120 217#define ATA_AHCI_P_SIG 0x124 218#define ATA_AHCI_P_SSTS 0x128 219#define ATA_AHCI_P_SCTL 0x12c 220#define ATA_AHCI_P_SERR 0x130 221#define ATA_AHCI_P_SACT 0x134 222#define ATA_AHCI_P_CI 0x138 223 224#define ATA_AHCI_CL_SIZE 32 225#define ATA_AHCI_CL_OFFSET 0 226#define ATA_AHCI_FB_OFFSET 1024 227#define ATA_AHCI_CT_OFFSET 1024+256 228#define ATA_AHCI_CT_SG_OFFSET 128 229#define ATA_AHCI_CT_SIZE 256 230 231struct ata_ahci_dma_prd { 232 u_int64_t dba; 233 u_int32_t reserved; 234 u_int32_t dbc; /* 0 based */ 235#define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 236#define ATA_AHCI_PRD_IPC (1<<31) 237} __packed; 238 239struct ata_ahci_cmd_tab { 240 u_int8_t cfis[64]; 241 u_int8_t acmd[32]; 242 u_int8_t reserved[32]; 243 struct ata_ahci_dma_prd prd_tab[16]; 244} __packed; 245 246struct ata_ahci_cmd_list { 247 u_int16_t cmd_flags; 248 u_int16_t prd_length; /* PRD entries */ 249 u_int32_t bytecount; 250 u_int64_t cmd_table_phys; /* 128byte aligned */ 251} __packed; 252 253 254/* DMA register defines */ 255#define ATA_DMA_ENTRIES 256 256#define ATA_DMA_EOT 0x80000000 257 258#define ATA_BMCMD_PORT 17 259#define ATA_BMCMD_START_STOP 0x01 260#define ATA_BMCMD_WRITE_READ 0x08 261 262#define ATA_BMDEVSPEC_0 18 263#define ATA_BMSTAT_PORT 19 264#define ATA_BMSTAT_ACTIVE 0x01 265#define ATA_BMSTAT_ERROR 0x02 266#define ATA_BMSTAT_INTERRUPT 0x04 267#define ATA_BMSTAT_MASK 0x07 268#define ATA_BMSTAT_DMA_MASTER 0x20 269#define ATA_BMSTAT_DMA_SLAVE 0x40 270#define ATA_BMSTAT_DMA_SIMPLEX 0x80 271 272#define ATA_BMDEVSPEC_1 20 273#define ATA_BMDTP_PORT 21 274 275#define ATA_IDX_ADDR 22 276#define ATA_IDX_DATA 23 277#define ATA_MAX_RES 24 278 279/* misc defines */ 280#define ATA_PRIMARY 0x1f0 281#define ATA_SECONDARY 0x170 282#define ATA_PC98_BANK 0x432 283#define ATA_IOSIZE 0x08 284#define ATA_PC98_IOSIZE 0x10 285#define ATA_CTLIOSIZE 0x01 286#define ATA_BMIOSIZE 0x08 287#define ATA_PC98_BANKIOSIZE 0x01 288#define ATA_IOADDR_RID 0 289#define ATA_CTLADDR_RID 1 290#define ATA_BMADDR_RID 0x20 291#define ATA_PC98_CTLADDR_RID 8 292#define ATA_PC98_BANKADDR_RID 9 293#define ATA_IRQ_RID 0 294#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 295#define ATA_CFA_MAGIC1 0x844A 296#define ATA_CFA_MAGIC2 0x848A 297#define ATA_CFA_MAGIC3 0x8400 298#define ATAPI_MAGIC_LSB 0x14 299#define ATAPI_MAGIC_MSB 0xeb 300#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 301#define ATAPI_P_WRITE (ATA_S_DRQ) 302#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 303#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 304#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 305#define ATAPI_P_ABORT 0 306#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 307#define ATA_OP_CONTINUES 0 308#define ATA_OP_FINISHED 1 309#define ATA_MAX_28BIT_LBA 268435455UL 310 311/* structure used for composite atomic operations */ 312#define MAX_COMPOSITES 32 /* u_int32_t bits */ 313struct ata_composite { 314 struct mtx lock; /* control lock */ 315 u_int32_t rd_needed; /* needed read subdisks */ 316 u_int32_t rd_done; /* done read subdisks */ 317 u_int32_t wr_needed; /* needed write subdisks */ 318 u_int32_t wr_depend; /* write depends on subdisks */ 319 u_int32_t wr_done; /* done write subdisks */ 320 struct ata_request *request[MAX_COMPOSITES]; 321 u_int32_t residual; /* bytes still to transfer */ 322 caddr_t data_1; 323 caddr_t data_2; 324}; 325 326/* structure used to queue an ATA/ATAPI request */ 327struct ata_request { 328 device_t dev; /* device handle */ 329 device_t parent; /* channel handle */ 330 union { 331 struct { 332 u_int8_t command; /* command reg */ 333 u_int16_t feature; /* feature reg */ 334 u_int16_t count; /* count reg */ 335 u_int64_t lba; /* lba reg */ 336 } ata; 337 struct { 338 u_int8_t ccb[16]; /* ATAPI command block */ 339 struct atapi_sense sense; /* ATAPI request sense data */ 340 u_int8_t saved_cmd; /* ATAPI saved command */ 341 } atapi; 342 } u; 343 u_int32_t bytecount; /* bytes to transfer */ 344 u_int32_t transfersize; /* bytes pr transfer */ 345 caddr_t data; /* pointer to data buf */ 346 int flags; 347#define ATA_R_CONTROL 0x00000001 348#define ATA_R_READ 0x00000002 349#define ATA_R_WRITE 0x00000004 350#define ATA_R_ATAPI 0x00000008 351#define ATA_R_DMA 0x00000010 352#define ATA_R_QUIET 0x00000020 353#define ATA_R_TIMEOUT 0x00000040 354 355#define ATA_R_ORDERED 0x00000100 356#define ATA_R_AT_HEAD 0x00000200 357#define ATA_R_REQUEUE 0x00000400 358#define ATA_R_THREAD 0x00000800 359#define ATA_R_DIRECT 0x00001000 360 361#define ATA_R_DEBUG 0x10000000 362#define ATA_R_DANGER1 0x20000000 363#define ATA_R_DANGER2 0x40000000 364 365 u_int8_t status; /* ATA status */ 366 u_int8_t error; /* ATA error */ 367 u_int8_t dmastat; /* DMA status */ 368 u_int32_t donecount; /* bytes transferred */ 369 int result; /* result error code */ 370 void (*callback)(struct ata_request *request); 371 struct sema done; /* request done sema */ 372 int retries; /* retry count */ 373 int timeout; /* timeout for this cmd */ 374 struct callout callout; /* callout management */ 375 struct task task; /* task management */ 376 struct bio *bio; /* bio for this request */ 377 int this; /* this request ID */ 378 struct ata_composite *composite; /* for composite atomic ops */ 379 void *driver; /* driver specific */ 380 TAILQ_ENTRY(ata_request) chain; /* list management */ 381}; 382 383/* define this for debugging request processing */ 384#if 0 385#define ATA_DEBUG_RQ(request, string) \ 386 { \ 387 if (request->flags & ATA_R_DEBUG) \ 388 device_printf(request->dev, "req=%p %s " string "\n", \ 389 request, ata_cmd2str(request)); \ 390 } 391#else 392#define ATA_DEBUG_RQ(request, string) 393#endif 394 395 396/* structure describing an ATA/ATAPI device */ 397struct ata_device { 398 device_t dev; /* device handle */ 399 int unit; /* physical unit */ 400#define ATA_MASTER 0x00 401#define ATA_SLAVE 0x10 402 403 struct ata_params param; /* ata param structure */ 404 int mode; /* current transfermode */ 405 u_int32_t max_iosize; /* max IO size */ 406 int flags; 407#define ATA_D_USE_CHS 0x0001 408#define ATA_D_MEDIA_CHANGED 0x0002 409#define ATA_D_ENC_PRESENT 0x0004 410#define ATA_D_48BIT_ACTIVE 0x0008 411}; 412 413/* structure for holding DMA Physical Region Descriptors (PRD) entries */ 414struct ata_dma_prdentry { 415 u_int32_t addr; 416 u_int32_t count; 417}; 418 419/* structure used by the setprd function */ 420struct ata_dmasetprd_args { 421 void *dmatab; 422 int nsegs; 423 int error; 424}; 425 426/* structure holding DMA related information */ 427struct ata_dma { 428 bus_dma_tag_t dmatag; /* parent DMA tag */ 429 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 430 bus_dmamap_t sg_map; /* SG list DMA map */ 431 void *sg; /* DMA transfer table */ 432 bus_addr_t sg_bus; /* bus address of dmatab */ 433 bus_dma_tag_t data_tag; /* data DMA tag */ 434 bus_dmamap_t data_map; /* data DMA map */ 435 bus_dma_tag_t work_tag; /* workspace DMA tag */ 436 bus_dmamap_t work_map; /* workspace DMA map */ 437 u_int8_t *work; /* workspace */ 438 bus_addr_t work_bus; /* bus address of dmatab */ 439 440 u_int32_t alignment; /* DMA SG list alignment */ 441 u_int32_t boundary; /* DMA SG list boundary */ 442 u_int32_t segsize; /* DMA SG list segment size */ 443 u_int32_t max_iosize; /* DMA data max IO size */ 444 u_int32_t cur_iosize; /* DMA data current IO size */ 445 u_int64_t max_address; /* highest DMA'able address */ 446 int flags; 447#define ATA_DMA_READ 0x01 /* transaction is a read */ 448#define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */ 449#define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */ 450 451 void (*alloc)(device_t dev); 452 void (*free)(device_t dev); 453 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 454 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs); 455 int (*unload)(device_t dev); 456 int (*start)(device_t dev); 457 int (*stop)(device_t dev); 458 void (*reset)(device_t dev); 459}; 460 461/* structure holding lowlevel functions */ 462struct ata_lowlevel { 463 int (*status)(device_t dev); 464 int (*begin_transaction)(struct ata_request *request); 465 int (*end_transaction)(struct ata_request *request); 466 int (*command)(struct ata_request *request); 467 void (*tf_read)(struct ata_request *request); 468 void (*tf_write)(struct ata_request *request); 469}; 470 471/* structure holding resources for an ATA channel */ 472struct ata_resource { 473 struct resource *res; 474 int offset; 475}; 476 477/* structure describing an ATA channel */ 478struct ata_channel { 479 device_t dev; /* device handle */ 480 int unit; /* physical channel */ 481 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 482 struct resource *r_irq; /* interrupt of this channel */ 483 void *ih; /* interrupt handle */ 484 struct ata_lowlevel hw; /* lowlevel HW functions */ 485 struct ata_dma *dma; /* DMA data / functions */ 486 int flags; /* channel flags */ 487#define ATA_NO_SLAVE 0x01 488#define ATA_USE_16BIT 0x02 489#define ATA_ATAPI_DMA_RO 0x04 490#define ATA_NO_48BIT_DMA 0x08 491#define ATA_ALWAYS_DMASTAT 0x10 492 493 int devices; /* what is present */ 494#define ATA_ATA_MASTER 0x01 495#define ATA_ATA_SLAVE 0x02 496#define ATA_ATAPI_MASTER 0x04 497#define ATA_ATAPI_SLAVE 0x08 498#define ATA_PORTMULTIPLIER 0x10 499 500 struct mtx state_mtx; /* state lock */ 501 int state; /* ATA channel state */ 502#define ATA_IDLE 0x0000 503#define ATA_ACTIVE 0x0001 504#define ATA_STALL_QUEUE 0x0002 505 506 struct mtx queue_mtx; /* queue lock */ 507 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 508 struct ata_request *freezepoint; /* composite freezepoint */ 509 struct ata_request *running; /* currently running request */ 510}; 511 512/* disk bay/enclosure related */ 513#define ATA_LED_OFF 0x00 514#define ATA_LED_RED 0x01 515#define ATA_LED_GREEN 0x02 516#define ATA_LED_ORANGE 0x03 517#define ATA_LED_MASK 0x03 518 519/* externs */ 520extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 521extern struct intr_config_hook *ata_delayed_attach; 522extern devclass_t ata_devclass; 523extern int ata_wc; 524 525/* public prototypes */ 526/* ata-all.c: */ 527int ata_probe(device_t dev); 528int ata_attach(device_t dev); 529int ata_detach(device_t dev); 530int ata_reinit(device_t dev); 531int ata_suspend(device_t dev); 532int ata_resume(device_t dev); 533int ata_interrupt(void *data); 534int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 535int ata_identify(device_t dev); 536void ata_default_registers(device_t dev); 537void ata_modify_if_48bit(struct ata_request *request); 538void ata_udelay(int interval); 539char *ata_mode2str(int mode); 540int ata_pmode(struct ata_params *ap); 541int ata_wmode(struct ata_params *ap); 542int ata_umode(struct ata_params *ap); 543int ata_limit_mode(device_t dev, int mode, int maxmode); 544 545/* ata-queue.c: */ 546int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 547int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 548void ata_queue_request(struct ata_request *request); 549void ata_start(device_t dev); 550void ata_finish(struct ata_request *request); 551void ata_timeout(struct ata_request *); 552void ata_catch_inflight(device_t dev); 553void ata_fail_requests(device_t dev); 554char *ata_cmd2str(struct ata_request *request); 555 556/* ata-lowlevel.c: */ 557void ata_generic_hw(device_t dev); 558int ata_begin_transaction(struct ata_request *); 559int ata_end_transaction(struct ata_request *); 560void ata_generic_reset(device_t dev); 561int ata_generic_command(struct ata_request *request); 562 563/* macros for alloc/free of struct ata_request */ 564extern uma_zone_t ata_request_zone; 565#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 566#define ata_free_request(request) { \ 567 if (!(request->flags & ATA_R_DANGER2)) \ 568 uma_zfree(ata_request_zone, request); \ 569 } 570/* macros for alloc/free of struct ata_composite */ 571extern uma_zone_t ata_composite_zone; 572#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 573#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 574 575MALLOC_DECLARE(M_ATA); 576 577/* misc newbus defines */ 578#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 579 580/* macros to hide busspace uglyness */ 581#define ATA_INB(res, offset) \ 582 bus_read_1((res), (offset)) 583 584#define ATA_INW(res, offset) \ 585 bus_read_2((res), (offset)) 586#define ATA_INL(res, offset) \ 587 bus_read_4((res), (offset)) 588#define ATA_INSW(res, offset, addr, count) \ 589 bus_read_multi_2((res), (offset), (addr), (count)) 590#define ATA_INSW_STRM(res, offset, addr, count) \ 591 bus_read_multi_stream_2((res), (offset), (addr), (count)) 592#define ATA_INSL(res, offset, addr, count) \ 593 bus_read_multi_4((res), (offset), (addr), (count)) 594#define ATA_INSL_STRM(res, offset, addr, count) \ 595 bus_read_multi_stream_4((res), (offset), (addr), (count)) 596#define ATA_OUTB(res, offset, value) \ 597 bus_write_1((res), (offset), (value)) 598#define ATA_OUTW(res, offset, value) \ 599 bus_write_2((res), (offset), (value)) 600#define ATA_OUTL(res, offset, value) \ 601 bus_write_4((res), (offset), (value)) 602#define ATA_OUTSW(res, offset, addr, count) \ 603 bus_write_multi_2((res), (offset), (addr), (count)) 604#define ATA_OUTSW_STRM(res, offset, addr, count) \ 605 bus_write_multi_stream_2((res), (offset), (addr), (count)) 606#define ATA_OUTSL(res, offset, addr, count) \ 607 bus_write_multi_4((res), (offset), (addr), (count)) 608#define ATA_OUTSL_STRM(res, offset, addr, count) \ 609 bus_write_multi_stream_4((res), (offset), (addr), (count)) 610 611#define ATA_IDX_INB(ch, idx) \ 612 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 613 614#define ATA_IDX_INW(ch, idx) \ 615 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 616 617#define ATA_IDX_INL(ch, idx) \ 618 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 619 620#define ATA_IDX_INSW(ch, idx, addr, count) \ 621 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 622 623#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 624 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 625 626#define ATA_IDX_INSL(ch, idx, addr, count) \ 627 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 628 629#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 630 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 631 632#define ATA_IDX_OUTB(ch, idx, value) \ 633 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 634 635#define ATA_IDX_OUTW(ch, idx, value) \ 636 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 637 638#define ATA_IDX_OUTL(ch, idx, value) \ 639 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 640 641#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 642 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 643 644#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 645 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 646 647#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 648 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 649 650#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 651 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 652