ata-all.h revision 151002
1/*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 151002 2005-10-06 15:44:07Z sos $ 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0 /* (RW) data */ 33 34#define ATA_FEATURE 1 /* (W) feature */ 35#define ATA_F_DMA 0x01 /* enable DMA */ 36#define ATA_F_OVL 0x02 /* enable overlap */ 37 38#define ATA_COUNT 2 /* (W) sector count */ 39 40#define ATA_SECTOR 3 /* (RW) sector # */ 41#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 42#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 43#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 44#define ATA_D_LBA 0x40 /* use LBA addressing */ 45#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 46 47#define ATA_COMMAND 7 /* (W) command */ 48 49#define ATA_ERROR 8 /* (R) error */ 50#define ATA_E_ILI 0x01 /* illegal length */ 51#define ATA_E_NM 0x02 /* no media */ 52#define ATA_E_ABORT 0x04 /* command aborted */ 53#define ATA_E_MCR 0x08 /* media change request */ 54#define ATA_E_IDNF 0x10 /* ID not found */ 55#define ATA_E_MC 0x20 /* media changed */ 56#define ATA_E_UNC 0x40 /* uncorrectable data */ 57#define ATA_E_ICRC 0x80 /* UDMA crc error */ 58#define ATA_E_MASK 0x0f /* error mask */ 59#define ATA_SK_MASK 0xf0 /* sense key mask */ 60#define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ 61#define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ 62#define ATA_SK_NOT_READY 0x20 /* no access to drive */ 63#define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ 64#define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ 65#define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ 66#define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ 67#define ATA_SK_DATA_PROTECT 0x70 /* write protect */ 68#define ATA_SK_BLANK_CHECK 0x80 /* blank check */ 69#define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ 70#define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ 71#define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ 72#define ATA_SK_EQUAL 0xc0 /* equal */ 73#define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ 74#define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ 75#define ATA_SK_RESERVED 0xf0 76 77#define ATA_IREASON 9 /* (R) interrupt reason */ 78#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 79#define ATA_I_IN 0x02 /* read (1) | write (0) */ 80#define ATA_I_RELEASE 0x04 /* released bus (1) */ 81#define ATA_I_TAGMASK 0xf8 /* tag mask */ 82 83#define ATA_STATUS 10 /* (R) status */ 84#define ATA_ALTSTAT 11 /* (R) alternate status */ 85#define ATA_S_ERROR 0x01 /* error */ 86#define ATA_S_INDEX 0x02 /* index */ 87#define ATA_S_CORR 0x04 /* data corrected */ 88#define ATA_S_DRQ 0x08 /* data request */ 89#define ATA_S_DSC 0x10 /* drive seek completed */ 90#define ATA_S_SERVICE 0x10 /* drive needs service */ 91#define ATA_S_DWF 0x20 /* drive write fault */ 92#define ATA_S_DMA 0x20 /* DMA ready */ 93#define ATA_S_READY 0x40 /* drive ready */ 94#define ATA_S_BUSY 0x80 /* busy */ 95 96#define ATA_CONTROL 12 /* (W) control */ 97 98#define ATA_CTLOFFSET 0x206 /* control register offset */ 99#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 100#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 101#define ATA_A_IDS 0x02 /* disable interrupts */ 102#define ATA_A_RESET 0x04 /* RESET controller */ 103#define ATA_A_4BIT 0x08 /* 4 head bits */ 104#define ATA_A_HOB 0x80 /* High Order Byte enable */ 105 106/* SATA register defines */ 107#define ATA_SSTATUS 13 108#define ATA_SS_DET_MASK 0x0000000f 109#define ATA_SS_DET_NO_DEVICE 0x00000000 110#define ATA_SS_DET_DEV_PRESENT 0x00000001 111#define ATA_SS_DET_PHY_ONLINE 0x00000003 112#define ATA_SS_DET_PHY_OFFLINE 0x00000004 113 114#define ATA_SS_SPD_MASK 0x000000f0 115#define ATA_SS_SPD_NO_SPEED 0x00000000 116#define ATA_SS_SPD_GEN1 0x00000010 117#define ATA_SS_SPD_GEN2 0x00000020 118 119#define ATA_SS_IPM_MASK 0x00000f00 120#define ATA_SS_IPM_NO_DEVICE 0x00000000 121#define ATA_SS_IPM_ACTIVE 0x00000100 122#define ATA_SS_IPM_PARTIAL 0x00000200 123#define ATA_SS_IPM_SLUMBER 0x00000600 124 125#define ATA_SS_CONWELL_MASK \ 126 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 127#define ATA_SS_CONWELL_GEN1 \ 128 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 129#define ATA_SS_CONWELL_GEN2 \ 130 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 131 132#define ATA_SERROR 14 133#define ATA_SE_DATA_CORRECTED 0x00000001 134#define ATA_SE_COMM_CORRECTED 0x00000002 135#define ATA_SE_DATA_ERR 0x00000100 136#define ATA_SE_COMM_ERR 0x00000200 137#define ATA_SE_PROT_ERR 0x00000400 138#define ATA_SE_HOST_ERR 0x00000800 139#define ATA_SE_PHY_CHANGED 0x00010000 140#define ATA_SE_PHY_IERROR 0x00020000 141#define ATA_SE_COMM_WAKE 0x00040000 142#define ATA_SE_DECODE_ERR 0x00080000 143#define ATA_SE_PARITY_ERR 0x00100000 144#define ATA_SE_CRC_ERR 0x00200000 145#define ATA_SE_HANDSHAKE_ERR 0x00400000 146#define ATA_SE_LINKSEQ_ERR 0x00800000 147#define ATA_SE_TRANSPORT_ERR 0x01000000 148#define ATA_SE_UNKNOWN_FIS 0x02000000 149 150#define ATA_SCONTROL 15 151#define ATA_SC_DET_MASK 0x0000000f 152#define ATA_SC_DET_IDLE 0x00000000 153#define ATA_SC_DET_RESET 0x00000001 154#define ATA_SC_DET_DISABLE 0x00000004 155 156#define ATA_SC_SPD_MASK 0x000000f0 157#define ATA_SC_SPD_NO_SPEED 0x00000000 158#define ATA_SC_SPD_SPEED_GEN1 0x00000010 159#define ATA_SC_SPD_SPEED_GEN2 0x00000020 160 161#define ATA_SC_IPM_MASK 0x00000f00 162#define ATA_SC_IPM_NONE 0x00000000 163#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 164#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 165 166#define ATA_SACTIVE 16 167 168/* SATA AHCI v1.0 register defines */ 169#define ATA_AHCI_CAP 0x00 170#define ATA_AHCI_NPMASK 0x1f 171 172#define ATA_AHCI_GHC 0x04 173#define ATA_AHCI_GHC_AE 0x80000000 174#define ATA_AHCI_GHC_IE 0x00000002 175#define ATA_AHCI_GHC_HR 0x80000001 176 177#define ATA_AHCI_IS 0x08 178#define ATA_AHCI_PI 0x0c 179#define ATA_AHCI_VS 0x10 180 181#define ATA_AHCI_OFFSET 0x80 182 183#define ATA_AHCI_P_CLB 0x100 184#define ATA_AHCI_P_CLBU 0x104 185#define ATA_AHCI_P_FB 0x108 186#define ATA_AHCI_P_FBU 0x10c 187#define ATA_AHCI_P_IS 0x110 188#define ATA_AHCI_P_IE 0x114 189#define ATA_AHCI_P_IX_DHR 0x00000001 190#define ATA_AHCI_P_IX_PS 0x00000002 191#define ATA_AHCI_P_IX_DS 0x00000004 192#define ATA_AHCI_P_IX_SDB 0x00000008 193#define ATA_AHCI_P_IX_UF 0x00000010 194#define ATA_AHCI_P_IX_DP 0x00000020 195#define ATA_AHCI_P_IX_PC 0x00000040 196#define ATA_AHCI_P_IX_DI 0x00000080 197 198#define ATA_AHCI_P_IX_PRC 0x00400000 199#define ATA_AHCI_P_IX_IPM 0x00800000 200#define ATA_AHCI_P_IX_OF 0x01000000 201#define ATA_AHCI_P_IX_INF 0x04000000 202#define ATA_AHCI_P_IX_IF 0x08000000 203#define ATA_AHCI_P_IX_HBD 0x10000000 204#define ATA_AHCI_P_IX_HBF 0x20000000 205#define ATA_AHCI_P_IX_TFE 0x40000000 206#define ATA_AHCI_P_IX_CPD 0x80000000 207 208#define ATA_AHCI_P_CMD 0x118 209#define ATA_AHCI_P_CMD_ST 0x00000001 210#define ATA_AHCI_P_CMD_SUD 0x00000002 211#define ATA_AHCI_P_CMD_POD 0x00000004 212#define ATA_AHCI_P_CMD_CLO 0x00000008 213#define ATA_AHCI_P_CMD_FRE 0x00000010 214#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 215#define ATA_AHCI_P_CMD_ISS 0x00002000 216#define ATA_AHCI_P_CMD_FR 0x00004000 217#define ATA_AHCI_P_CMD_CR 0x00008000 218#define ATA_AHCI_P_CMD_CPS 0x00010000 219#define ATA_AHCI_P_CMD_PMA 0x00020000 220#define ATA_AHCI_P_CMD_HPCP 0x00040000 221#define ATA_AHCI_P_CMD_ISP 0x00080000 222#define ATA_AHCI_P_CMD_CPD 0x00100000 223#define ATA_AHCI_P_CMD_ATAPI 0x01000000 224#define ATA_AHCI_P_CMD_DLAE 0x02000000 225#define ATA_AHCI_P_CMD_ALPE 0x04000000 226#define ATA_AHCI_P_CMD_ASP 0x08000000 227#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 228#define ATA_AHCI_P_CMD_NOOP 0x00000000 229#define ATA_AHCI_P_CMD_ACTIVE 0x10000000 230#define ATA_AHCI_P_CMD_PARTIAL 0x20000000 231#define ATA_AHCI_P_CMD_SLUMPER 0x60000000 232 233#define ATA_AHCI_P_TFD 0x120 234#define ATA_AHCI_P_SIG 0x124 235#define ATA_AHCI_P_SSTS 0x128 236#define ATA_AHCI_P_SCTL 0x12c 237#define ATA_AHCI_P_SERR 0x130 238#define ATA_AHCI_P_SACT 0x134 239#define ATA_AHCI_P_CI 0x138 240 241#define ATA_AHCI_CL_SIZE 32 242#define ATA_AHCI_CL_OFFSET 0 243#define ATA_AHCI_FB_OFFSET 1024 244#define ATA_AHCI_CT_OFFSET 1024+256 245#define ATA_AHCI_CT_SG_OFFSET 128 246#define ATA_AHCI_CT_SIZE 256 247 248/* DMA register defines */ 249#define ATA_DMA_ENTRIES 256 250#define ATA_DMA_EOT 0x80000000 251 252#define ATA_BMCMD_PORT 17 253#define ATA_BMCMD_START_STOP 0x01 254#define ATA_BMCMD_WRITE_READ 0x08 255 256#define ATA_BMDEVSPEC_0 18 257#define ATA_BMSTAT_PORT 19 258#define ATA_BMSTAT_ACTIVE 0x01 259#define ATA_BMSTAT_ERROR 0x02 260#define ATA_BMSTAT_INTERRUPT 0x04 261#define ATA_BMSTAT_MASK 0x07 262#define ATA_BMSTAT_DMA_MASTER 0x20 263#define ATA_BMSTAT_DMA_SLAVE 0x40 264#define ATA_BMSTAT_DMA_SIMPLEX 0x80 265 266#define ATA_BMDEVSPEC_1 20 267#define ATA_BMDTP_PORT 21 268 269#define ATA_IDX_ADDR 22 270#define ATA_IDX_DATA 23 271#define ATA_MAX_RES 24 272 273/* misc defines */ 274#define ATA_PRIMARY 0x1f0 275#define ATA_SECONDARY 0x170 276#define ATA_PC98_BANK 0x432 277#define ATA_IOSIZE 0x08 278#define ATA_PC98_IOSIZE 0x10 279#define ATA_CTLIOSIZE 0x01 280#define ATA_BMIOSIZE 0x08 281#define ATA_PC98_BANKIOSIZE 0x01 282#define ATA_IOADDR_RID 0 283#define ATA_CTLADDR_RID 1 284#define ATA_BMADDR_RID 0x20 285#define ATA_PC98_CTLADDR_RID 8 286#define ATA_PC98_BANKADDR_RID 9 287#define ATA_IRQ_RID 0 288#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 289#define ATA_CFA_MAGIC 0x848A 290#define ATAPI_MAGIC_LSB 0x14 291#define ATAPI_MAGIC_MSB 0xeb 292#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 293#define ATAPI_P_WRITE (ATA_S_DRQ) 294#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 295#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 296#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 297#define ATAPI_P_ABORT 0 298#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 299#define ATA_OP_CONTINUES 0 300#define ATA_OP_FINISHED 1 301#define ATA_MAX_28BIT_LBA 268435455 302 303/* ATAPI request sense structure */ 304struct atapi_sense { 305 u_int8_t error_code :7; /* current or deferred errors */ 306 u_int8_t valid :1; /* follows ATAPI spec */ 307 u_int8_t segment; /* Segment number */ 308 u_int8_t sense_key :4; /* sense key */ 309 u_int8_t reserved2_4 :1; /* reserved */ 310 u_int8_t ili :1; /* incorrect length indicator */ 311 u_int8_t eom :1; /* end of medium */ 312 u_int8_t filemark :1; /* filemark */ 313 u_int32_t cmd_info __packed; /* cmd information */ 314 u_int8_t sense_length; /* additional sense len (n-7) */ 315 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ 316 u_int8_t asc; /* additional sense code */ 317 u_int8_t ascq; /* additional sense code qual */ 318 u_int8_t replaceable_unit_code; /* replaceable unit code */ 319 u_int8_t sk_specific :7; /* sense key specific */ 320 u_int8_t sksv :1; /* sense key specific info OK */ 321 u_int8_t sk_specific1; /* sense key specific */ 322 u_int8_t sk_specific2; /* sense key specific */ 323}; 324 325/* structure used for composite atomic operations */ 326struct ata_composite { 327 struct mtx lock; /* control lock */ 328 u_int32_t rd_needed; /* needed read subdisks */ 329 u_int32_t rd_done; /* done read subdisks */ 330 u_int32_t wr_needed; /* needed write subdisks */ 331 u_int32_t wr_depend; /* write depends on subdisks */ 332 u_int32_t wr_done; /* done write subdisks */ 333 struct ata_request *request[32]; /* size must match maps above */ 334 caddr_t data_1; 335 caddr_t data_2; 336}; 337 338/* structure used to queue an ATA/ATAPI request */ 339struct ata_request { 340 device_t dev; /* device handle */ 341 union { 342 struct { 343 u_int8_t command; /* command reg */ 344 u_int16_t feature; /* feature reg */ 345 u_int16_t count; /* count reg */ 346 u_int64_t lba; /* lba reg */ 347 } ata; 348 struct { 349 u_int8_t ccb[16]; /* ATAPI command block */ 350 struct atapi_sense sense_data; /* ATAPI request sense data */ 351 u_int8_t sense_key; /* ATAPI request sense key */ 352 u_int8_t sense_cmd; /* ATAPI saved command */ 353 } atapi; 354 } u; 355 u_int32_t bytecount; /* bytes to transfer */ 356 u_int32_t transfersize; /* bytes pr transfer */ 357 caddr_t data; /* pointer to data buf */ 358 int flags; 359#define ATA_R_CONTROL 0x00000001 360#define ATA_R_READ 0x00000002 361#define ATA_R_WRITE 0x00000004 362#define ATA_R_ATAPI 0x00000008 363#define ATA_R_DMA 0x00000010 364#define ATA_R_QUIET 0x00000020 365#define ATA_R_TIMEOUT 0x00000040 366 367#define ATA_R_ORDERED 0x00000100 368#define ATA_R_AT_HEAD 0x00000200 369#define ATA_R_REQUEUE 0x00000400 370#define ATA_R_THREAD 0x00000800 371#define ATA_R_DIRECT 0x00001000 372 373#define ATA_R_DEBUG 0x10000000 374 375 u_int8_t status; /* ATA status */ 376 u_int8_t error; /* ATA error */ 377 u_int8_t dmastat; /* DMA status */ 378 u_int32_t donecount; /* bytes transferred */ 379 int result; /* result error code */ 380 void (*callback)(struct ata_request *request); 381 struct sema done; /* request done sema */ 382 int retries; /* retry count */ 383 int timeout; /* timeout for this cmd */ 384 struct callout callout; /* callout management */ 385 struct task task; /* task management */ 386 struct bio *bio; /* bio for this request */ 387 int this; /* this request ID */ 388 struct ata_composite *composite; /* for composite atomic ops */ 389 void *driver; /* driver specific */ 390 TAILQ_ENTRY(ata_request) chain; /* list management */ 391}; 392 393/* define this for debugging request processing */ 394#if 0 395#define ATA_DEBUG_RQ(request, string) \ 396 { \ 397 if (request->flags & ATA_R_DEBUG) \ 398 device_printf(request->dev, "req=%p %s " string "\n", \ 399 request, ata_cmd2str(request)); \ 400 } 401#else 402#define ATA_DEBUG_RQ(request, string) 403#endif 404 405 406/* structure describing an ATA/ATAPI device */ 407struct ata_device { 408 device_t dev; /* device handle */ 409 int unit; /* physical unit */ 410#define ATA_MASTER 0x00 411#define ATA_SLAVE 0x10 412 413 struct ata_params param; /* ata param structure */ 414 int mode; /* current transfermode */ 415 u_int32_t max_iosize; /* max IO size */ 416 int cmd; /* last cmd executed */ 417 int flags; 418#define ATA_D_USE_CHS 0x0001 419#define ATA_D_MEDIA_CHANGED 0x0002 420#define ATA_D_ENC_PRESENT 0x0004 421#define ATA_D_48BIT_ACTIVE 0x0008 422}; 423 424/* structure for holding DMA Physical Region Descriptors (PRD) entries */ 425struct ata_dma_prdentry { 426 u_int32_t addr; 427 u_int32_t count; 428}; 429 430/* structure used by the setprd function */ 431struct ata_dmasetprd_args { 432 void *dmatab; 433 int nsegs; 434 int error; 435}; 436 437/* structure holding DMA related information */ 438struct ata_dma { 439 bus_dma_tag_t dmatag; /* parent DMA tag */ 440 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 441 bus_dmamap_t sg_map; /* SG list DMA map */ 442 void *sg; /* DMA transfer table */ 443 bus_addr_t sg_bus; /* bus address of dmatab */ 444 bus_dma_tag_t data_tag; /* data DMA tag */ 445 bus_dmamap_t data_map; /* data DMA map */ 446 bus_dma_tag_t work_tag; /* workspace DMA tag */ 447 bus_dmamap_t work_map; /* workspace DMA map */ 448 u_int8_t *work; /* workspace */ 449 bus_addr_t work_bus; /* bus address of dmatab */ 450 451 u_int32_t alignment; /* DMA SG list alignment */ 452 u_int32_t boundary; /* DMA SG list boundary */ 453 u_int32_t segsize; /* DMA SG list segment size */ 454 u_int32_t max_iosize; /* DMA data max IO size */ 455 u_int32_t cur_iosize; /* DMA data current IO size */ 456 int flags; 457#define ATA_DMA_READ 0x01 /* transaction is a read */ 458#define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */ 459#define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */ 460 461 void (*alloc)(device_t dev); 462 void (*free)(device_t dev); 463 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 464 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs); 465 int (*unload)(device_t dev); 466 int (*start)(device_t dev); 467 int (*stop)(device_t dev); 468 void (*reset)(device_t dev); 469}; 470 471/* structure holding lowlevel functions */ 472struct ata_lowlevel { 473 int (*begin_transaction)(struct ata_request *request); 474 int (*end_transaction)(struct ata_request *request); 475 int (*command)(struct ata_request *request); 476}; 477 478/* structure holding resources for an ATA channel */ 479struct ata_resource { 480 struct resource *res; 481 int offset; 482}; 483 484/* structure describing an ATA channel */ 485struct ata_channel { 486 device_t dev; /* device handle */ 487 int unit; /* physical channel */ 488 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 489 struct resource *r_irq; /* interrupt of this channel */ 490 void *ih; /* interrupt handle */ 491 struct ata_lowlevel hw; /* lowlevel HW functions */ 492 struct ata_dma *dma; /* DMA data / functions */ 493 int flags; /* channel flags */ 494#define ATA_NO_SLAVE 0x01 495#define ATA_USE_16BIT 0x02 496#define ATA_ATAPI_DMA_RO 0x04 497#define ATA_NO_48BIT_DMA 0x08 498 499 int devices; /* what is present */ 500#define ATA_ATA_MASTER 0x01 501#define ATA_ATA_SLAVE 0x02 502#define ATA_ATAPI_MASTER 0x04 503#define ATA_ATAPI_SLAVE 0x08 504 505 struct mtx state_mtx; /* state lock */ 506 int state; /* ATA channel state */ 507#define ATA_IDLE 0x0000 508#define ATA_ACTIVE 0x0001 509#define ATA_STALL_QUEUE 0x0002 510 511 struct mtx queue_mtx; /* queue lock */ 512 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 513 struct ata_request *freezepoint; /* composite freezepoint */ 514 struct ata_request *running; /* currently running request */ 515}; 516 517/* disk bay/enclosure related */ 518#define ATA_LED_OFF 0x00 519#define ATA_LED_RED 0x01 520#define ATA_LED_GREEN 0x02 521#define ATA_LED_ORANGE 0x03 522#define ATA_LED_MASK 0x03 523 524/* externs */ 525extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 526extern devclass_t ata_devclass; 527extern int ata_wc; 528 529/* public prototypes */ 530/* ata-all.c: */ 531int ata_probe(device_t dev); 532int ata_attach(device_t dev); 533int ata_detach(device_t dev); 534int ata_reinit(device_t dev); 535int ata_suspend(device_t dev); 536int ata_resume(device_t dev); 537int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data); 538int ata_identify(device_t dev); 539void ata_default_registers(device_t dev); 540void ata_modify_if_48bit(struct ata_request *request); 541void ata_udelay(int interval); 542char *ata_mode2str(int mode); 543int ata_pmode(struct ata_params *ap); 544int ata_wmode(struct ata_params *ap); 545int ata_umode(struct ata_params *ap); 546int ata_limit_mode(device_t dev, int mode, int maxmode); 547 548/* ata-queue.c: */ 549int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 550int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 551void ata_queue_request(struct ata_request *request); 552void ata_start(device_t dev); 553void ata_finish(struct ata_request *request); 554void ata_timeout(struct ata_request *); 555void ata_catch_inflight(device_t dev); 556void ata_fail_requests(device_t dev); 557char *ata_cmd2str(struct ata_request *request); 558 559/* ata-lowlevel.c: */ 560void ata_generic_hw(device_t dev); 561void ata_generic_reset(device_t dev); 562int ata_generic_command(struct ata_request *request); 563 564/* macros for alloc/free of struct ata_request */ 565extern uma_zone_t ata_request_zone; 566#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 567#define ata_free_request(request) uma_zfree(ata_request_zone, request) 568 569/* macros for alloc/free of struct ata_composite */ 570extern uma_zone_t ata_composite_zone; 571#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 572#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 573 574MALLOC_DECLARE(M_ATA); 575 576/* misc newbus defines */ 577#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 578 579/* macros to hide busspace uglyness */ 580#define ATA_INB(res, offset) \ 581 bus_space_read_1(rman_get_bustag((res)), \ 582 rman_get_bushandle((res)), (offset)) 583 584#define ATA_INW(res, offset) \ 585 bus_space_read_2(rman_get_bustag((res)), \ 586 rman_get_bushandle((res)), (offset)) 587#define ATA_INL(res, offset) \ 588 bus_space_read_4(rman_get_bustag((res)), \ 589 rman_get_bushandle((res)), (offset)) 590#define ATA_INSW(res, offset, addr, count) \ 591 bus_space_read_multi_2(rman_get_bustag((res)), \ 592 rman_get_bushandle((res)), \ 593 (offset), (addr), (count)) 594#define ATA_INSW_STRM(res, offset, addr, count) \ 595 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 596 rman_get_bushandle((res)), \ 597 (offset), (addr), (count)) 598#define ATA_INSL(res, offset, addr, count) \ 599 bus_space_read_multi_4(rman_get_bustag((res)), \ 600 rman_get_bushandle((res)), \ 601 (offset), (addr), (count)) 602#define ATA_INSL_STRM(res, offset, addr, count) \ 603 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 604 rman_get_bushandle((res)), \ 605 (offset), (addr), (count)) 606#define ATA_OUTB(res, offset, value) \ 607 bus_space_write_1(rman_get_bustag((res)), \ 608 rman_get_bushandle((res)), (offset), (value)) 609#define ATA_OUTW(res, offset, value) \ 610 bus_space_write_2(rman_get_bustag((res)), \ 611 rman_get_bushandle((res)), (offset), (value)) 612#define ATA_OUTL(res, offset, value) \ 613 bus_space_write_4(rman_get_bustag((res)), \ 614 rman_get_bushandle((res)), (offset), (value)) 615#define ATA_OUTSW(res, offset, addr, count) \ 616 bus_space_write_multi_2(rman_get_bustag((res)), \ 617 rman_get_bushandle((res)), \ 618 (offset), (addr), (count)) 619#define ATA_OUTSW_STRM(res, offset, addr, count) \ 620 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 621 rman_get_bushandle((res)), \ 622 (offset), (addr), (count)) 623#define ATA_OUTSL(res, offset, addr, count) \ 624 bus_space_write_multi_4(rman_get_bustag((res)), \ 625 rman_get_bushandle((res)), \ 626 (offset), (addr), (count)) 627#define ATA_OUTSL_STRM(res, offset, addr, count) \ 628 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 629 rman_get_bushandle((res)), \ 630 (offset), (addr), (count)) 631 632#define ATA_IDX_INB(ch, idx) \ 633 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 634 635#define ATA_IDX_INW(ch, idx) \ 636 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 637 638#define ATA_IDX_INL(ch, idx) \ 639 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 640 641#define ATA_IDX_INSW(ch, idx, addr, count) \ 642 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 643 644#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 645 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 646 647#define ATA_IDX_INSL(ch, idx, addr, count) \ 648 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 649 650#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 651 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 652 653#define ATA_IDX_OUTB(ch, idx, value) \ 654 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 655 656#define ATA_IDX_OUTW(ch, idx, value) \ 657 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 658 659#define ATA_IDX_OUTL(ch, idx, value) \ 660 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 661 662#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 663 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 664 665#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 666 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 667 668#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 669 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 670 671#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 672 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 673