ata-all.h revision 145273
1/*- 2 * Copyright (c) 1998 - 2005 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 145273 2005-04-19 12:33:26Z sos $ 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0 /* (RW) data */ 33 34#define ATA_FEATURE 1 /* (W) feature */ 35#define ATA_F_DMA 0x01 /* enable DMA */ 36#define ATA_F_OVL 0x02 /* enable overlap */ 37 38#define ATA_COUNT 2 /* (W) sector count */ 39 40#define ATA_SECTOR 3 /* (RW) sector # */ 41#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 42#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 43#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 44#define ATA_D_LBA 0x40 /* use LBA addressing */ 45#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 46 47#define ATA_COMMAND 7 /* (W) command */ 48 49#define ATA_ERROR 8 /* (R) error */ 50#define ATA_E_ILI 0x01 /* illegal length */ 51#define ATA_E_NM 0x02 /* no media */ 52#define ATA_E_ABORT 0x04 /* command aborted */ 53#define ATA_E_MCR 0x08 /* media change request */ 54#define ATA_E_IDNF 0x10 /* ID not found */ 55#define ATA_E_MC 0x20 /* media changed */ 56#define ATA_E_UNC 0x40 /* uncorrectable data */ 57#define ATA_E_ICRC 0x80 /* UDMA crc error */ 58#define ATA_E_MASK 0x0f /* error mask */ 59#define ATA_SK_MASK 0xf0 /* sense key mask */ 60#define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ 61#define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ 62#define ATA_SK_NOT_READY 0x20 /* no access to drive */ 63#define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ 64#define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ 65#define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ 66#define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ 67#define ATA_SK_DATA_PROTECT 0x70 /* write protect */ 68#define ATA_SK_BLANK_CHECK 0x80 /* blank check */ 69#define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ 70#define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ 71#define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ 72#define ATA_SK_EQUAL 0xc0 /* equal */ 73#define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ 74#define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ 75#define ATA_SK_RESERVED 0xf0 76 77#define ATA_IREASON 9 /* (R) interrupt reason */ 78#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 79#define ATA_I_IN 0x02 /* read (1) | write (0) */ 80#define ATA_I_RELEASE 0x04 /* released bus (1) */ 81#define ATA_I_TAGMASK 0xf8 /* tag mask */ 82 83#define ATA_STATUS 10 /* (R) status */ 84#define ATA_ALTSTAT 11 /* (R) alternate status */ 85#define ATA_S_ERROR 0x01 /* error */ 86#define ATA_S_INDEX 0x02 /* index */ 87#define ATA_S_CORR 0x04 /* data corrected */ 88#define ATA_S_DRQ 0x08 /* data request */ 89#define ATA_S_DSC 0x10 /* drive seek completed */ 90#define ATA_S_SERVICE 0x10 /* drive needs service */ 91#define ATA_S_DWF 0x20 /* drive write fault */ 92#define ATA_S_DMA 0x20 /* DMA ready */ 93#define ATA_S_READY 0x40 /* drive ready */ 94#define ATA_S_BUSY 0x80 /* busy */ 95 96#define ATA_CONTROL 12 /* (W) control */ 97 98#define ATA_CTLOFFSET 0x206 /* control register offset */ 99#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 100#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 101#define ATA_A_IDS 0x02 /* disable interrupts */ 102#define ATA_A_RESET 0x04 /* RESET controller */ 103#define ATA_A_4BIT 0x08 /* 4 head bits */ 104#define ATA_A_HOB 0x80 /* High Order Byte enable */ 105 106/* SATA register defines */ 107#define ATA_SSTATUS 13 108#define ATA_SS_DET_MASK 0x0000000f 109#define ATA_SS_DET_NO_DEVICE 0x00000000 110#define ATA_SS_DET_DEV_PRESENT 0x00000001 111#define ATA_SS_DET_PHY_ONLINE 0x00000003 112#define ATA_SS_DET_PHY_OFFLINE 0x00000004 113 114#define ATA_SS_SPD_MASK 0x000000f0 115#define ATA_SS_SPD_NO_SPEED 0x00000000 116#define ATA_SS_SPD_GEN1 0x00000010 117#define ATA_SS_SPD_GEN2 0x00000020 118 119#define ATA_SS_IPM_MASK 0x00000f00 120#define ATA_SS_IPM_NO_DEVICE 0x00000000 121#define ATA_SS_IPM_ACTIVE 0x00000100 122#define ATA_SS_IPM_PARTIAL 0x00000200 123#define ATA_SS_IPM_SLUMBER 0x00000600 124 125#define ATA_SS_CONWELL_MASK \ 126 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK) 127#define ATA_SS_CONWELL_GEN1 \ 128 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE) 129#define ATA_SS_CONWELL_GEN2 \ 130 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE) 131 132#define ATA_SERROR 14 133#define ATA_SE_DATA_CORRECTED 0x00000001 134#define ATA_SE_COMM_CORRECTED 0x00000002 135#define ATA_SE_DATA_ERR 0x00000100 136#define ATA_SE_COMM_ERR 0x00000200 137#define ATA_SE_PROT_ERR 0x00000400 138#define ATA_SE_HOST_ERR 0x00000800 139#define ATA_SE_PHY_CHANGED 0x00010000 140#define ATA_SE_PHY_IERROR 0x00020000 141#define ATA_SE_COMM_WAKE 0x00040000 142#define ATA_SE_DECODE_ERR 0x00080000 143#define ATA_SE_PARITY_ERR 0x00100000 144#define ATA_SE_CRC_ERR 0x00200000 145#define ATA_SE_HANDSHAKE_ERR 0x00400000 146#define ATA_SE_LINKSEQ_ERR 0x00800000 147#define ATA_SE_TRANSPORT_ERR 0x01000000 148#define ATA_SE_UNKNOWN_FIS 0x02000000 149 150#define ATA_SCONTROL 15 151#define ATA_SC_DET_MASK 0x0000000f 152#define ATA_SC_DET_IDLE 0x00000000 153#define ATA_SC_DET_RESET 0x00000001 154#define ATA_SC_DET_DISABLE 0x00000004 155 156#define ATA_SC_SPD_MASK 0x000000f0 157#define ATA_SC_SPD_NO_SPEED 0x00000000 158#define ATA_SC_SPD_SPEED_GEN1 0x00000010 159#define ATA_SC_SPD_SPEED_GEN2 0x00000020 160 161#define ATA_SC_IPM_MASK 0x00000f00 162#define ATA_SC_IPM_NONE 0x00000000 163#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 164#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 165 166/* DMA register defines */ 167#define ATA_DMA_ENTRIES 256 168#define ATA_DMA_EOT 0x80000000 169 170#define ATA_BMCMD_PORT 16 171#define ATA_BMCMD_START_STOP 0x01 172#define ATA_BMCMD_WRITE_READ 0x08 173 174#define ATA_BMDEVSPEC_0 17 175#define ATA_BMSTAT_PORT 18 176#define ATA_BMSTAT_ACTIVE 0x01 177#define ATA_BMSTAT_ERROR 0x02 178#define ATA_BMSTAT_INTERRUPT 0x04 179#define ATA_BMSTAT_MASK 0x07 180#define ATA_BMSTAT_DMA_MASTER 0x20 181#define ATA_BMSTAT_DMA_SLAVE 0x40 182#define ATA_BMSTAT_DMA_SIMPLEX 0x80 183 184#define ATA_BMDEVSPEC_1 19 185#define ATA_BMDTP_PORT 20 186 187#define ATA_IDX_ADDR 21 188#define ATA_IDX_DATA 22 189#define ATA_MAX_RES 23 190 191/* misc defines */ 192#define ATA_PRIMARY 0x1f0 193#define ATA_SECONDARY 0x170 194#define ATA_PC98_BANK 0x432 195#define ATA_IOSIZE 0x08 196#define ATA_PC98_IOSIZE 0x10 197#define ATA_CTLIOSIZE 0x01 198#define ATA_BMIOSIZE 0x08 199#define ATA_PC98_BANKIOSIZE 0x01 200#define ATA_IOADDR_RID 0 201#define ATA_CTLADDR_RID 1 202#define ATA_BMADDR_RID 0x20 203#define ATA_PC98_CTLADDR_RID 8 204#define ATA_PC98_BANKADDR_RID 9 205#define ATA_IRQ_RID 0 206#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) 207#define ATA_CFA_MAGIC 0x848A 208#define ATAPI_MAGIC_LSB 0x14 209#define ATAPI_MAGIC_MSB 0xeb 210#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 211#define ATAPI_P_WRITE (ATA_S_DRQ) 212#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 213#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 214#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 215#define ATAPI_P_ABORT 0 216#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 217#define ATA_OP_CONTINUES 0 218#define ATA_OP_FINISHED 1 219#define ATA_MAX_28BIT_LBA 268435455 220 221/* ATAPI request sense structure */ 222struct atapi_sense { 223 u_int8_t error_code :7; /* current or deferred errors */ 224 u_int8_t valid :1; /* follows ATAPI spec */ 225 u_int8_t segment; /* Segment number */ 226 u_int8_t sense_key :4; /* sense key */ 227 u_int8_t reserved2_4 :1; /* reserved */ 228 u_int8_t ili :1; /* incorrect length indicator */ 229 u_int8_t eom :1; /* end of medium */ 230 u_int8_t filemark :1; /* filemark */ 231 u_int32_t cmd_info __packed; /* cmd information */ 232 u_int8_t sense_length; /* additional sense len (n-7) */ 233 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ 234 u_int8_t asc; /* additional sense code */ 235 u_int8_t ascq; /* additional sense code qual */ 236 u_int8_t replaceable_unit_code; /* replaceable unit code */ 237 u_int8_t sk_specific :7; /* sense key specific */ 238 u_int8_t sksv :1; /* sense key specific info OK */ 239 u_int8_t sk_specific1; /* sense key specific */ 240 u_int8_t sk_specific2; /* sense key specific */ 241}; 242 243/* structure used for composite atomic operations */ 244struct ata_composite { 245 struct mtx lock; /* control lock */ 246 u_int32_t rd_needed; /* needed read subdisks */ 247 u_int32_t rd_done; /* done read subdisks */ 248 u_int32_t wr_needed; /* needed write subdisks */ 249 u_int32_t wr_depend; /* write depends on subdisks */ 250 u_int32_t wr_done; /* done write subdisks */ 251 struct ata_request *request[32]; /* size must match maps above */ 252 caddr_t data_1; 253 caddr_t data_2; 254}; 255 256/* structure used to queue an ATA/ATAPI request */ 257struct ata_request { 258 device_t dev; /* device handle */ 259 union { 260 struct { 261 u_int8_t command; /* command reg */ 262 u_int16_t feature; /* feature reg */ 263 u_int16_t count; /* count reg */ 264 u_int64_t lba; /* lba reg */ 265 } ata; 266 struct { 267 u_int8_t ccb[16]; /* ATAPI command block */ 268 struct atapi_sense sense_data; /* ATAPI request sense data */ 269 u_int8_t sense_key; /* ATAPI request sense key */ 270 u_int8_t sense_cmd; /* ATAPI saved command */ 271 } atapi; 272 } u; 273 u_int32_t bytecount; /* bytes to transfer */ 274 u_int32_t transfersize; /* bytes pr transfer */ 275 caddr_t data; /* pointer to data buf */ 276 int flags; 277#define ATA_R_CONTROL 0x00000001 278#define ATA_R_READ 0x00000002 279#define ATA_R_WRITE 0x00000004 280#define ATA_R_DMA 0x00000008 281 282#define ATA_R_ATAPI 0x00000010 283#define ATA_R_QUIET 0x00000020 284#define ATA_R_INTR_SEEN 0x00000040 285#define ATA_R_TIMEOUT 0x00000080 286 287#define ATA_R_ORDERED 0x00000100 288#define ATA_R_AT_HEAD 0x00000200 289#define ATA_R_REQUEUE 0x00000400 290#define ATA_R_THREAD 0x00000800 291#define ATA_R_DIRECT 0x00001000 292 293#define ATA_R_DEBUG 0x10000000 294 295 u_int8_t status; /* ATA status */ 296 u_int8_t error; /* ATA error */ 297 u_int8_t dmastat; /* DMA status */ 298 u_int32_t donecount; /* bytes transferred */ 299 int result; /* result error code */ 300 void (*callback)(struct ata_request *request); 301 struct sema done; /* request done sema */ 302 int retries; /* retry count */ 303 int timeout; /* timeout for this cmd */ 304 struct callout callout; /* callout management */ 305 struct task task; /* task management */ 306 struct bio *bio; /* bio for this request */ 307 int this; /* this request ID */ 308 struct ata_composite *composite; /* for composite atomic ops */ 309 void *driver; /* driver specific */ 310 TAILQ_ENTRY(ata_request) chain; /* list management */ 311}; 312 313/* define this for debugging request processing */ 314#if 0 315#define ATA_DEBUG_RQ(request, string) \ 316 { \ 317 if (request->flags & ATA_R_DEBUG) \ 318 device_printf(request->dev, "req=%p %s " string "\n", \ 319 request, ata_cmd2str(request)); \ 320 } 321#else 322#define ATA_DEBUG_RQ(request, string) 323#endif 324 325 326/* structure describing an ATA/ATAPI device */ 327struct ata_device { 328 device_t dev; /* device handle */ 329 int unit; /* physical unit */ 330#define ATA_MASTER 0x00 331#define ATA_SLAVE 0x10 332 333 struct ata_params param; /* ata param structure */ 334 int mode; /* current transfermode */ 335 u_int32_t max_iosize; /* max IO size */ 336 int cmd; /* last cmd executed */ 337 int flags; 338#define ATA_D_USE_CHS 0x0001 339#define ATA_D_MEDIA_CHANGED 0x0002 340#define ATA_D_ENC_PRESENT 0x0004 341}; 342 343/* structure for holding DMA Physical Region Descriptors (PRD) entries */ 344struct ata_dma_prdentry { 345 u_int32_t addr; 346 u_int32_t count; 347}; 348 349/* structure used by the setprd function */ 350struct ata_dmasetprd_args { 351 void *dmatab; 352 int error; 353}; 354 355struct ata_channel {}; 356/* structure holding DMA related information */ 357struct ata_dma { 358 bus_dma_tag_t dmatag; /* parent DMA tag */ 359 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 360 bus_dmamap_t sg_map; /* SG list DMA map */ 361 void *sg; /* DMA transfer table */ 362 bus_addr_t sg_bus; /* bus address of dmatab */ 363 bus_dma_tag_t data_tag; /* data DMA tag */ 364 bus_dmamap_t data_map; /* data DMA map */ 365 bus_dma_tag_t work_tag; /* workspace DMA tag */ 366 bus_dmamap_t work_map; /* workspace DMA map */ 367 u_int8_t *work; /* workspace */ 368 bus_addr_t work_bus; /* bus address of dmatab */ 369 370 u_int32_t alignment; /* DMA engine alignment */ 371 u_int32_t boundary; /* DMA engine boundary */ 372 u_int32_t max_iosize; /* DMA engine max IO size */ 373 u_int32_t cur_iosize; /* DMA engine current IO size */ 374 int flags; 375#define ATA_DMA_READ 0x01 /* transaction is a read */ 376#define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */ 377#define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */ 378 379 void (*alloc)(struct ata_channel *ch); 380 void (*free)(struct ata_channel *ch); 381 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 382 int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir); 383 int (*unload)(struct ata_channel *ch); 384 int (*start)(struct ata_channel *ch); 385 int (*stop)(struct ata_channel *ch); 386}; 387 388/* structure holding lowlevel functions */ 389struct ata_lowlevel { 390 int (*begin_transaction)(struct ata_request *request); 391 int (*end_transaction)(struct ata_request *request); 392 void (*reset)(struct ata_channel *ch); 393 int (*command)(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature); 394}; 395 396/* structure holding resources for an ATA channel */ 397struct ata_resource { 398 struct resource *res; 399 int offset; 400}; 401 402/* structure describing an ATA channel */ 403struct ata_channel { 404 device_t dev; /* device handle */ 405 int unit; /* physical channel */ 406 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 407 struct resource *r_irq; /* interrupt of this channel */ 408 void *ih; /* interrupt handle */ 409 struct ata_lowlevel hw; /* lowlevel HW functions */ 410 struct ata_dma *dma; /* DMA data / functions */ 411 int flags; /* channel flags */ 412#define ATA_NO_SLAVE 0x01 413#define ATA_USE_16BIT 0x02 414#define ATA_ATAPI_DMA_RO 0x04 415#define ATA_48BIT_ACTIVE 0x08 416 417 int devices; /* what is present */ 418#define ATA_ATA_MASTER 0x01 419#define ATA_ATA_SLAVE 0x02 420#define ATA_ATAPI_MASTER 0x04 421#define ATA_ATAPI_SLAVE 0x08 422 423 struct mtx state_mtx; /* state lock */ 424 int state; /* ATA channel state */ 425#define ATA_IDLE 0x0000 426#define ATA_ACTIVE 0x0001 427#define ATA_STALL_QUEUE 0x0002 428#define ATA_TIMEOUT 0x0004 429 430 struct mtx queue_mtx; /* queue lock */ 431 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ 432 struct ata_request *freezepoint; /* composite freezepoint */ 433 struct ata_request *running; /* currently running request */ 434}; 435 436/* disk bay/enclosure related */ 437#define ATA_LED_OFF 0x00 438#define ATA_LED_RED 0x01 439#define ATA_LED_GREEN 0x02 440#define ATA_LED_ORANGE 0x03 441#define ATA_LED_MASK 0x03 442 443/* externs */ 444extern int (*ata_ioctl_func)(struct ata_cmd *iocmd); 445extern devclass_t ata_devclass; 446extern int ata_wc; 447 448/* public prototypes */ 449/* ata-all.c: */ 450int ata_probe(device_t dev); 451int ata_attach(device_t dev); 452int ata_detach(device_t dev); 453int ata_reinit(device_t dev); 454int ata_suspend(device_t dev); 455int ata_resume(device_t dev); 456void ata_default_registers(struct ata_channel *ch); 457void ata_udelay(int interval); 458char *ata_mode2str(int mode); 459int ata_pmode(struct ata_params *ap); 460int ata_wmode(struct ata_params *ap); 461int ata_umode(struct ata_params *ap); 462int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode); 463 464/* ata-queue.c: */ 465int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); 466int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); 467void ata_queue_request(struct ata_request *request); 468void ata_start(device_t dev); 469void ata_finish(struct ata_request *request); 470void ata_catch_inflight(struct ata_channel *ch); 471void ata_fail_requests(struct ata_channel *ch, device_t dev); 472char *ata_cmd2str(struct ata_request *request); 473 474/* ata-lowlevel.c: */ 475void ata_generic_hw(struct ata_channel *ch); 476int ata_generic_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature); 477int ata_getparam(device_t parent, struct ata_device *atadev, u_int8_t command); 478 479/* macros for alloc/free of struct ata_request */ 480extern uma_zone_t ata_request_zone; 481#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 482#define ata_free_request(request) uma_zfree(ata_request_zone, request) 483 484/* macros for alloc/free of struct ata_composite */ 485extern uma_zone_t ata_composite_zone; 486#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO) 487#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite) 488 489MALLOC_DECLARE(M_ATA); 490 491/* misc newbus defines */ 492#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 493 494/* macros to hide busspace uglyness */ 495#define ATA_INB(res, offset) \ 496 bus_space_read_1(rman_get_bustag((res)), \ 497 rman_get_bushandle((res)), (offset)) 498 499#define ATA_INW(res, offset) \ 500 bus_space_read_2(rman_get_bustag((res)), \ 501 rman_get_bushandle((res)), (offset)) 502#define ATA_INL(res, offset) \ 503 bus_space_read_4(rman_get_bustag((res)), \ 504 rman_get_bushandle((res)), (offset)) 505#define ATA_INSW(res, offset, addr, count) \ 506 bus_space_read_multi_2(rman_get_bustag((res)), \ 507 rman_get_bushandle((res)), \ 508 (offset), (addr), (count)) 509#define ATA_INSW_STRM(res, offset, addr, count) \ 510 bus_space_read_multi_stream_2(rman_get_bustag((res)), \ 511 rman_get_bushandle((res)), \ 512 (offset), (addr), (count)) 513#define ATA_INSL(res, offset, addr, count) \ 514 bus_space_read_multi_4(rman_get_bustag((res)), \ 515 rman_get_bushandle((res)), \ 516 (offset), (addr), (count)) 517#define ATA_INSL_STRM(res, offset, addr, count) \ 518 bus_space_read_multi_stream_4(rman_get_bustag((res)), \ 519 rman_get_bushandle((res)), \ 520 (offset), (addr), (count)) 521#define ATA_OUTB(res, offset, value) \ 522 bus_space_write_1(rman_get_bustag((res)), \ 523 rman_get_bushandle((res)), (offset), (value)) 524#define ATA_OUTW(res, offset, value) \ 525 bus_space_write_2(rman_get_bustag((res)), \ 526 rman_get_bushandle((res)), (offset), (value)) 527#define ATA_OUTL(res, offset, value) \ 528 bus_space_write_4(rman_get_bustag((res)), \ 529 rman_get_bushandle((res)), (offset), (value)) 530#define ATA_OUTSW(res, offset, addr, count) \ 531 bus_space_write_multi_2(rman_get_bustag((res)), \ 532 rman_get_bushandle((res)), \ 533 (offset), (addr), (count)) 534#define ATA_OUTSW_STRM(res, offset, addr, count) \ 535 bus_space_write_multi_stream_2(rman_get_bustag((res)), \ 536 rman_get_bushandle((res)), \ 537 (offset), (addr), (count)) 538#define ATA_OUTSL(res, offset, addr, count) \ 539 bus_space_write_multi_4(rman_get_bustag((res)), \ 540 rman_get_bushandle((res)), \ 541 (offset), (addr), (count)) 542#define ATA_OUTSL_STRM(res, offset, addr, count) \ 543 bus_space_write_multi_stream_4(rman_get_bustag((res)), \ 544 rman_get_bushandle((res)), \ 545 (offset), (addr), (count)) 546 547#define ATA_IDX_INB(ch, idx) \ 548 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 549 550#define ATA_IDX_INW(ch, idx) \ 551 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 552 553#define ATA_IDX_INL(ch, idx) \ 554 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 555 556#define ATA_IDX_INSW(ch, idx, addr, count) \ 557 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 558 559#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 560 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 561 562#define ATA_IDX_INSL(ch, idx, addr, count) \ 563 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 564 565#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 566 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 567 568#define ATA_IDX_OUTB(ch, idx, value) \ 569 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 570 571#define ATA_IDX_OUTW(ch, idx, value) \ 572 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 573 574#define ATA_IDX_OUTL(ch, idx, value) \ 575 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 576 577#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 578 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 579 580#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 581 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 582 583#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 584 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 585 586#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 587 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 588