1139749Simp/*- 223925Sgibbs * Aic7xxx register and scratch ram definitions. 323925Sgibbs * 495378Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 595378Sgibbs * Copyright (c) 2000-2001 Adaptec Inc. 623925Sgibbs * All rights reserved. 723925Sgibbs * 823925Sgibbs * Redistribution and use in source and binary forms, with or without 923925Sgibbs * modification, are permitted provided that the following conditions 1023925Sgibbs * are met: 1123925Sgibbs * 1. Redistributions of source code must retain the above copyright 1226997Sgibbs * notice, this list of conditions, and the following disclaimer, 1354211Sgibbs * without modification. 1495378Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1595378Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1695378Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1795378Sgibbs * including a substantially similar Disclaimer requirement for further 1895378Sgibbs * binary redistribution. 1995378Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2095378Sgibbs * of any contributors may be used to endorse or promote products derived 2195378Sgibbs * from this software without specific prior written permission. 2223925Sgibbs * 2354211Sgibbs * Alternatively, this software may be distributed under the terms of the 2495378Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2595378Sgibbs * Software Foundation. 2626997Sgibbs * 2795378Sgibbs * NO WARRANTY 2895378Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2995378Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3095378Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3195378Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3295378Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3323925Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3423925Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3595378Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3695378Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3795378Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3895378Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3923925Sgibbs * 4050477Speter * $FreeBSD$ 4123925Sgibbs */ 42123579SgibbsVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $" 4323925Sgibbs 4423925Sgibbs/* 4523925Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 4623925Sgibbs * firmware for the aic7xxx family of SCSI host adapters as well as to generate 4723925Sgibbs * a C header file for use in the kernel portion of the Aic7xxx driver. 4823925Sgibbs * 4923925Sgibbs * All page numbers refer to the Adaptec AIC-7770 Data Book available from 5023925Sgibbs * Adaptec's Technical Documents Department 1-800-934-2766 5123925Sgibbs */ 5223925Sgibbs 5323925Sgibbs/* 5423925Sgibbs * SCSI Sequence Control (p. 3-11). 5523925Sgibbs * Each bit, when set starts a specific SCSI sequence on the bus 5623925Sgibbs */ 5723925Sgibbsregister SCSISEQ { 5823925Sgibbs address 0x000 5923925Sgibbs access_mode RW 60102672Sgibbs field TEMODE 0x80 61102672Sgibbs field ENSELO 0x40 62102672Sgibbs field ENSELI 0x20 63102672Sgibbs field ENRSELI 0x10 64102672Sgibbs field ENAUTOATNO 0x08 65102672Sgibbs field ENAUTOATNI 0x04 66102672Sgibbs field ENAUTOATNP 0x02 67102672Sgibbs field SCSIRSTO 0x01 6823925Sgibbs} 6923925Sgibbs 7023925Sgibbs/* 7123925Sgibbs * SCSI Transfer Control 0 Register (pp. 3-13). 7223925Sgibbs * Controls the SCSI module data path. 7323925Sgibbs */ 7423925Sgibbsregister SXFRCTL0 { 7523925Sgibbs address 0x001 7623925Sgibbs access_mode RW 77102672Sgibbs field DFON 0x80 78102672Sgibbs field DFPEXP 0x40 79102672Sgibbs field FAST20 0x20 80102672Sgibbs field CLRSTCNT 0x10 81102672Sgibbs field SPIOEN 0x08 82102672Sgibbs field SCAMEN 0x04 83102672Sgibbs field CLRCHN 0x02 8423925Sgibbs} 8523925Sgibbs 8623925Sgibbs/* 8723925Sgibbs * SCSI Transfer Control 1 Register (pp. 3-14,15). 8823925Sgibbs * Controls the SCSI module data path. 8923925Sgibbs */ 9023925Sgibbsregister SXFRCTL1 { 9123925Sgibbs address 0x002 9223925Sgibbs access_mode RW 93102672Sgibbs field BITBUCKET 0x80 94102672Sgibbs field SWRAPEN 0x40 95102672Sgibbs field ENSPCHK 0x20 9623925Sgibbs mask STIMESEL 0x18 97102672Sgibbs field ENSTIMER 0x04 98102672Sgibbs field ACTNEGEN 0x02 99102672Sgibbs field STPWEN 0x01 /* Powered Termination */ 10023925Sgibbs} 10123925Sgibbs 10223925Sgibbs/* 10323925Sgibbs * SCSI Control Signal Read Register (p. 3-15). 10423925Sgibbs * Reads the actual state of the SCSI bus pins 10523925Sgibbs */ 10623925Sgibbsregister SCSISIGI { 10723925Sgibbs address 0x003 10823925Sgibbs access_mode RO 109102672Sgibbs field CDI 0x80 110102672Sgibbs field IOI 0x40 111102672Sgibbs field MSGI 0x20 112102672Sgibbs field ATNI 0x10 113102672Sgibbs field SELI 0x08 114102672Sgibbs field BSYI 0x04 115102672Sgibbs field REQI 0x02 116102672Sgibbs field ACKI 0x01 11723925Sgibbs/* 11823925Sgibbs * Possible phases in SCSISIGI 11923925Sgibbs */ 12023925Sgibbs mask PHASE_MASK CDI|IOI|MSGI 12123925Sgibbs mask P_DATAOUT 0x00 12223925Sgibbs mask P_DATAIN IOI 12365948Sgibbs mask P_DATAOUT_DT P_DATAOUT|MSGI 12465948Sgibbs mask P_DATAIN_DT P_DATAIN|MSGI 12523925Sgibbs mask P_COMMAND CDI 12623925Sgibbs mask P_MESGOUT CDI|MSGI 12723925Sgibbs mask P_STATUS CDI|IOI 12823925Sgibbs mask P_MESGIN CDI|IOI|MSGI 12923925Sgibbs} 13023925Sgibbs 13123925Sgibbs/* 13223925Sgibbs * SCSI Control Signal Write Register (p. 3-16). 13323925Sgibbs * Writing to this register modifies the control signals on the bus. Only 13423925Sgibbs * those signals that are allowed in the current mode (Initiator/Target) are 13523925Sgibbs * asserted. 13623925Sgibbs */ 13723925Sgibbsregister SCSISIGO { 13823925Sgibbs address 0x003 13923925Sgibbs access_mode WO 140102672Sgibbs field CDO 0x80 141102672Sgibbs field IOO 0x40 142102672Sgibbs field MSGO 0x20 143102672Sgibbs field ATNO 0x10 144102672Sgibbs field SELO 0x08 145102672Sgibbs field BSYO 0x04 146102672Sgibbs field REQO 0x02 147102672Sgibbs field ACKO 0x01 14823925Sgibbs/* 14923925Sgibbs * Possible phases to write into SCSISIG0 15023925Sgibbs */ 15123925Sgibbs mask PHASE_MASK CDI|IOI|MSGI 15223925Sgibbs mask P_DATAOUT 0x00 15323925Sgibbs mask P_DATAIN IOI 15423925Sgibbs mask P_COMMAND CDI 15523925Sgibbs mask P_MESGOUT CDI|MSGI 15623925Sgibbs mask P_STATUS CDI|IOI 15723925Sgibbs mask P_MESGIN CDI|IOI|MSGI 15823925Sgibbs} 15923925Sgibbs 16023925Sgibbs/* 16123925Sgibbs * SCSI Rate Control (p. 3-17). 16223925Sgibbs * Contents of this register determine the Synchronous SCSI data transfer 16323925Sgibbs * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 16423925Sgibbs * SOFS (3:0) bits disables synchronous data transfers. Any offset value 16523925Sgibbs * greater than 0 enables synchronous transfers. 16623925Sgibbs */ 16723925Sgibbsregister SCSIRATE { 16823925Sgibbs address 0x004 16923925Sgibbs access_mode RW 170102672Sgibbs field WIDEXFER 0x80 /* Wide transfer control */ 171102672Sgibbs field ENABLE_CRC 0x40 /* CRC for D-Phases */ 172102672Sgibbs field SINGLE_EDGE 0x10 /* Disable DT Transfers */ 17323925Sgibbs mask SXFR 0x70 /* Sync transfer rate */ 17455581Sgibbs mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 17523925Sgibbs mask SOFS 0x0f /* Sync offset */ 17623925Sgibbs} 17723925Sgibbs 17823925Sgibbs/* 17923925Sgibbs * SCSI ID (p. 3-18). 18023925Sgibbs * Contains the ID of the board and the current target on the 18123925Sgibbs * selected channel. 18223925Sgibbs */ 18323925Sgibbsregister SCSIID { 18423925Sgibbs address 0x005 18523925Sgibbs access_mode RW 18623925Sgibbs mask TID 0xf0 /* Target ID mask */ 18763457Sgibbs mask TWIN_TID 0x70 188102672Sgibbs field TWIN_CHNLB 0x80 18923925Sgibbs mask OID 0x0f /* Our ID mask */ 19039220Sgibbs /* 19139220Sgibbs * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 19239220Sgibbs * The aic7890/91 allow an offset of up to 127 transfers in both wide 19339220Sgibbs * and narrow mode. 19439220Sgibbs */ 19539220Sgibbs alias SCSIOFFSET 19639220Sgibbs mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 19723925Sgibbs} 19823925Sgibbs 19923925Sgibbs/* 20023925Sgibbs * SCSI Latched Data (p. 3-19). 20123925Sgibbs * Read/Write latches used to transfer data on the SCSI bus during 20223925Sgibbs * Automatic or Manual PIO mode. SCSIDATH can be used for the 20323925Sgibbs * upper byte of a 16bit wide asynchronouse data phase transfer. 20423925Sgibbs */ 20523925Sgibbsregister SCSIDATL { 20623925Sgibbs address 0x006 20723925Sgibbs access_mode RW 20823925Sgibbs} 20923925Sgibbs 21023925Sgibbsregister SCSIDATH { 21123925Sgibbs address 0x007 21223925Sgibbs access_mode RW 21323925Sgibbs} 21423925Sgibbs 21523925Sgibbs/* 21623925Sgibbs * SCSI Transfer Count (pp. 3-19,20) 21723925Sgibbs * These registers count down the number of bytes transferred 21823925Sgibbs * across the SCSI bus. The counter is decremented only once 21923925Sgibbs * the data has been safely transferred. SDONE in SSTAT0 is 22023925Sgibbs * set when STCNT goes to 0 22123925Sgibbs */ 22223925Sgibbsregister STCNT { 22323925Sgibbs address 0x008 22423925Sgibbs size 3 22523925Sgibbs access_mode RW 22623925Sgibbs} 22723925Sgibbs 228102672Sgibbs/* ALT_MODE registers (Ultra2 and Ultra160 chips) */ 229102672Sgibbsregister SXFRCTL2 { 230102672Sgibbs address 0x013 231102672Sgibbs access_mode RW 232102672Sgibbs field AUTORSTDIS 0x10 233102672Sgibbs field CMDDMAEN 0x08 234102672Sgibbs mask ASYNC_SETUP 0x07 235102672Sgibbs} 236102672Sgibbs 23755581Sgibbs/* ALT_MODE register on Ultra160 chips */ 23855581Sgibbsregister OPTIONMODE { 23955581Sgibbs address 0x008 24055581Sgibbs access_mode RW 241102672Sgibbs field AUTORATEEN 0x80 242102672Sgibbs field AUTOACKEN 0x40 243102672Sgibbs field ATNMGMNTEN 0x20 244102672Sgibbs field BUSFREEREV 0x10 245102672Sgibbs field EXPPHASEDIS 0x08 246102672Sgibbs field SCSIDATL_IMGEN 0x04 247102672Sgibbs field AUTO_MSGOUT_DE 0x02 248102672Sgibbs field DIS_MSGIN_DUALEDGE 0x01 24955581Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 25055581Sgibbs} 25155581Sgibbs 25255581Sgibbs/* ALT_MODE register on Ultra160 chips */ 25355581Sgibbsregister TARGCRCCNT { 25455581Sgibbs address 0x00a 25555581Sgibbs size 2 25655581Sgibbs access_mode RW 25755581Sgibbs} 25855581Sgibbs 25923925Sgibbs/* 26023925Sgibbs * Clear SCSI Interrupt 0 (p. 3-20) 26123925Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 26223925Sgibbs */ 26323925Sgibbsregister CLRSINT0 { 26423925Sgibbs address 0x00b 26523925Sgibbs access_mode WO 266102672Sgibbs field CLRSELDO 0x40 267102672Sgibbs field CLRSELDI 0x20 268102672Sgibbs field CLRSELINGO 0x10 269102672Sgibbs field CLRSWRAP 0x08 270102672Sgibbs field CLRIOERR 0x08 /* Ultra2 Only */ 271102672Sgibbs field CLRSPIORDY 0x02 27223925Sgibbs} 27323925Sgibbs 27423925Sgibbs/* 27523925Sgibbs * SCSI Status 0 (p. 3-21) 27623925Sgibbs * Contains one set of SCSI Interrupt codes 27723925Sgibbs * These are most likely of interest to the sequencer 27823925Sgibbs */ 27923925Sgibbsregister SSTAT0 { 28023925Sgibbs address 0x00b 28123925Sgibbs access_mode RO 282102672Sgibbs field TARGET 0x80 /* Board acting as target */ 283102672Sgibbs field SELDO 0x40 /* Selection Done */ 284102672Sgibbs field SELDI 0x20 /* Board has been selected */ 285102672Sgibbs field SELINGO 0x10 /* Selection In Progress */ 286102672Sgibbs field SWRAP 0x08 /* 24bit counter wrap */ 287102672Sgibbs field IOERR 0x08 /* LVD Tranceiver mode changed */ 288102672Sgibbs field SDONE 0x04 /* STCNT = 0x000000 */ 289102672Sgibbs field SPIORDY 0x02 /* SCSI PIO Ready */ 290102672Sgibbs field DMADONE 0x01 /* DMA transfer completed */ 29123925Sgibbs} 29223925Sgibbs 29323925Sgibbs/* 29423925Sgibbs * Clear SCSI Interrupt 1 (p. 3-23) 29523925Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 29623925Sgibbs */ 29723925Sgibbsregister CLRSINT1 { 29823925Sgibbs address 0x00c 29923925Sgibbs access_mode WO 300102672Sgibbs field CLRSELTIMEO 0x80 301102672Sgibbs field CLRATNO 0x40 302102672Sgibbs field CLRSCSIRSTI 0x20 303102672Sgibbs field CLRBUSFREE 0x08 304102672Sgibbs field CLRSCSIPERR 0x04 305102672Sgibbs field CLRPHASECHG 0x02 306102672Sgibbs field CLRREQINIT 0x01 30723925Sgibbs} 30823925Sgibbs 30923925Sgibbs/* 31023925Sgibbs * SCSI Status 1 (p. 3-24) 31123925Sgibbs */ 31223925Sgibbsregister SSTAT1 { 31323925Sgibbs address 0x00c 31423925Sgibbs access_mode RO 315102672Sgibbs field SELTO 0x80 316102672Sgibbs field ATNTARG 0x40 317102672Sgibbs field SCSIRSTI 0x20 318102672Sgibbs field PHASEMIS 0x10 319102672Sgibbs field BUSFREE 0x08 320102672Sgibbs field SCSIPERR 0x04 321102672Sgibbs field PHASECHG 0x02 322102672Sgibbs field REQINIT 0x01 32323925Sgibbs} 32423925Sgibbs 32523925Sgibbs/* 32623925Sgibbs * SCSI Status 2 (pp. 3-25,26) 32723925Sgibbs */ 32823925Sgibbsregister SSTAT2 { 32923925Sgibbs address 0x00d 33023925Sgibbs access_mode RO 331102672Sgibbs field OVERRUN 0x80 332102672Sgibbs field SHVALID 0x40 /* Shaddow Layer non-zero */ 333102672Sgibbs field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 334102672Sgibbs field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 335102672Sgibbs field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 336102672Sgibbs field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 337102672Sgibbs field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 33823925Sgibbs mask SFCNT 0x1f 33923925Sgibbs} 34023925Sgibbs 34123925Sgibbs/* 34223925Sgibbs * SCSI Status 3 (p. 3-26) 34323925Sgibbs */ 34423925Sgibbsregister SSTAT3 { 34523925Sgibbs address 0x00e 34623925Sgibbs access_mode RO 34723925Sgibbs mask SCSICNT 0xf0 34823925Sgibbs mask OFFCNT 0x0f 34995378Sgibbs mask U2OFFCNT 0x7f 35023925Sgibbs} 35123925Sgibbs 35223925Sgibbs/* 35339220Sgibbs * SCSI ID for the aic7890/91 chips 35423925Sgibbs */ 35539220Sgibbsregister SCSIID_ULTRA2 { 35623925Sgibbs address 0x00f 35723925Sgibbs access_mode RW 35839220Sgibbs mask TID 0xf0 /* Target ID mask */ 35939220Sgibbs mask OID 0x0f /* Our ID mask */ 36023925Sgibbs} 36123925Sgibbs 36223925Sgibbs/* 36323925Sgibbs * SCSI Interrupt Mode 1 (p. 3-28) 36423925Sgibbs * Setting any bit will enable the corresponding function 36523925Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 36623925Sgibbs */ 36723925Sgibbsregister SIMODE0 { 36823925Sgibbs address 0x010 36923925Sgibbs access_mode RW 370102672Sgibbs field ENSELDO 0x40 371102672Sgibbs field ENSELDI 0x20 372102672Sgibbs field ENSELINGO 0x10 373102672Sgibbs field ENSWRAP 0x08 374102672Sgibbs field ENIOERR 0x08 /* LVD Tranceiver mode changes */ 375102672Sgibbs field ENSDONE 0x04 376102672Sgibbs field ENSPIORDY 0x02 377102672Sgibbs field ENDMADONE 0x01 37823925Sgibbs} 37923925Sgibbs 38023925Sgibbs/* 38123925Sgibbs * SCSI Interrupt Mode 1 (pp. 3-28,29) 38223925Sgibbs * Setting any bit will enable the corresponding function 38323925Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 38423925Sgibbs */ 38523925Sgibbsregister SIMODE1 { 38623925Sgibbs address 0x011 38723925Sgibbs access_mode RW 388102672Sgibbs field ENSELTIMO 0x80 389102672Sgibbs field ENATNTARG 0x40 390102672Sgibbs field ENSCSIRST 0x20 391102672Sgibbs field ENPHASEMIS 0x10 392102672Sgibbs field ENBUSFREE 0x08 393102672Sgibbs field ENSCSIPERR 0x04 394102672Sgibbs field ENPHASECHG 0x02 395102672Sgibbs field ENREQINIT 0x01 39623925Sgibbs} 39723925Sgibbs 39823925Sgibbs/* 39923925Sgibbs * SCSI Data Bus (High) (p. 3-29) 40023925Sgibbs * This register reads data on the SCSI Data bus directly. 40123925Sgibbs */ 40223925Sgibbsregister SCSIBUSL { 40323925Sgibbs address 0x012 40468087Sgibbs access_mode RW 40523925Sgibbs} 40623925Sgibbs 40723925Sgibbsregister SCSIBUSH { 40823925Sgibbs address 0x013 40968087Sgibbs access_mode RW 41023925Sgibbs} 41123925Sgibbs 41223925Sgibbs/* 41323925Sgibbs * SCSI/Host Address (p. 3-30) 41423925Sgibbs * These registers hold the host address for the byte about to be 41523925Sgibbs * transferred on the SCSI bus. They are counted up in the same 41623925Sgibbs * manner as STCNT is counted down. SHADDR should always be used 41723925Sgibbs * to determine the address of the last byte transferred since HADDR 41823925Sgibbs * can be skewed by write ahead. 41923925Sgibbs */ 42023925Sgibbsregister SHADDR { 42123925Sgibbs address 0x014 42223925Sgibbs size 4 42323925Sgibbs access_mode RO 42423925Sgibbs} 42523925Sgibbs 42623925Sgibbs/* 42723925Sgibbs * Selection Timeout Timer (p. 3-30) 42823925Sgibbs */ 42923925Sgibbsregister SELTIMER { 43023925Sgibbs address 0x018 43123925Sgibbs access_mode RW 432102672Sgibbs field STAGE6 0x20 433102672Sgibbs field STAGE5 0x10 434102672Sgibbs field STAGE4 0x08 435102672Sgibbs field STAGE3 0x04 436102672Sgibbs field STAGE2 0x02 437102672Sgibbs field STAGE1 0x01 43839220Sgibbs alias TARGIDIN 43923925Sgibbs} 44023925Sgibbs 44123925Sgibbs/* 44223925Sgibbs * Selection/Reselection ID (p. 3-31) 44323925Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 44423925Sgibbs * device did not set its own ID. 44523925Sgibbs */ 44623925Sgibbsregister SELID { 44723925Sgibbs address 0x019 44823925Sgibbs access_mode RW 44923925Sgibbs mask SELID_MASK 0xf0 450102672Sgibbs field ONEBIT 0x08 45123925Sgibbs} 45223925Sgibbs 45355581Sgibbsregister SCAMCTL { 45455581Sgibbs address 0x01a 45555581Sgibbs access_mode RW 456102672Sgibbs field ENSCAMSELO 0x80 457102672Sgibbs field CLRSCAMSELID 0x40 458102672Sgibbs field ALTSTIM 0x20 459102672Sgibbs field DFLTTID 0x10 46055581Sgibbs mask SCAMLVL 0x03 46155581Sgibbs} 46255581Sgibbs 46323925Sgibbs/* 46439220Sgibbs * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 46539220Sgibbs */ 46639220Sgibbsregister TARGID { 46739220Sgibbs address 0x01b 46839220Sgibbs size 2 46939220Sgibbs access_mode RW 47039220Sgibbs} 47139220Sgibbs 47239220Sgibbs/* 47339220Sgibbs * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 47439220Sgibbs * Indicates if external logic has been attached to the chip to 47539220Sgibbs * perform the tasks of accessing a serial eeprom, testing termination 47639220Sgibbs * strength, and performing cable detection. On the aic7860, most of 47739220Sgibbs * these features are handled on chip, but on the aic7855 an attached 47839220Sgibbs * aic3800 does the grunt work. 47939220Sgibbs */ 48039220Sgibbsregister SPIOCAP { 48139220Sgibbs address 0x01b 48239220Sgibbs access_mode RW 483102672Sgibbs field SOFT1 0x80 484102672Sgibbs field SOFT0 0x40 485102672Sgibbs field SOFTCMDEN 0x20 486102672Sgibbs field EXT_BRDCTL 0x10 /* External Board control */ 487102672Sgibbs field SEEPROM 0x08 /* External serial eeprom logic */ 488102672Sgibbs field EEPROM 0x04 /* Writable external BIOS ROM */ 489102672Sgibbs field ROM 0x02 /* Logic for accessing external ROM */ 490102672Sgibbs field SSPIOCPS 0x01 /* Termination and cable detection */ 49139220Sgibbs} 49239220Sgibbs 49344590Sgibbsregister BRDCTL { 49444590Sgibbs address 0x01d 495102672Sgibbs field BRDDAT7 0x80 496102672Sgibbs field BRDDAT6 0x40 497102672Sgibbs field BRDDAT5 0x20 498102672Sgibbs field BRDSTB 0x10 499102672Sgibbs field BRDCS 0x08 500102672Sgibbs field BRDRW 0x04 501102672Sgibbs field BRDCTL1 0x02 502102672Sgibbs field BRDCTL0 0x01 50344590Sgibbs /* 7890 Definitions */ 504102672Sgibbs field BRDDAT4 0x10 505102672Sgibbs field BRDDAT3 0x08 506102672Sgibbs field BRDDAT2 0x04 507102672Sgibbs field BRDRW_ULTRA2 0x02 508102672Sgibbs field BRDSTB_ULTRA2 0x01 50944590Sgibbs} 51044590Sgibbs 51139220Sgibbs/* 51244590Sgibbs * Serial EEPROM Control (p. 4-92 in 7870 Databook) 51344590Sgibbs * Controls the reading and writing of an external serial 1-bit 51444590Sgibbs * EEPROM Device. In order to access the serial EEPROM, you must 51544590Sgibbs * first set the SEEMS bit that generates a request to the memory 51644590Sgibbs * port for access to the serial EEPROM device. When the memory 51744590Sgibbs * port is not busy servicing another request, it reconfigures 51844590Sgibbs * to allow access to the serial EEPROM. When this happens, SEERDY 51944590Sgibbs * gets set high to verify that the memory port access has been 52044590Sgibbs * granted. 52144590Sgibbs * 52244590Sgibbs * After successful arbitration for the memory port, the SEECS bit of 52344590Sgibbs * the SEECTL register is connected to the chip select. The SEECK, 52444590Sgibbs * SEEDO, and SEEDI are connected to the clock, data out, and data in 52544590Sgibbs * lines respectively. The SEERDY bit of SEECTL is useful in that it 52644590Sgibbs * gives us an 800 nsec timer. After a write to the SEECTL register, 52744590Sgibbs * the SEERDY goes high 800 nsec later. The one exception to this is 52844590Sgibbs * when we first request access to the memory port. The SEERDY goes 52944590Sgibbs * high to signify that access has been granted and, for this case, has 53044590Sgibbs * no implied timing. 53144590Sgibbs * 53244590Sgibbs * See 93cx6.c for detailed information on the protocol necessary to 53344590Sgibbs * read the serial EEPROM. 53444590Sgibbs */ 53544590Sgibbsregister SEECTL { 53644590Sgibbs address 0x01e 537102672Sgibbs field EXTARBACK 0x80 538102672Sgibbs field EXTARBREQ 0x40 539102672Sgibbs field SEEMS 0x20 540102672Sgibbs field SEERDY 0x10 541102672Sgibbs field SEECS 0x08 542102672Sgibbs field SEECK 0x04 543102672Sgibbs field SEEDO 0x02 544102672Sgibbs field SEEDI 0x01 54544590Sgibbs} 54644590Sgibbs/* 54723925Sgibbs * SCSI Block Control (p. 3-32) 54823925Sgibbs * Controls Bus type and channel selection. In a twin channel configuration 54923925Sgibbs * addresses 0x00-0x1e are gated to the appropriate channel based on this 55023925Sgibbs * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 55123925Sgibbs * on a wide bus. 55223925Sgibbs */ 55323925Sgibbsregister SBLKCTL { 55423925Sgibbs address 0x01f 55523925Sgibbs access_mode RW 556102672Sgibbs field DIAGLEDEN 0x80 /* Aic78X0 only */ 557102672Sgibbs field DIAGLEDON 0x40 /* Aic78X0 only */ 558102672Sgibbs field AUTOFLUSHDIS 0x20 559102672Sgibbs field SELBUSB 0x08 560102672Sgibbs field ENAB40 0x08 /* LVD transceiver active */ 561102672Sgibbs field ENAB20 0x04 /* SE/HVD transceiver active */ 562102672Sgibbs field SELWIDE 0x02 563102672Sgibbs field XCVR 0x01 /* External transceiver active */ 56423925Sgibbs} 56523925Sgibbs 56623925Sgibbs/* 56723925Sgibbs * Sequencer Control (p. 3-33) 56823925Sgibbs * Error detection mode and speed configuration 56923925Sgibbs */ 57023925Sgibbsregister SEQCTL { 57123925Sgibbs address 0x060 57223925Sgibbs access_mode RW 573102672Sgibbs field PERRORDIS 0x80 574102672Sgibbs field PAUSEDIS 0x40 575102672Sgibbs field FAILDIS 0x20 576102672Sgibbs field FASTMODE 0x10 577102672Sgibbs field BRKADRINTEN 0x08 578102672Sgibbs field STEP 0x04 579102672Sgibbs field SEQRESET 0x02 580102672Sgibbs field LOADRAM 0x01 58123925Sgibbs} 58223925Sgibbs 58323925Sgibbs/* 58423925Sgibbs * Sequencer RAM Data (p. 3-34) 58523925Sgibbs * Single byte window into the Scratch Ram area starting at the address 58623925Sgibbs * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 58742652Sgibbs * four bytes in succession. The SEQADDRs will increment after the most 58823925Sgibbs * significant byte is written 58923925Sgibbs */ 59023925Sgibbsregister SEQRAM { 59123925Sgibbs address 0x061 59223925Sgibbs access_mode RW 59323925Sgibbs} 59423925Sgibbs 59523925Sgibbs/* 59623925Sgibbs * Sequencer Address Registers (p. 3-35) 59723925Sgibbs * Only the first bit of SEQADDR1 holds addressing information 59823925Sgibbs */ 59923925Sgibbsregister SEQADDR0 { 60023925Sgibbs address 0x062 60123925Sgibbs access_mode RW 60223925Sgibbs} 60323925Sgibbs 60423925Sgibbsregister SEQADDR1 { 60523925Sgibbs address 0x063 60623925Sgibbs access_mode RW 60723925Sgibbs mask SEQADDR1_MASK 0x01 60823925Sgibbs} 60923925Sgibbs 61023925Sgibbs/* 61123925Sgibbs * Accumulator 61223925Sgibbs * We cheat by passing arguments in the Accumulator up to the kernel driver 61323925Sgibbs */ 61423925Sgibbsregister ACCUM { 61523925Sgibbs address 0x064 61623925Sgibbs access_mode RW 61723925Sgibbs accumulator 61823925Sgibbs} 61923925Sgibbs 62023925Sgibbsregister SINDEX { 62123925Sgibbs address 0x065 62223925Sgibbs access_mode RW 62323925Sgibbs sindex 62423925Sgibbs} 62523925Sgibbs 62623925Sgibbsregister DINDEX { 62723925Sgibbs address 0x066 62823925Sgibbs access_mode RW 62923925Sgibbs} 63023925Sgibbs 63123925Sgibbsregister ALLONES { 63223925Sgibbs address 0x069 63323925Sgibbs access_mode RO 63423925Sgibbs allones 63523925Sgibbs} 63623925Sgibbs 63723925Sgibbsregister ALLZEROS { 63823925Sgibbs address 0x06a 63923925Sgibbs access_mode RO 64023925Sgibbs allzeros 64123925Sgibbs} 64223925Sgibbs 64323925Sgibbsregister NONE { 64423925Sgibbs address 0x06a 64523925Sgibbs access_mode WO 64623925Sgibbs none 64723925Sgibbs} 64823925Sgibbs 64923925Sgibbsregister FLAGS { 65023925Sgibbs address 0x06b 65123925Sgibbs access_mode RO 652102672Sgibbs field ZERO 0x02 653102672Sgibbs field CARRY 0x01 65423925Sgibbs} 65523925Sgibbs 65623925Sgibbsregister SINDIR { 65723925Sgibbs address 0x06c 65823925Sgibbs access_mode RO 65923925Sgibbs} 66023925Sgibbs 66123925Sgibbsregister DINDIR { 66223925Sgibbs address 0x06d 66323925Sgibbs access_mode WO 66423925Sgibbs} 66523925Sgibbs 66623925Sgibbsregister FUNCTION1 { 66723925Sgibbs address 0x06e 66823925Sgibbs access_mode RW 66923925Sgibbs} 67023925Sgibbs 67123925Sgibbsregister STACK { 67223925Sgibbs address 0x06f 67323925Sgibbs access_mode RO 67423925Sgibbs} 67523925Sgibbs 676109590Sgibbsconst STACK_SIZE 4 677109590Sgibbs 67823925Sgibbs/* 67923925Sgibbs * Board Control (p. 3-43) 68023925Sgibbs */ 68123925Sgibbsregister BCTL { 68223925Sgibbs address 0x084 68323925Sgibbs access_mode RW 684102672Sgibbs field ACE 0x08 685102672Sgibbs field ENABLE 0x01 68623925Sgibbs} 68723925Sgibbs 68823925Sgibbs/* 68923925Sgibbs * On the aic78X0 chips, Board Control is replaced by the DSCommand 69023925Sgibbs * register (p. 4-64) 69123925Sgibbs */ 69244590Sgibbsregister DSCOMMAND0 { 69323925Sgibbs address 0x084 69423925Sgibbs access_mode RW 695102672Sgibbs field CACHETHEN 0x80 /* Cache Threshold enable */ 696102672Sgibbs field DPARCKEN 0x40 /* Data Parity Check Enable */ 697102672Sgibbs field MPARCKEN 0x20 /* Memory Parity Check Enable */ 698102672Sgibbs field EXTREQLCK 0x10 /* External Request Lock */ 69944590Sgibbs /* aic7890/91/96/97 only */ 700102672Sgibbs field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 701102672Sgibbs field RAMPS 0x04 /* External SCB RAM Present */ 702102672Sgibbs field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 703102672Sgibbs field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 70423925Sgibbs} 70523925Sgibbs 70679874Sgibbsregister DSCOMMAND1 { 70779874Sgibbs address 0x085 70879874Sgibbs access_mode RW 70979874Sgibbs mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 710102672Sgibbs field HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 711102672Sgibbs field HADDLDSEL0 0x01 71279874Sgibbs} 71379874Sgibbs 71423925Sgibbs/* 71579874Sgibbs * Bus On/Off Time (p. 3-44) aic7770 only 71623925Sgibbs */ 71723925Sgibbsregister BUSTIME { 71823925Sgibbs address 0x085 71923925Sgibbs access_mode RW 72023925Sgibbs mask BOFF 0xf0 72123925Sgibbs mask BON 0x0f 72223925Sgibbs} 72323925Sgibbs 72423925Sgibbs/* 72544590Sgibbs * Bus Speed (p. 3-45) aic7770 only 72623925Sgibbs */ 72723925Sgibbsregister BUSSPD { 72823925Sgibbs address 0x086 72923925Sgibbs access_mode RW 73023925Sgibbs mask DFTHRSH 0xc0 73123925Sgibbs mask STBOFF 0x38 73223925Sgibbs mask STBON 0x07 73323925Sgibbs mask DFTHRSH_100 0xc0 73468087Sgibbs mask DFTHRSH_75 0x80 73523925Sgibbs} 73623925Sgibbs 73744590Sgibbs/* aic7850/55/60/70/80/95 only */ 73844590Sgibbsregister DSPCISTATUS { 73944590Sgibbs address 0x086 74044590Sgibbs mask DFTHRSH_100 0xc0 74144590Sgibbs} 74244590Sgibbs 74347158Sgibbs/* aic7890/91/96/97 only */ 74447158Sgibbsregister HS_MAILBOX { 74547158Sgibbs address 0x086 74647158Sgibbs mask HOST_MAILBOX 0xF0 74747158Sgibbs mask SEQ_MAILBOX 0x0F 74858258Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 74947158Sgibbs} 75047158Sgibbs 75147158Sgibbsconst HOST_MAILBOX_SHIFT 4 75247158Sgibbsconst SEQ_MAILBOX_SHIFT 0 75347158Sgibbs 75423925Sgibbs/* 75523925Sgibbs * Host Control (p. 3-47) R/W 75623925Sgibbs * Overall host control of the device. 75723925Sgibbs */ 75823925Sgibbsregister HCNTRL { 75923925Sgibbs address 0x087 76023925Sgibbs access_mode RW 761102672Sgibbs field POWRDN 0x40 762102672Sgibbs field SWINT 0x10 763102672Sgibbs field IRQMS 0x08 764102672Sgibbs field PAUSE 0x04 765102672Sgibbs field INTEN 0x02 766102672Sgibbs field CHIPRST 0x01 767102672Sgibbs field CHIPRSTACK 0x01 76823925Sgibbs} 76923925Sgibbs 77023925Sgibbs/* 77123925Sgibbs * Host Address (p. 3-48) 77223925Sgibbs * This register contains the address of the byte about 77323925Sgibbs * to be transferred across the host bus. 77423925Sgibbs */ 77523925Sgibbsregister HADDR { 77623925Sgibbs address 0x088 77723925Sgibbs size 4 77823925Sgibbs access_mode RW 77923925Sgibbs} 78023925Sgibbs 78123925Sgibbsregister HCNT { 78223925Sgibbs address 0x08c 78323925Sgibbs size 3 78423925Sgibbs access_mode RW 78523925Sgibbs} 78623925Sgibbs 78723925Sgibbs/* 78823925Sgibbs * SCB Pointer (p. 3-49) 78963457Sgibbs * Gate one of the SCBs into the SCBARRAY window. 79023925Sgibbs */ 79123925Sgibbsregister SCBPTR { 79223925Sgibbs address 0x090 79323925Sgibbs access_mode RW 79423925Sgibbs} 79523925Sgibbs 79623925Sgibbs/* 79723925Sgibbs * Interrupt Status (p. 3-50) 79823925Sgibbs * Status for system interrupts 79923925Sgibbs */ 80023925Sgibbsregister INTSTAT { 80123925Sgibbs address 0x091 80223925Sgibbs access_mode RW 803102672Sgibbs field BRKADRINT 0x08 804102672Sgibbs field SCSIINT 0x04 805102672Sgibbs field CMDCMPLT 0x02 806102672Sgibbs field SEQINT 0x01 80723925Sgibbs mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 80823925Sgibbs mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 809107420Sscottl mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */ 81023925Sgibbs mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 81163457Sgibbs mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 81279874Sgibbs mask PDATA_REINIT 0x50|SEQINT /* 81379874Sgibbs * Returned to data phase 81479874Sgibbs * that requires data 81579874Sgibbs * transfer pointers to be 81679874Sgibbs * recalculated from the 81779874Sgibbs * transfer residual. 81879874Sgibbs */ 81968087Sgibbs mask HOST_MSG_LOOP 0x60|SEQINT /* 82041646Sgibbs * The bus is ready for the 82141646Sgibbs * host to perform another 82241646Sgibbs * message transaction. This 82341646Sgibbs * mechanism is used for things 82441646Sgibbs * like sync/wide negotiation 82541646Sgibbs * that require a kernel based 82641646Sgibbs * message state engine. 82723925Sgibbs */ 82868087Sgibbs mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 82968087Sgibbs mask PERR_DETECTED 0x80|SEQINT /* 83057099Sgibbs * Either the phase_lock 83157099Sgibbs * or inb_next routine has 83257099Sgibbs * noticed a parity error. 83357099Sgibbs */ 83468087Sgibbs mask DATA_OVERRUN 0x90|SEQINT /* 83523925Sgibbs * Target attempted to write 83623925Sgibbs * beyond the bounds of its 83723925Sgibbs * command. 83823925Sgibbs */ 83968402Sgibbs mask MKMSG_FAILED 0xa0|SEQINT /* 84068402Sgibbs * Target completed command 84168402Sgibbs * without honoring our ATN 84268402Sgibbs * request to issue a message. 84368087Sgibbs */ 84468579Sgibbs mask MISSED_BUSFREE 0xb0|SEQINT /* 84568579Sgibbs * The sequencer never saw 84668579Sgibbs * the bus go free after 84768579Sgibbs * either a command complete 84868579Sgibbs * or disconnect message. 84968087Sgibbs */ 85068087Sgibbs mask SCB_MISMATCH 0xc0|SEQINT /* 85168087Sgibbs * Downloaded SCB's tag does 85268087Sgibbs * not match the entry we 85368087Sgibbs * intended to download. 85468087Sgibbs */ 85571390Sgibbs mask NO_FREE_SCB 0xd0|SEQINT /* 85668087Sgibbs * get_free_or_disc_scb failed. 85768087Sgibbs */ 85871390Sgibbs mask OUT_OF_RANGE 0xe0|SEQINT 85923925Sgibbs 86023925Sgibbs mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 86123925Sgibbs mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 86223925Sgibbs} 86323925Sgibbs 86423925Sgibbs/* 86523925Sgibbs * Hard Error (p. 3-53) 86623925Sgibbs * Reporting of catastrophic errors. You usually cannot recover from 86723925Sgibbs * these without a full board reset. 86823925Sgibbs */ 86923925Sgibbsregister ERROR { 87023925Sgibbs address 0x092 87123925Sgibbs access_mode RO 872102672Sgibbs field CIOPARERR 0x80 /* Ultra2 only */ 873102672Sgibbs field PCIERRSTAT 0x40 /* PCI only */ 874102672Sgibbs field MPARERR 0x20 /* PCI only */ 875102672Sgibbs field DPARERR 0x10 /* PCI only */ 876102672Sgibbs field SQPARERR 0x08 877102672Sgibbs field ILLOPCODE 0x04 878102672Sgibbs field ILLSADDR 0x02 879102672Sgibbs field ILLHADDR 0x01 88023925Sgibbs} 88123925Sgibbs 88223925Sgibbs/* 88323925Sgibbs * Clear Interrupt Status (p. 3-52) 88423925Sgibbs */ 88523925Sgibbsregister CLRINT { 88623925Sgibbs address 0x092 88723925Sgibbs access_mode WO 888102672Sgibbs field CLRPARERR 0x10 /* PCI only */ 889102672Sgibbs field CLRBRKADRINT 0x08 890102672Sgibbs field CLRSCSIINT 0x04 891102672Sgibbs field CLRCMDINT 0x02 892102672Sgibbs field CLRSEQINT 0x01 89323925Sgibbs} 89423925Sgibbs 89523925Sgibbsregister DFCNTRL { 89623925Sgibbs address 0x093 89723925Sgibbs access_mode RW 898102672Sgibbs field PRELOADEN 0x80 /* aic7890 only */ 899102672Sgibbs field WIDEODD 0x40 900102672Sgibbs field SCSIEN 0x20 901102672Sgibbs field SDMAEN 0x10 902102672Sgibbs field SDMAENACK 0x10 903102672Sgibbs field HDMAEN 0x08 904102672Sgibbs field HDMAENACK 0x08 905102672Sgibbs field DIRECTION 0x04 906102672Sgibbs field FIFOFLUSH 0x02 907102672Sgibbs field FIFORESET 0x01 90823925Sgibbs} 90923925Sgibbs 91023925Sgibbsregister DFSTATUS { 91123925Sgibbs address 0x094 91223925Sgibbs access_mode RO 913102672Sgibbs field PRELOAD_AVAIL 0x80 914102672Sgibbs field DFCACHETH 0x40 915102672Sgibbs field FIFOQWDEMP 0x20 916102672Sgibbs field MREQPEND 0x10 917102672Sgibbs field HDONE 0x08 918102672Sgibbs field DFTHRESH 0x04 919102672Sgibbs field FIFOFULL 0x02 920102672Sgibbs field FIFOEMP 0x01 92123925Sgibbs} 92223925Sgibbs 92341299Sgibbsregister DFWADDR { 92441299Sgibbs address 0x95 92541299Sgibbs access_mode RW 92641299Sgibbs} 92741299Sgibbs 92841299Sgibbsregister DFRADDR { 92941299Sgibbs address 0x97 93041299Sgibbs access_mode RW 93141299Sgibbs} 93241299Sgibbs 93323925Sgibbsregister DFDAT { 93423925Sgibbs address 0x099 93523925Sgibbs access_mode RW 93623925Sgibbs} 93723925Sgibbs 93823925Sgibbs/* 93923925Sgibbs * SCB Auto Increment (p. 3-59) 94023925Sgibbs * Byte offset into the SCB Array and an optional bit to allow auto 94123925Sgibbs * incrementing of the address during download and upload operations 94223925Sgibbs */ 94323925Sgibbsregister SCBCNT { 94423925Sgibbs address 0x09a 94523925Sgibbs access_mode RW 946102672Sgibbs field SCBAUTO 0x80 94723925Sgibbs mask SCBCNT_MASK 0x1f 94823925Sgibbs} 94923925Sgibbs 95023925Sgibbs/* 95123925Sgibbs * Queue In FIFO (p. 3-60) 95223925Sgibbs * Input queue for queued SCBs (commands that the seqencer has yet to start) 95323925Sgibbs */ 95423925Sgibbsregister QINFIFO { 95523925Sgibbs address 0x09b 95623925Sgibbs access_mode RW 95723925Sgibbs} 95823925Sgibbs 95923925Sgibbs/* 96023925Sgibbs * Queue In Count (p. 3-60) 96123925Sgibbs * Number of queued SCBs 96223925Sgibbs */ 96323925Sgibbsregister QINCNT { 96423925Sgibbs address 0x09c 96523925Sgibbs access_mode RO 96623925Sgibbs} 96723925Sgibbs 96823925Sgibbs/* 96923925Sgibbs * Queue Out FIFO (p. 3-61) 97023925Sgibbs * Queue of SCBs that have completed and await the host 97123925Sgibbs */ 97223925Sgibbsregister QOUTFIFO { 97323925Sgibbs address 0x09d 97423925Sgibbs access_mode WO 97523925Sgibbs} 97623925Sgibbs 97755581Sgibbsregister CRCCONTROL1 { 97855581Sgibbs address 0x09d 97955581Sgibbs access_mode RW 980102672Sgibbs field CRCONSEEN 0x80 981102672Sgibbs field CRCVALCHKEN 0x40 982102672Sgibbs field CRCENDCHKEN 0x20 983102672Sgibbs field CRCREQCHKEN 0x10 984102672Sgibbs field TARGCRCENDEN 0x08 985102672Sgibbs field TARGCRCCNTEN 0x04 98655581Sgibbs} 98755581Sgibbs 98855581Sgibbs 98923925Sgibbs/* 99023925Sgibbs * Queue Out Count (p. 3-61) 99123925Sgibbs * Number of queued SCBs in the Out FIFO 99223925Sgibbs */ 99323925Sgibbsregister QOUTCNT { 99423925Sgibbs address 0x09e 99523925Sgibbs access_mode RO 99623925Sgibbs} 99723925Sgibbs 99855581Sgibbsregister SCSIPHASE { 99955581Sgibbs address 0x09e 100055581Sgibbs access_mode RO 1001102672Sgibbs field STATUS_PHASE 0x20 1002102672Sgibbs field COMMAND_PHASE 0x10 1003102672Sgibbs field MSG_IN_PHASE 0x08 1004102672Sgibbs field MSG_OUT_PHASE 0x04 1005102672Sgibbs field DATA_IN_PHASE 0x02 1006102672Sgibbs field DATA_OUT_PHASE 0x01 100776634Sgibbs mask DATA_PHASE_MASK 0x03 100855581Sgibbs} 100955581Sgibbs 101023925Sgibbs/* 101139220Sgibbs * Special Function 101239220Sgibbs */ 101339220Sgibbsregister SFUNCT { 101439220Sgibbs address 0x09f 101539220Sgibbs access_mode RW 1016102672Sgibbs field ALT_MODE 0x80 101739220Sgibbs} 101839220Sgibbs 101939220Sgibbs/* 102023925Sgibbs * SCB Definition (p. 5-4) 102123925Sgibbs */ 102223925Sgibbsscb { 102395378Sgibbs address 0x0a0 102495378Sgibbs size 64 102595378Sgibbs 102663457Sgibbs SCB_CDB_PTR { 102723925Sgibbs size 4 102863457Sgibbs alias SCB_RESIDUAL_DATACNT 102963457Sgibbs alias SCB_CDB_STORE 103023925Sgibbs } 103163457Sgibbs SCB_RESIDUAL_SGPTR { 103263457Sgibbs size 4 103363457Sgibbs } 103463457Sgibbs SCB_SCSI_STATUS { 103523925Sgibbs size 1 103623925Sgibbs } 103795378Sgibbs SCB_TARGET_PHASES { 103895378Sgibbs size 1 103923925Sgibbs } 104095378Sgibbs SCB_TARGET_DATA_DIR { 104195378Sgibbs size 1 104295378Sgibbs } 104395378Sgibbs SCB_TARGET_ITAG { 104495378Sgibbs size 1 104595378Sgibbs } 104623925Sgibbs SCB_DATAPTR { 104723925Sgibbs size 4 104823925Sgibbs } 104923925Sgibbs SCB_DATACNT { 105039220Sgibbs /* 105163457Sgibbs * The last byte is really the high address bits for 105263457Sgibbs * the data address. 105339220Sgibbs */ 105439220Sgibbs size 4 1055102672Sgibbs field SG_LAST_SEG 0x80 /* In the fourth byte */ 105663457Sgibbs mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 105723925Sgibbs } 105863457Sgibbs SCB_SGPTR { 105923925Sgibbs size 4 1060102672Sgibbs field SG_RESID_VALID 0x04 /* In the first byte */ 1061102672Sgibbs field SG_FULL_RESID 0x02 /* In the first byte */ 1062102672Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 106323925Sgibbs } 106465948Sgibbs SCB_CONTROL { 106565948Sgibbs size 1 1066102672Sgibbs field TARGET_SCB 0x80 1067107420Sscottl field STATUS_RCVD 0x80 1068102672Sgibbs field DISCENB 0x40 1069102672Sgibbs field TAG_ENB 0x20 1070102672Sgibbs field MK_MESSAGE 0x10 1071102672Sgibbs field ULTRAENB 0x08 1072102672Sgibbs field DISCONNECTED 0x04 107365948Sgibbs mask SCB_TAG_TYPE 0x03 107465948Sgibbs } 107565948Sgibbs SCB_SCSIID { 107665948Sgibbs size 1 1077102672Sgibbs field TWIN_CHNLB 0x80 107865948Sgibbs mask TWIN_TID 0x70 107965948Sgibbs mask TID 0xf0 108065948Sgibbs mask OID 0x0f 108165948Sgibbs } 108265948Sgibbs SCB_LUN { 1083115333Sgibbs field SCB_XFERLEN_ODD 0x80 1084115333Sgibbs mask LID 0x3f 108565948Sgibbs size 1 108665948Sgibbs } 108723925Sgibbs SCB_TAG { 108823925Sgibbs size 1 108923925Sgibbs } 109065948Sgibbs SCB_CDB_LEN { 109165948Sgibbs size 1 109265948Sgibbs } 109339220Sgibbs SCB_SCSIRATE { 109423925Sgibbs size 1 109523925Sgibbs } 109639220Sgibbs SCB_SCSIOFFSET { 109739220Sgibbs size 1 109839220Sgibbs } 109963457Sgibbs SCB_NEXT { 110063457Sgibbs size 1 110139220Sgibbs } 110265948Sgibbs SCB_64_SPARE { 110339220Sgibbs size 16 110439220Sgibbs } 110565948Sgibbs SCB_64_BTT { 110663457Sgibbs size 16 110723925Sgibbs } 110823925Sgibbs} 110923925Sgibbs 111065948Sgibbsconst SCB_UPLOAD_SIZE 32 111165948Sgibbsconst SCB_DOWNLOAD_SIZE 32 111265948Sgibbsconst SCB_DOWNLOAD_SIZE_64 48 111339220Sgibbs 111423925Sgibbsconst SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 111523925Sgibbs 111623925Sgibbs/* --------------------- AHA-2840-only definitions -------------------- */ 111723925Sgibbs 111823925Sgibbsregister SEECTL_2840 { 111923925Sgibbs address 0x0c0 112023925Sgibbs access_mode RW 1121102672Sgibbs field CS_2840 0x04 1122102672Sgibbs field CK_2840 0x02 1123102672Sgibbs field DO_2840 0x01 112423925Sgibbs} 112523925Sgibbs 112623925Sgibbsregister STATUS_2840 { 112723925Sgibbs address 0x0c1 112823925Sgibbs access_mode RW 1129102672Sgibbs field EEPROM_TF 0x80 113023925Sgibbs mask BIOS_SEL 0x60 113123925Sgibbs mask ADSEL 0x1e 1132102672Sgibbs field DI_2840 0x01 113323925Sgibbs} 113423925Sgibbs 113523925Sgibbs/* --------------------- AIC-7870-only definitions -------------------- */ 113623925Sgibbs 113739220Sgibbsregister CCHADDR { 113839220Sgibbs address 0x0E0 113939220Sgibbs size 8 114039220Sgibbs} 114139220Sgibbs 114239220Sgibbsregister CCHCNT { 114339220Sgibbs address 0x0E8 114439220Sgibbs} 114539220Sgibbs 114639220Sgibbsregister CCSGRAM { 114739220Sgibbs address 0x0E9 114839220Sgibbs} 114939220Sgibbs 115039220Sgibbsregister CCSGADDR { 115139220Sgibbs address 0x0EA 115239220Sgibbs} 115339220Sgibbs 115439220Sgibbsregister CCSGCTL { 115539220Sgibbs address 0x0EB 1156102672Sgibbs field CCSGDONE 0x80 1157102672Sgibbs field CCSGEN 0x08 1158102672Sgibbs field SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1159102672Sgibbs field CCSGRESET 0x01 116039220Sgibbs} 116139220Sgibbs 116239220Sgibbsregister CCSCBCNT { 116339220Sgibbs address 0xEF 116439220Sgibbs} 116539220Sgibbs 116639220Sgibbsregister CCSCBCTL { 116739220Sgibbs address 0x0EE 1168102672Sgibbs field CCSCBDONE 0x80 1169102672Sgibbs field ARRDONE 0x40 /* SCB Array prefetch done */ 1170102672Sgibbs field CCARREN 0x10 1171102672Sgibbs field CCSCBEN 0x08 1172102672Sgibbs field CCSCBDIR 0x04 1173102672Sgibbs field CCSCBRESET 0x01 117439220Sgibbs} 117539220Sgibbs 117639220Sgibbsregister CCSCBADDR { 117739220Sgibbs address 0x0ED 117839220Sgibbs} 117939220Sgibbs 118039220Sgibbsregister CCSCBRAM { 118139220Sgibbs address 0xEC 118239220Sgibbs} 118339220Sgibbs 118439220Sgibbs/* 118539220Sgibbs * SCB bank address (7895/7896/97 only) 118639220Sgibbs */ 118739220Sgibbsregister SCBBADDR { 118839220Sgibbs address 0x0F0 118939220Sgibbs access_mode RW 119039220Sgibbs} 119139220Sgibbs 119239220Sgibbsregister CCSCBPTR { 119339220Sgibbs address 0x0F1 119439220Sgibbs} 119539220Sgibbs 119639220Sgibbsregister HNSCB_QOFF { 119739220Sgibbs address 0x0F4 119839220Sgibbs} 119939220Sgibbs 120039220Sgibbsregister SNSCB_QOFF { 120139220Sgibbs address 0x0F6 120239220Sgibbs} 120339220Sgibbs 120439220Sgibbsregister SDSCB_QOFF { 120539220Sgibbs address 0x0F8 120639220Sgibbs} 120739220Sgibbs 120839220Sgibbsregister QOFF_CTLSTA { 120939220Sgibbs address 0x0FA 1210102672Sgibbs field SCB_AVAIL 0x40 1211102672Sgibbs field SNSCB_ROLLOVER 0x20 1212102672Sgibbs field SDSCB_ROLLOVER 0x10 121339220Sgibbs mask SCB_QSIZE 0x07 121439220Sgibbs mask SCB_QSIZE_256 0x06 121539220Sgibbs} 121639220Sgibbs 121739220Sgibbsregister DFF_THRSH { 121839220Sgibbs address 0x0FB 121939220Sgibbs mask WR_DFTHRSH 0x70 122039220Sgibbs mask RD_DFTHRSH 0x07 122139220Sgibbs mask RD_DFTHRSH_MIN 0x00 122239220Sgibbs mask RD_DFTHRSH_25 0x01 122339220Sgibbs mask RD_DFTHRSH_50 0x02 122439220Sgibbs mask RD_DFTHRSH_63 0x03 122539220Sgibbs mask RD_DFTHRSH_75 0x04 122639220Sgibbs mask RD_DFTHRSH_85 0x05 122739220Sgibbs mask RD_DFTHRSH_90 0x06 122839220Sgibbs mask RD_DFTHRSH_MAX 0x07 122939220Sgibbs mask WR_DFTHRSH_MIN 0x00 123039220Sgibbs mask WR_DFTHRSH_25 0x10 123139220Sgibbs mask WR_DFTHRSH_50 0x20 123239220Sgibbs mask WR_DFTHRSH_63 0x30 123339220Sgibbs mask WR_DFTHRSH_75 0x40 123439220Sgibbs mask WR_DFTHRSH_85 0x50 123539220Sgibbs mask WR_DFTHRSH_90 0x60 123639220Sgibbs mask WR_DFTHRSH_MAX 0x70 123739220Sgibbs} 123839220Sgibbs 123963457Sgibbsregister SG_CACHE_PRE { 124063457Sgibbs access_mode WO 124139220Sgibbs address 0x0fc 124263457Sgibbs mask SG_ADDR_MASK 0xf8 1243102672Sgibbs field LAST_SEG 0x02 1244102672Sgibbs field LAST_SEG_DONE 0x01 124539220Sgibbs} 124639220Sgibbs 124763457Sgibbsregister SG_CACHE_SHADOW { 124863457Sgibbs access_mode RO 124963457Sgibbs address 0x0fc 125063457Sgibbs mask SG_ADDR_MASK 0xf8 1251102672Sgibbs field LAST_SEG 0x02 1252102672Sgibbs field LAST_SEG_DONE 0x01 125363457Sgibbs} 125423925Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 125523925Sgibbs/* These offsets are either to values that are initialized by the board's 125623925Sgibbs * BIOS or are specified by the sequencer code. 125723925Sgibbs * 125823925Sgibbs * The host adapter card (at least the BIOS) uses 20-2f for SCSI 125923925Sgibbs * device information, 32-33 and 5a-5f as well. As it turns out, the 126023925Sgibbs * BIOS trashes 20-2f, writing the synchronous negotiation results 126123925Sgibbs * on top of the BIOS values, so we re-use those for our per-target 126223925Sgibbs * scratchspace (actually a value that can be copied directly into 126323925Sgibbs * SCSIRATE). The kernel driver will enable synchronous negotiation 126423925Sgibbs * for all targets that have a value other than 0 in the lower four 126523925Sgibbs * bits of the target scratch space. This should work regardless of 126623925Sgibbs * whether the bios has been installed. 126723925Sgibbs */ 126823925Sgibbs 126923925Sgibbsscratch_ram { 127095378Sgibbs address 0x020 127195378Sgibbs size 58 127223925Sgibbs 127323925Sgibbs /* 127423925Sgibbs * 1 byte per target starting at this address for configuration values 127523925Sgibbs */ 127671390Sgibbs BUSY_TARGETS { 127763457Sgibbs alias TARG_SCSIRATE 127871390Sgibbs size 16 127963457Sgibbs } 128039220Sgibbs /* 128168087Sgibbs * Bit vector of targets that have ULTRA enabled as set by 128268087Sgibbs * the BIOS. The Sequencer relies on a per-SCB field to 128368087Sgibbs * control whether to enable Ultra transfers or not. During 128468087Sgibbs * initialization, we read this field and reuse it for 2 128568087Sgibbs * entries in the busy target table. 128668087Sgibbs */ 128768087Sgibbs ULTRA_ENB { 128871390Sgibbs alias CMDSIZE_TABLE 128968087Sgibbs size 2 129068087Sgibbs } 129168087Sgibbs /* 129268087Sgibbs * Bit vector of targets that have disconnection disabled as set by 129368087Sgibbs * the BIOS. The Sequencer relies in a per-SCB field to control the 129468087Sgibbs * disconnect priveldge. During initialization, we read this field 129568087Sgibbs * and reuse it for 2 entries in the busy target table. 129668087Sgibbs */ 129768087Sgibbs DISC_DSB { 129868087Sgibbs size 2 129968087Sgibbs } 130071390Sgibbs CMDSIZE_TABLE_TAIL { 130168087Sgibbs size 4 130268087Sgibbs } 130368087Sgibbs /* 130466647Sgibbs * Partial transfer past cacheline end to be 130566647Sgibbs * transferred using an extra S/G. 130639220Sgibbs */ 130766647Sgibbs MWI_RESIDUAL { 130866647Sgibbs size 1 130923925Sgibbs } 131023925Sgibbs /* 131166647Sgibbs * SCBID of the next SCB to be started by the controller. 131266647Sgibbs */ 131366647Sgibbs NEXT_QUEUED_SCB { 131466647Sgibbs size 1 131566647Sgibbs } 131666647Sgibbs /* 131739220Sgibbs * Single byte buffer used to designate the type or message 131839220Sgibbs * to send to a target. 131923925Sgibbs */ 132039220Sgibbs MSG_OUT { 132123925Sgibbs size 1 132223925Sgibbs } 132323925Sgibbs /* Parameters for DMA Logic */ 132423925Sgibbs DMAPARAMS { 132523925Sgibbs size 1 1326102672Sgibbs field PRELOADEN 0x80 1327102672Sgibbs field WIDEODD 0x40 1328102672Sgibbs field SCSIEN 0x20 1329102672Sgibbs field SDMAEN 0x10 1330102672Sgibbs field SDMAENACK 0x10 1331102672Sgibbs field HDMAEN 0x08 1332102672Sgibbs field HDMAENACK 0x08 1333102672Sgibbs field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 1334102672Sgibbs field FIFOFLUSH 0x02 1335102672Sgibbs field FIFORESET 0x01 133623925Sgibbs } 133723925Sgibbs SEQ_FLAGS { 133823925Sgibbs size 1 1339107420Sscottl field NOT_IDENTIFIED 0x80 1340107420Sscottl field NO_CDB_SENT 0x40 1341102672Sgibbs field TARGET_CMD_IS_TAGGED 0x40 1342102672Sgibbs field DPHASE 0x20 134339220Sgibbs /* Target flags */ 1344102672Sgibbs field TARG_CMD_PENDING 0x10 1345102672Sgibbs field CMDPHASE_PENDING 0x08 1346102672Sgibbs field DPHASE_PENDING 0x04 1347102672Sgibbs field SPHASE_PENDING 0x02 1348102672Sgibbs field NO_DISCONNECT 0x01 134923925Sgibbs } 135023925Sgibbs /* 135123925Sgibbs * Temporary storage for the 135223925Sgibbs * target/channel/lun of a 135323925Sgibbs * reconnecting target 135423925Sgibbs */ 135563457Sgibbs SAVED_SCSIID { 135623925Sgibbs size 1 135723925Sgibbs } 135863457Sgibbs SAVED_LUN { 135923925Sgibbs size 1 136023925Sgibbs } 136123925Sgibbs /* 136223925Sgibbs * The last bus phase as seen by the sequencer. 136323925Sgibbs */ 136423925Sgibbs LASTPHASE { 136523925Sgibbs size 1 1366102672Sgibbs field CDI 0x80 1367102672Sgibbs field IOI 0x40 1368102672Sgibbs field MSGI 0x20 136923925Sgibbs mask PHASE_MASK CDI|IOI|MSGI 137023925Sgibbs mask P_DATAOUT 0x00 137123925Sgibbs mask P_DATAIN IOI 137223925Sgibbs mask P_COMMAND CDI 137323925Sgibbs mask P_MESGOUT CDI|MSGI 137423925Sgibbs mask P_STATUS CDI|IOI 137523925Sgibbs mask P_MESGIN CDI|IOI|MSGI 137623925Sgibbs mask P_BUSFREE 0x01 137723925Sgibbs } 137823925Sgibbs /* 137939220Sgibbs * head of list of SCBs awaiting 138039220Sgibbs * selection 138123925Sgibbs */ 138239220Sgibbs WAITING_SCBH { 138339220Sgibbs size 1 138423925Sgibbs } 138523925Sgibbs /* 138623925Sgibbs * head of list of SCBs that are 138723925Sgibbs * disconnected. Used for SCB 138823925Sgibbs * paging. 138923925Sgibbs */ 139023925Sgibbs DISCONNECTED_SCBH { 139123925Sgibbs size 1 139223925Sgibbs } 139323925Sgibbs /* 139423925Sgibbs * head of list of SCBs that are 139523925Sgibbs * not in use. Used for SCB paging. 139623925Sgibbs */ 139723925Sgibbs FREE_SCBH { 139823925Sgibbs size 1 139923925Sgibbs } 140039220Sgibbs /* 140172325Sgibbs * head of list of SCBs that have 140272325Sgibbs * completed but have not been 140372325Sgibbs * put into the qoutfifo. 140472325Sgibbs */ 140572325Sgibbs COMPLETE_SCBH { 140672325Sgibbs size 1 140772325Sgibbs } 140872325Sgibbs /* 140939220Sgibbs * Address of the hardware scb array in the host. 141039220Sgibbs */ 141123925Sgibbs HSCB_ADDR { 141223925Sgibbs size 4 141323925Sgibbs } 141439220Sgibbs /* 141563457Sgibbs * Base address of our shared data with the kernel driver in host 141666647Sgibbs * memory. This includes the qoutfifo and target mode 141763457Sgibbs * incoming command queue. 141839220Sgibbs */ 141963457Sgibbs SHARED_DATA_ADDR { 142039220Sgibbs size 4 142139220Sgibbs } 142239220Sgibbs KERNEL_QINPOS { 142323925Sgibbs size 1 142423925Sgibbs } 142539220Sgibbs QINPOS { 142639220Sgibbs size 1 142739220Sgibbs } 142839220Sgibbs QOUTPOS { 142939220Sgibbs size 1 143039220Sgibbs } 143128169Sgibbs /* 143241299Sgibbs * Kernel and sequencer offsets into the queue of 143341299Sgibbs * incoming target mode command descriptors. The 143444507Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 143528169Sgibbs */ 143641299Sgibbs KERNEL_TQINPOS { 143728169Sgibbs size 1 143828169Sgibbs } 143941299Sgibbs TQINPOS { 144041299Sgibbs size 1 144141299Sgibbs } 144223925Sgibbs ARG_1 { 144323925Sgibbs size 1 144441646Sgibbs mask SEND_MSG 0x80 144541646Sgibbs mask SEND_SENSE 0x40 144641646Sgibbs mask SEND_REJ 0x20 144741646Sgibbs mask MSGOUT_PHASEMIS 0x10 144841646Sgibbs mask EXIT_MSG_LOOP 0x08 144941646Sgibbs mask CONT_MSG_LOOP 0x04 145041646Sgibbs mask CONT_TARG_SESSION 0x02 1451210055Sgibbs mask SPARE 0x01 145223925Sgibbs alias RETURN_1 145323925Sgibbs } 145439220Sgibbs ARG_2 { 145539220Sgibbs size 1 145639220Sgibbs alias RETURN_2 145739220Sgibbs } 145839220Sgibbs 145923925Sgibbs /* 146039220Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 146139220Sgibbs */ 146239220Sgibbs LAST_MSG { 146339220Sgibbs size 1 1464123579Sgibbs alias TARG_IMMEDIATE_SCB 146539220Sgibbs } 146639220Sgibbs 146739220Sgibbs /* 146841816Sgibbs * Sequences the kernel driver has okayed for us. This allows 146941816Sgibbs * the driver to do things like prevent initiator or target 147041816Sgibbs * operations. 147141816Sgibbs */ 147241816Sgibbs SCSISEQ_TEMPLATE { 147341816Sgibbs size 1 1474102672Sgibbs field ENSELO 0x40 1475102672Sgibbs field ENSELI 0x20 1476102672Sgibbs field ENRSELI 0x10 1477102672Sgibbs field ENAUTOATNO 0x08 1478102672Sgibbs field ENAUTOATNI 0x04 1479102672Sgibbs field ENAUTOATNP 0x02 148041816Sgibbs } 1481102672Sgibbs} 148242652Sgibbs 1483102672Sgibbsscratch_ram { 1484102672Sgibbs address 0x056 1485102672Sgibbs size 4 148642652Sgibbs /* 1487102672Sgibbs * These scratch ram locations are initialized by the 274X BIOS. 1488102672Sgibbs * We reuse them after capturing the BIOS settings during 1489102672Sgibbs * initialization. 1490102672Sgibbs */ 1491102672Sgibbs 1492102672Sgibbs /* 149342652Sgibbs * The initiator specified tag for this target mode transaction. 149442652Sgibbs */ 1495102672Sgibbs HA_274_BIOSGLOBAL { 1496102672Sgibbs size 1 1497102672Sgibbs field HA_274_EXTENDED_TRANS 0x01 1498102672Sgibbs alias INITIATOR_TAG 149942652Sgibbs } 150042652Sgibbs 150174094Sgibbs SEQ_FLAGS2 { 1502102672Sgibbs size 1 1503102672Sgibbs field SCB_DMA 0x01 1504102672Sgibbs field TARGET_MSG_PENDING 0x02 150574094Sgibbs } 150695378Sgibbs} 150795378Sgibbs 150895378Sgibbsscratch_ram { 150995378Sgibbs address 0x05a 151095378Sgibbs size 6 151142652Sgibbs /* 1512102672Sgibbs * These are reserved registers in the card's scratch ram on the 2742. 1513102672Sgibbs * The EISA configuraiton chip is mapped here. On Rev E. of the 1514102672Sgibbs * aic7770, the sequencer can use this area for scratch, but the 1515102672Sgibbs * host cannot directly access these registers. On later chips, this 1516102672Sgibbs * area can be read and written by both the host and the sequencer. 1517102672Sgibbs * Even on later chips, many of these locations are initialized by 1518102672Sgibbs * the BIOS. 151923925Sgibbs */ 152023925Sgibbs SCSICONF { 152123925Sgibbs size 1 1522102672Sgibbs field TERM_ENB 0x80 1523102672Sgibbs field RESET_SCSI 0x40 1524102672Sgibbs field ENSPCHK 0x20 152539220Sgibbs mask HSCSIID 0x07 /* our SCSI ID */ 152639220Sgibbs mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 152723925Sgibbs } 152865953Sgibbs INTDEF { 152965953Sgibbs address 0x05c 153065953Sgibbs size 1 1531102672Sgibbs field EDGE_TRIG 0x80 153265953Sgibbs mask VECTOR 0x0f 153365953Sgibbs } 153423925Sgibbs HOSTCONF { 153523925Sgibbs address 0x05d 153623925Sgibbs size 1 153723925Sgibbs } 153823925Sgibbs HA_274_BIOSCTRL { 153923925Sgibbs address 0x05f 154023925Sgibbs size 1 154123925Sgibbs mask BIOSMODE 0x30 154223925Sgibbs mask BIOSDISABLED 0x30 1543102672Sgibbs field CHANNEL_B_PRIMARY 0x08 154423925Sgibbs } 154595378Sgibbs} 154695378Sgibbs 154795378Sgibbsscratch_ram { 154895378Sgibbs address 0x070 154995378Sgibbs size 16 155095378Sgibbs 155139220Sgibbs /* 155239220Sgibbs * Per target SCSI offset values for Ultra2 controllers. 155339220Sgibbs */ 155439220Sgibbs TARG_OFFSET { 155539220Sgibbs size 16 155639220Sgibbs } 155723925Sgibbs} 155823925Sgibbs 155963457Sgibbsconst TID_SHIFT 4 156023925Sgibbsconst SCB_LIST_NULL 0xff 156139220Sgibbsconst TARGET_CMD_CMPLT 0xfe 156223925Sgibbs 156339220Sgibbsconst CCSGADDR_MAX 0x80 156439220Sgibbsconst CCSGRAM_MAXSEGS 16 156523925Sgibbs 156623925Sgibbs/* WDTR Message values */ 156739220Sgibbsconst BUS_8_BIT 0x00 156823925Sgibbsconst BUS_16_BIT 0x01 156923925Sgibbsconst BUS_32_BIT 0x02 157039220Sgibbs 157139220Sgibbs/* Offset maximums */ 157223925Sgibbsconst MAX_OFFSET_8BIT 0x0f 157339220Sgibbsconst MAX_OFFSET_16BIT 0x08 157439220Sgibbsconst MAX_OFFSET_ULTRA2 0x7f 1575114621Sgibbsconst MAX_OFFSET 0x7f 157639220Sgibbsconst HOST_MSG 0xff 157729897Sgibbs 157839220Sgibbs/* Target mode command processing constants */ 157939220Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 158039220Sgibbs 158144507Sgibbsconst STATUS_BUSY 0x08 158263457Sgibbsconst STATUS_QUEUE_FULL 0x28 158363457Sgibbsconst TARGET_DATA_IN 1 158444507Sgibbs 158529897Sgibbs/* 158629897Sgibbs * Downloaded (kernel inserted) constants 158729897Sgibbs */ 158863457Sgibbs/* Offsets into the SCBID array where different data is stored */ 158963457Sgibbsconst QOUTFIFO_OFFSET download 159063457Sgibbsconst QINFIFO_OFFSET download 159165948Sgibbsconst CACHESIZE_MASK download 159265948Sgibbsconst INVERTED_CACHESIZE_MASK download 159366647Sgibbsconst SG_PREFETCH_CNT download 159466647Sgibbsconst SG_PREFETCH_ALIGN_MASK download 159566647Sgibbsconst SG_PREFETCH_ADDR_MASK download 1596