1139749Simp/*- 265942Sgibbs * Core definitions and data structures shareable across OS platforms. 339220Sgibbs * 471717Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 595378Sgibbs * Copyright (c) 2000-2001 Adaptec Inc. 639220Sgibbs * All rights reserved. 739220Sgibbs * 839220Sgibbs * Redistribution and use in source and binary forms, with or without 939220Sgibbs * modification, are permitted provided that the following conditions 1039220Sgibbs * are met: 1139220Sgibbs * 1. Redistributions of source code must retain the above copyright 1239220Sgibbs * notice, this list of conditions, and the following disclaimer, 1354211Sgibbs * without modification. 1495378Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1595378Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1695378Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1795378Sgibbs * including a substantially similar Disclaimer requirement for further 1895378Sgibbs * binary redistribution. 1995378Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2095378Sgibbs * of any contributors may be used to endorse or promote products derived 2195378Sgibbs * from this software without specific prior written permission. 2239220Sgibbs * 2354211Sgibbs * Alternatively, this software may be distributed under the terms of the 2495378Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2595378Sgibbs * Software Foundation. 2639220Sgibbs * 2795378Sgibbs * NO WARRANTY 2895378Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2995378Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3095378Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3195378Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3295378Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3339220Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3439220Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3595378Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3695378Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3795378Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3895378Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3939220Sgibbs * 40123579Sgibbs * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $ 4165942Sgibbs * 4250477Speter * $FreeBSD$ 4339220Sgibbs */ 4439220Sgibbs 4539220Sgibbs#ifndef _AIC7XXX_H_ 4639220Sgibbs#define _AIC7XXX_H_ 4739220Sgibbs 4865942Sgibbs/* Register Definitions */ 4963457Sgibbs#include "aic7xxx_reg.h" 5039220Sgibbs 5165942Sgibbs/************************* Forward Declarations *******************************/ 5265942Sgibbsstruct ahc_platform_data; 5365942Sgibbsstruct scb_platform_data; 5495378Sgibbsstruct seeprom_descriptor; 5539220Sgibbs 5665942Sgibbs/****************************** Useful Macros *********************************/ 5745965Sgibbs#ifndef MAX 5845965Sgibbs#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 5945965Sgibbs#endif 6045965Sgibbs 6145965Sgibbs#ifndef MIN 6245965Sgibbs#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 6345965Sgibbs#endif 6445965Sgibbs 6565942Sgibbs#ifndef TRUE 6665942Sgibbs#define TRUE 1 6765942Sgibbs#endif 6865942Sgibbs#ifndef FALSE 6965942Sgibbs#define FALSE 0 7065942Sgibbs#endif 7165942Sgibbs 7265942Sgibbs#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 7365942Sgibbs 7465942Sgibbs#define ALL_CHANNELS '\0' 7565942Sgibbs#define ALL_TARGETS_MASK 0xFFFF 7665942Sgibbs#define INITIATOR_WILDCARD (~0) 7765942Sgibbs 7865942Sgibbs#define SCSIID_TARGET(ahc, scsiid) \ 7965942Sgibbs (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 8065942Sgibbs >> TID_SHIFT) 8165942Sgibbs#define SCSIID_OUR_ID(scsiid) \ 8265942Sgibbs ((scsiid) & OID) 8365942Sgibbs#define SCSIID_CHANNEL(ahc, scsiid) \ 8465942Sgibbs ((((ahc)->features & AHC_TWIN) != 0) \ 8565942Sgibbs ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 8665942Sgibbs : 'A') 8765942Sgibbs#define SCB_IS_SCSIBUS_B(ahc, scb) \ 8865942Sgibbs (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 8965942Sgibbs#define SCB_GET_OUR_ID(scb) \ 9065942Sgibbs SCSIID_OUR_ID((scb)->hscb->scsiid) 9165942Sgibbs#define SCB_GET_TARGET(ahc, scb) \ 9265942Sgibbs SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 9365942Sgibbs#define SCB_GET_CHANNEL(ahc, scb) \ 9465942Sgibbs SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 9565942Sgibbs#define SCB_GET_LUN(scb) \ 96115333Sgibbs ((scb)->hscb->lun & LID) 9765942Sgibbs#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 9865942Sgibbs (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 9965942Sgibbs#define SCB_GET_TARGET_MASK(ahc, scb) \ 10065942Sgibbs (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101109590Sgibbs#ifdef AHC_DEBUG 102109590Sgibbs#define SCB_IS_SILENT(scb) \ 103109590Sgibbs ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 104109590Sgibbs && (((scb)->flags & SCB_SILENT) != 0)) 105109590Sgibbs#else 106109590Sgibbs#define SCB_IS_SILENT(scb) \ 107109590Sgibbs (((scb)->flags & SCB_SILENT) != 0) 108109590Sgibbs#endif 10965942Sgibbs#define TCL_TARGET_OFFSET(tcl) \ 11065942Sgibbs ((((tcl) >> 4) & TID) >> 4) 11165942Sgibbs#define TCL_LUN(tcl) \ 11265942Sgibbs (tcl & (AHC_NUM_LUNS - 1)) 11365942Sgibbs#define BUILD_TCL(scsiid, lun) \ 11465942Sgibbs ((lun) | (((scsiid) & TID) << 4)) 11565942Sgibbs 11668579Sgibbs#ifndef AHC_TARGET_MODE 11768579Sgibbs#undef AHC_TMODE_ENABLE 11868579Sgibbs#define AHC_TMODE_ENABLE 0 11968579Sgibbs#endif 12068579Sgibbs 12165942Sgibbs/**************************** Driver Constants ********************************/ 12245965Sgibbs/* 12363457Sgibbs * The maximum number of supported targets. 12463457Sgibbs */ 12563457Sgibbs#define AHC_NUM_TARGETS 16 12663457Sgibbs 12763457Sgibbs/* 12863457Sgibbs * The maximum number of supported luns. 12970204Sgibbs * The identify message only supports 64 luns in SPI3. 13070204Sgibbs * You can have 2^64 luns when information unit transfers are enabled, 13170204Sgibbs * but it is doubtful this driver will ever support IUTs. 13263457Sgibbs */ 13370204Sgibbs#define AHC_NUM_LUNS 64 13463457Sgibbs 13563457Sgibbs/* 13645965Sgibbs * The maximum transfer per S/G segment. 13745965Sgibbs */ 13839220Sgibbs#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 13939220Sgibbs 14045965Sgibbs/* 14171390Sgibbs * The maximum amount of SCB storage in hardware on a controller. 14271390Sgibbs * This value represents an upper bound. Controllers vary in the number 14371390Sgibbs * they actually support. 14471390Sgibbs */ 14571390Sgibbs#define AHC_SCB_MAX 255 14671390Sgibbs 14771390Sgibbs/* 14865942Sgibbs * The maximum number of concurrent transactions supported per driver instance. 14965942Sgibbs * Sequencer Control Blocks (SCBs) store per-transaction information. Although 15065942Sgibbs * the space for SCBs on the host adapter varies by model, the driver will 15165942Sgibbs * page the SCBs between host and controller memory as needed. We are limited 15271390Sgibbs * to 253 because: 15371390Sgibbs * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 15471390Sgibbs * 2) We reserve one value, 255, to represent the invalid element. 15571390Sgibbs * 3) Our input queue scheme requires one SCB to always be reserved 15671390Sgibbs * in advance of queuing any SCBs. This takes us down to 254. 15771390Sgibbs * 4) To handle our output queue correctly on machines that only 15871390Sgibbs * support 32bit stores, we must clear the array 4 bytes at a 15971390Sgibbs * time. To avoid colliding with a DMA write from the sequencer, 16071390Sgibbs * we must be sure that 4 slots are empty when we write to clear 16171390Sgibbs * the queue. This reduces us to 253 SCBs: 1 that just completed 16271390Sgibbs * and the known three additional empty slots in the queue that 16372640Sasmodai * precede it. 16445965Sgibbs */ 16571390Sgibbs#define AHC_MAX_QUEUE 253 16645965Sgibbs 16765942Sgibbs/* 16895378Sgibbs * The maximum amount of SCB storage we allocate in host memory. This 16995378Sgibbs * number should reflect the 1 additional SCB we require to handle our 17095378Sgibbs * qinfifo mechanism. 17195378Sgibbs */ 17295378Sgibbs#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 17395378Sgibbs 17495378Sgibbs/* 17565942Sgibbs * Ring Buffer of incoming target commands. 17665942Sgibbs * We allocate 256 to simplify the logic in the sequencer 17765942Sgibbs * by using the natural wrap point of an 8bit counter. 17865942Sgibbs */ 17965942Sgibbs#define AHC_TMODE_CMDS 256 18039220Sgibbs 18165942Sgibbs/* Reset line assertion time in us */ 182102671Sgibbs#define AHC_BUSRESET_DELAY 25 18339220Sgibbs 184136711Sgibbs/* Phase change constants used in target mode. */ 185136711Sgibbs#define AHC_BUSSETTLE_DELAY 400 186136711Sgibbs#define AHC_DATARELEASE_DELAY 400 187136711Sgibbs 18865942Sgibbs/******************* Chip Characteristics/Operating Settings *****************/ 18963457Sgibbs/* 19065942Sgibbs * Chip Type 19165942Sgibbs * The chip order is from least sophisticated to most sophisticated. 19263457Sgibbs */ 19339220Sgibbstypedef enum { 19439220Sgibbs AHC_NONE = 0x0000, 19539220Sgibbs AHC_CHIPID_MASK = 0x00FF, 19639220Sgibbs AHC_AIC7770 = 0x0001, 19739220Sgibbs AHC_AIC7850 = 0x0002, 19850662Sgibbs AHC_AIC7855 = 0x0003, 19950662Sgibbs AHC_AIC7859 = 0x0004, 20050662Sgibbs AHC_AIC7860 = 0x0005, 20150662Sgibbs AHC_AIC7870 = 0x0006, 20250662Sgibbs AHC_AIC7880 = 0x0007, 20363457Sgibbs AHC_AIC7895 = 0x0008, 20465942Sgibbs AHC_AIC7895C = 0x0009, 20565942Sgibbs AHC_AIC7890 = 0x000a, 20665942Sgibbs AHC_AIC7896 = 0x000b, 20765942Sgibbs AHC_AIC7892 = 0x000c, 20865942Sgibbs AHC_AIC7899 = 0x000d, 20939220Sgibbs AHC_VL = 0x0100, /* Bus type VL */ 21039220Sgibbs AHC_EISA = 0x0200, /* Bus type EISA */ 21139220Sgibbs AHC_PCI = 0x0400, /* Bus type PCI */ 21254211Sgibbs AHC_BUS_MASK = 0x0F00 21339220Sgibbs} ahc_chip; 21439220Sgibbs 21565942Sgibbs/* 21665942Sgibbs * Features available in each chip type. 21765942Sgibbs */ 21839220Sgibbstypedef enum { 21965942Sgibbs AHC_FENONE = 0x00000, 22065942Sgibbs AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 22165942Sgibbs AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 22265942Sgibbs AHC_WIDE = 0x00004, /* Wide Channel */ 22365942Sgibbs AHC_TWIN = 0x00008, /* Twin Channel */ 22465942Sgibbs AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 22565942Sgibbs AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 22665942Sgibbs AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 22765942Sgibbs AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 22865942Sgibbs AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 22965942Sgibbs AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 23065942Sgibbs AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 23165942Sgibbs AHC_DT = 0x00800, /* Double Transition transfers */ 23265942Sgibbs AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 23365942Sgibbs AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 23465942Sgibbs AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 23565942Sgibbs AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 23665942Sgibbs AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 23768087Sgibbs AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 23868087Sgibbs AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 23971390Sgibbs AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 24063457Sgibbs AHC_AIC7770_FE = AHC_FENONE, 24176634Sgibbs /* 24276634Sgibbs * The real 7850 does not support Ultra modes, but there are 24376634Sgibbs * several cards that use the generic 7850 PCI ID even though 24476634Sgibbs * they are using an Ultra capable chip (7859/7860). We start 24576634Sgibbs * out with the AHC_ULTRA feature set and then check the DEVSTATUS 24676634Sgibbs * register to determine if the capability is really present. 24776634Sgibbs */ 24876634Sgibbs AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 24976634Sgibbs AHC_AIC7860_FE = AHC_AIC7850_FE, 250123579Sgibbs AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 25168087Sgibbs AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 25268087Sgibbs /* 25368087Sgibbs * Although we have space for both the initiator and 25468087Sgibbs * target roles on ULTRA2 chips, we currently disable 25568087Sgibbs * the initiator role to allow multi-scsi-id target mode 25668087Sgibbs * configurations. We can only respond on the same SCSI 25768087Sgibbs * ID as our initiator role if we allow initiator operation. 25868087Sgibbs * At some point, we should add a configuration knob to 25968087Sgibbs * allow both roles to be loaded. 26068087Sgibbs */ 26168087Sgibbs AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 26268087Sgibbs |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 26371390Sgibbs |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 26468087Sgibbs |AHC_TARGETMODE, 26565942Sgibbs AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 26665942Sgibbs AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 26763457Sgibbs |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 26855581Sgibbs AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 26955581Sgibbs AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 27055581Sgibbs AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 27139220Sgibbs} ahc_feature; 27239220Sgibbs 27365942Sgibbs/* 27465942Sgibbs * Bugs in the silicon that we work around in software. 27565942Sgibbs */ 27639220Sgibbstypedef enum { 27763457Sgibbs AHC_BUGNONE = 0x00, 27863457Sgibbs /* 27963457Sgibbs * On all chips prior to the U2 product line, 28063457Sgibbs * the WIDEODD S/G segment feature does not 28163457Sgibbs * work during scsi->HostBus transfers. 28263457Sgibbs */ 28363457Sgibbs AHC_TMODE_WIDEODD_BUG = 0x01, 28463457Sgibbs /* 28563457Sgibbs * On the aic7890/91 Rev 0 chips, the autoflush 28663457Sgibbs * feature does not work. A manual flush of 28763457Sgibbs * the DMA FIFO is required. 28863457Sgibbs */ 28963944Sgibbs AHC_AUTOFLUSH_BUG = 0x02, 29063944Sgibbs /* 29165942Sgibbs * On many chips, cacheline streaming does not work. 29263944Sgibbs */ 29363944Sgibbs AHC_CACHETHEN_BUG = 0x04, 29463944Sgibbs /* 29563944Sgibbs * On the aic7896/97 chips, cacheline 29663944Sgibbs * streaming must be enabled. 29763944Sgibbs */ 29865942Sgibbs AHC_CACHETHEN_DIS_BUG = 0x08, 29965942Sgibbs /* 30065942Sgibbs * PCI 2.1 Retry failure on non-empty data fifo. 30165942Sgibbs */ 30265942Sgibbs AHC_PCI_2_1_RETRY_BUG = 0x10, 30365942Sgibbs /* 30465942Sgibbs * Controller does not handle cacheline residuals 30565942Sgibbs * properly on S/G segments if PCI MWI instructions 30665942Sgibbs * are allowed. 30765942Sgibbs */ 30865942Sgibbs AHC_PCI_MWI_BUG = 0x20, 30965942Sgibbs /* 31065942Sgibbs * An SCB upload using the SCB channel's 31165942Sgibbs * auto array entry copy feature may 31265942Sgibbs * corrupt data. This appears to only 31365942Sgibbs * occur on 66MHz systems. 31465942Sgibbs */ 31565942Sgibbs AHC_SCBCHAN_UPLOAD_BUG = 0x40 31663457Sgibbs} ahc_bug; 31763457Sgibbs 31865942Sgibbs/* 31965942Sgibbs * Configuration specific settings. 32065942Sgibbs * The driver determines these settings by probing the 32165942Sgibbs * chip/controller's configuration. 32265942Sgibbs */ 32363457Sgibbstypedef enum { 32474094Sgibbs AHC_FNONE = 0x000, 325109590Sgibbs AHC_PRIMARY_CHANNEL = 0x003, /* 32674094Sgibbs * The channel that should 32774094Sgibbs * be probed first. 32839220Sgibbs */ 329109590Sgibbs AHC_USEDEFAULTS = 0x004, /* 33039220Sgibbs * For cards without an seeprom 33139220Sgibbs * or a BIOS to initialize the chip's 33239220Sgibbs * SRAM, we use the default target 33339220Sgibbs * settings. 33439220Sgibbs */ 33574094Sgibbs AHC_SEQUENCER_DEBUG = 0x008, 33674094Sgibbs AHC_SHARED_SRAM = 0x010, 337109590Sgibbs AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 33874094Sgibbs AHC_RESET_BUS_A = 0x040, 33974094Sgibbs AHC_RESET_BUS_B = 0x080, 34074094Sgibbs AHC_EXTENDED_TRANS_A = 0x100, 34174094Sgibbs AHC_EXTENDED_TRANS_B = 0x200, 34274094Sgibbs AHC_TERM_ENB_A = 0x400, 34374094Sgibbs AHC_TERM_ENB_B = 0x800, 344109590Sgibbs AHC_INITIATORROLE = 0x1000, /* 34541646Sgibbs * Allow initiator operations on 34641646Sgibbs * this controller. 34741646Sgibbs */ 348109590Sgibbs AHC_TARGETROLE = 0x2000, /* 34939220Sgibbs * Allow target operations on this 35039220Sgibbs * controller. 35139220Sgibbs */ 35274094Sgibbs AHC_NEWEEPROM_FMT = 0x4000, 35374094Sgibbs AHC_RESOURCE_SHORTAGE = 0x8000, 354109590Sgibbs AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 355109590Sgibbs AHC_INT50_SPEEDFLEX = 0x20000, /* 35655581Sgibbs * Internal 50pin connector 35755581Sgibbs * sits behind an aic3860 35855581Sgibbs */ 359109590Sgibbs AHC_SCB_BTT = 0x40000, /* 36063457Sgibbs * The busy targets table is 36163457Sgibbs * stored in SCB space rather 36263457Sgibbs * than SRAM. 36363457Sgibbs */ 36474094Sgibbs AHC_BIOS_ENABLED = 0x80000, 36574094Sgibbs AHC_ALL_INTERRUPTS = 0x100000, 366102671Sgibbs AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 367102671Sgibbs AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 368102671Sgibbs AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 369102671Sgibbs AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 370109590Sgibbs AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 371109590Sgibbs AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 372114621Sgibbs AHC_DISABLE_PCI_PERR = 0x10000000, 373123579Sgibbs AHC_HAS_TERM_LOGIC = 0x20000000, 374123579Sgibbs AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */ 37539220Sgibbs} ahc_flag; 37639220Sgibbs 37765942Sgibbs/************************* Hardware SCB Definition ***************************/ 37839220Sgibbs 37939220Sgibbs/* 38039220Sgibbs * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 381114621Sgibbs * consists of a "hardware SCB" mirroring the fields available on the card 38239220Sgibbs * and additional information the kernel stores for each transaction. 38363457Sgibbs * 38463457Sgibbs * To minimize space utilization, a portion of the hardware scb stores 38563457Sgibbs * different data during different portions of a SCSI transaction. 38663457Sgibbs * As initialized by the host driver for the initiator role, this area 38765942Sgibbs * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 38863457Sgibbs * the cdb has been presented to the target, this area serves to store 38963457Sgibbs * residual transfer information and the SCSI status byte. 39063457Sgibbs * For the target role, the contents of this area do not change, but 39163457Sgibbs * still serve a different purpose than for the initiator role. See 39263457Sgibbs * struct target_data for details. 39339220Sgibbs */ 39463457Sgibbs 39565942Sgibbs/* 39665942Sgibbs * Status information embedded in the shared poriton of 39765942Sgibbs * an SCB after passing the cdb to the target. The kernel 39865942Sgibbs * driver will only read this data for transactions that 39965942Sgibbs * complete abnormally (non-zero status byte). 40065942Sgibbs */ 40163457Sgibbsstruct status_pkt { 40265942Sgibbs uint32_t residual_datacnt; /* Residual in the current S/G seg */ 40365942Sgibbs uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 40465942Sgibbs uint8_t scsi_status; /* Standard SCSI status byte */ 40563457Sgibbs}; 40663457Sgibbs 40765942Sgibbs/* 40865942Sgibbs * Target mode version of the shared data SCB segment. 40965942Sgibbs */ 41063457Sgibbsstruct target_data { 41195378Sgibbs uint32_t residual_datacnt; /* Residual in the current S/G seg */ 41295378Sgibbs uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 41395378Sgibbs uint8_t scsi_status; /* SCSI status to give to initiator */ 41495378Sgibbs uint8_t target_phases; /* Bitmap of phases to execute */ 41595378Sgibbs uint8_t data_phase; /* Data-In or Data-Out */ 41695378Sgibbs uint8_t initiator_tag; /* Initiator's transaction tag */ 41763457Sgibbs}; 41863457Sgibbs 419123579Sgibbs#define MAX_CDB_LEN 16 42039220Sgibbsstruct hardware_scb { 42165942Sgibbs/*0*/ union { 42263457Sgibbs /* 42365942Sgibbs * If the cdb is 12 bytes or less, we embed it directly 42465942Sgibbs * in the SCB. For longer cdbs, we embed the address 42565942Sgibbs * of the cdb payload as seen by the chip and a DMA 42665942Sgibbs * is used to pull it in. 42763457Sgibbs */ 42895378Sgibbs uint8_t cdb[12]; 42995378Sgibbs uint32_t cdb_ptr; 43095378Sgibbs struct status_pkt status; 43195378Sgibbs struct target_data tdata; 43263457Sgibbs } shared_data; 43363457Sgibbs/* 43465942Sgibbs * A word about residuals. 43565942Sgibbs * The scb is presented to the sequencer with the dataptr and datacnt 43665942Sgibbs * fields initialized to the contents of the first S/G element to 43765942Sgibbs * transfer. The sgptr field is initialized to the bus address for 43865942Sgibbs * the S/G element that follows the first in the in core S/G array 43965942Sgibbs * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 44065942Sgibbs * S/G entry for this transfer (single S/G element transfer with the 44165942Sgibbs * first elements address and length preloaded in the dataptr/datacnt 44265942Sgibbs * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 44365942Sgibbs * The SG_FULL_RESID flag ensures that the residual will be correctly 44465942Sgibbs * noted even if no data transfers occur. Once the data phase is entered, 44565942Sgibbs * the residual sgptr and datacnt are loaded from the sgptr and the 44665942Sgibbs * datacnt fields. After each S/G element's dataptr and length are 44765942Sgibbs * loaded into the hardware, the residual sgptr is advanced. After 44865942Sgibbs * each S/G element is expired, its datacnt field is checked to see 44965942Sgibbs * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 45065942Sgibbs * residual sg ptr and the transfer is considered complete. If the 45165942Sgibbs * sequencer determines that there is a residual in the tranfer, it 45265942Sgibbs * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 45363457Sgibbs * host memory. To sumarize: 45463457Sgibbs * 45563457Sgibbs * Sequencer: 45663457Sgibbs * o A residual has occurred if SG_FULL_RESID is set in sgptr, 45763457Sgibbs * or residual_sgptr does not have SG_LIST_NULL set. 45863457Sgibbs * 45963457Sgibbs * o We are transfering the last segment if residual_datacnt has 46063457Sgibbs * the SG_LAST_SEG flag set. 46163457Sgibbs * 46263457Sgibbs * Host: 46363457Sgibbs * o A residual has occurred if a completed scb has the 46463457Sgibbs * SG_RESID_VALID flag set. 46563457Sgibbs * 46663457Sgibbs * o residual_sgptr and sgptr refer to the "next" sg entry 46763457Sgibbs * and so may point beyond the last valid sg entry for the 46863457Sgibbs * transfer. 46963457Sgibbs */ 47065942Sgibbs/*12*/ uint32_t dataptr; 47165942Sgibbs/*16*/ uint32_t datacnt; /* 47265942Sgibbs * Byte 3 (numbered from 0) of 47365942Sgibbs * the datacnt is really the 47465942Sgibbs * 4th byte in that data address. 47539220Sgibbs */ 47665942Sgibbs/*20*/ uint32_t sgptr; 47763457Sgibbs#define SG_PTR_MASK 0xFFFFFFF8 47865942Sgibbs/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 47965942Sgibbs/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 48065942Sgibbs/*26*/ uint8_t lun; 48165942Sgibbs/*27*/ uint8_t tag; /* 48265942Sgibbs * Index into our kernel SCB array. 48339220Sgibbs * Also used as the tag for tagged I/O 48439220Sgibbs */ 48565942Sgibbs/*28*/ uint8_t cdb_len; 48663457Sgibbs/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 48763457Sgibbs/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 48865942Sgibbs/*31*/ uint8_t next; /* 48965942Sgibbs * Used for threading SCBs in the 49039220Sgibbs * "Waiting for Selection" and 49139220Sgibbs * "Disconnected SCB" lists down 49239220Sgibbs * in the sequencer. 49339220Sgibbs */ 49463457Sgibbs/*32*/ uint8_t cdb32[32]; /* 49565942Sgibbs * CDB storage for cdbs of size 49665942Sgibbs * 13->32. We store them here 49765942Sgibbs * because hardware scbs are 49865942Sgibbs * allocated from DMA safe 49965942Sgibbs * memory so we are guaranteed 50065942Sgibbs * the controller can access 50165942Sgibbs * this data. 50239220Sgibbs */ 50339220Sgibbs}; 50439220Sgibbs 50565942Sgibbs/************************ Kernel SCB Definitions ******************************/ 50665942Sgibbs/* 50765942Sgibbs * Some fields of the SCB are OS dependent. Here we collect the 50865942Sgibbs * definitions for elements that all OS platforms need to include 50965942Sgibbs * in there SCB definition. 51065942Sgibbs */ 51165942Sgibbs 51265942Sgibbs/* 51365942Sgibbs * Definition of a scatter/gather element as transfered to the controller. 51465942Sgibbs * The aic7xxx chips only support a 24bit length. We use the top byte of 51565942Sgibbs * the length to store additional address bits and a flag to indicate 51665942Sgibbs * that a given segment terminates the transfer. This gives us an 51765942Sgibbs * addressable range of 512GB on machines with 64bit PCI or with chips 51865942Sgibbs * that can support dual address cycles on 32bit PCI busses. 51965942Sgibbs */ 52065942Sgibbsstruct ahc_dma_seg { 52165942Sgibbs uint32_t addr; 52265942Sgibbs uint32_t len; 52365942Sgibbs#define AHC_DMA_LAST_SEG 0x80000000 52465942Sgibbs#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 52565942Sgibbs#define AHC_SG_LEN_MASK 0x00FFFFFF 52665942Sgibbs}; 52765942Sgibbs 52879874Sgibbsstruct sg_map_node { 52979874Sgibbs bus_dmamap_t sg_dmamap; 53079874Sgibbs bus_addr_t sg_physaddr; 53179874Sgibbs struct ahc_dma_seg* sg_vaddr; 53279874Sgibbs SLIST_ENTRY(sg_map_node) links; 53379874Sgibbs}; 53479874Sgibbs 53565942Sgibbs/* 53665942Sgibbs * The current state of this SCB. 53765942Sgibbs */ 53865942Sgibbstypedef enum { 539123579Sgibbs SCB_FLAG_NONE = 0x0000, 54065942Sgibbs SCB_OTHERTCL_TIMEOUT = 0x0002,/* 54165942Sgibbs * Another device was active 54265942Sgibbs * during the first timeout for 54365942Sgibbs * this SCB so we gave ourselves 54465942Sgibbs * an additional timeout period 54565942Sgibbs * in case it was hogging the 54665942Sgibbs * bus. 54765942Sgibbs */ 54865942Sgibbs SCB_DEVICE_RESET = 0x0004, 54965942Sgibbs SCB_SENSE = 0x0008, 55068087Sgibbs SCB_CDB32_PTR = 0x0010, 55174972Sgibbs SCB_RECOVERY_SCB = 0x0020, 55274972Sgibbs SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 55374972Sgibbs SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 554107420Sscottl SCB_ABORT = 0x0100, 555107420Sscottl SCB_UNTAGGEDQ = 0x0200, 556107420Sscottl SCB_ACTIVE = 0x0400, 557107420Sscottl SCB_TARGET_IMMEDIATE = 0x0800, 558107420Sscottl SCB_TRANSMISSION_ERROR = 0x1000,/* 559107420Sscottl * We detected a parity or CRC 560107420Sscottl * error that has effected the 561107420Sscottl * payload of the command. This 562107420Sscottl * flag is checked when normal 563107420Sscottl * status is returned to catch 564107420Sscottl * the case of a target not 565107420Sscottl * responding to our attempt 566107420Sscottl * to report the error. 567107420Sscottl */ 568109590Sgibbs SCB_TARGET_SCB = 0x2000, 569123579Sgibbs SCB_SILENT = 0x4000,/* 570109590Sgibbs * Be quiet about transmission type 571109590Sgibbs * errors. They are expected and we 572109590Sgibbs * don't want to upset the user. This 573109590Sgibbs * flag is typically used during DV. 574109590Sgibbs */ 575123579Sgibbs SCB_TIMEDOUT = 0x8000 /* 576123579Sgibbs * SCB has timed out and is on the 577123579Sgibbs * timedout list. 578123579Sgibbs */ 57965942Sgibbs} scb_flag; 58065942Sgibbs 58139220Sgibbsstruct scb { 58265942Sgibbs struct hardware_scb *hscb; 58363457Sgibbs union { 58465942Sgibbs SLIST_ENTRY(scb) sle; 58565942Sgibbs TAILQ_ENTRY(scb) tqe; 58663457Sgibbs } links; 58765942Sgibbs LIST_ENTRY(scb) pending_links; 588123579Sgibbs LIST_ENTRY(scb) timedout_links; 589123579Sgibbs aic_io_ctx_t io_ctx; 59066986Sgibbs struct ahc_softc *ahc_softc; 59165942Sgibbs scb_flag flags; 59265942Sgibbs#ifndef __linux__ 59365942Sgibbs bus_dmamap_t dmamap; 59465942Sgibbs#endif 59565942Sgibbs struct scb_platform_data *platform_data; 59679874Sgibbs struct sg_map_node *sg_map; 59779874Sgibbs struct ahc_dma_seg *sg_list; 59865942Sgibbs bus_addr_t sg_list_phys; 59965942Sgibbs u_int sg_count;/* How full ahc_dma_seg is */ 600168807Sscottl aic_timer_t io_timer; 60139220Sgibbs}; 60239220Sgibbs 60365942Sgibbsstruct scb_data { 60465942Sgibbs SLIST_HEAD(, scb) free_scbs; /* 60565942Sgibbs * Pool of SCBs ready to be assigned 60665942Sgibbs * commands to execute. 60765942Sgibbs */ 60895378Sgibbs struct scb *scbindex[256]; /* 60995378Sgibbs * Mapping from tag to SCB. 61095378Sgibbs * As tag identifiers are an 61195378Sgibbs * 8bit value, we provide space 61295378Sgibbs * for all possible tag values. 61395378Sgibbs * Any lookups to entries at or 61495378Sgibbs * above AHC_SCB_MAX_ALLOC will 61595378Sgibbs * always fail. 61695378Sgibbs */ 61766647Sgibbs struct hardware_scb *hscbs; /* Array of hardware SCBs */ 61866647Sgibbs struct scb *scbarray; /* Array of kernel SCBs */ 61965942Sgibbs struct scsi_sense_data *sense; /* Per SCB sense data */ 62065942Sgibbs 621133911Sgibbs u_int recovery_scbs; /* Transactions currently in recovery */ 622133911Sgibbs 62365942Sgibbs /* 62465942Sgibbs * "Bus" addresses of our data structures. 62565942Sgibbs */ 62665942Sgibbs bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 62765942Sgibbs bus_dmamap_t hscb_dmamap; 62865942Sgibbs bus_addr_t hscb_busaddr; 62965942Sgibbs bus_dma_tag_t sense_dmat; 63065942Sgibbs bus_dmamap_t sense_dmamap; 63165942Sgibbs bus_addr_t sense_busaddr; 63265942Sgibbs bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 63365942Sgibbs SLIST_HEAD(, sg_map_node) sg_maps; 63465942Sgibbs uint8_t numscbs; 63565942Sgibbs uint8_t maxhscbs; /* Number of SCBs on the card */ 63665942Sgibbs uint8_t init_level; /* 63765942Sgibbs * How far we've initialized 63865942Sgibbs * this structure. 63965942Sgibbs */ 64065942Sgibbs}; 64165942Sgibbs 64265942Sgibbs/************************ Target Mode Definitions *****************************/ 64365942Sgibbs 64439220Sgibbs/* 64539220Sgibbs * Connection desciptor for select-in requests in target mode. 64639220Sgibbs */ 64739220Sgibbsstruct target_cmd { 64865942Sgibbs uint8_t scsiid; /* Our ID and the initiator's ID */ 64963457Sgibbs uint8_t identify; /* Identify message */ 65065942Sgibbs uint8_t bytes[22]; /* 65165942Sgibbs * Bytes contains any additional message 65265942Sgibbs * bytes terminated by 0xFF. The remainder 65365942Sgibbs * is the cdb to execute. 65465942Sgibbs */ 65565942Sgibbs uint8_t cmd_valid; /* 65665942Sgibbs * When a command is complete, the firmware 65765942Sgibbs * will set cmd_valid to all bits set. 65865942Sgibbs * After the host has seen the command, 65965942Sgibbs * the bits are cleared. This allows us 66065942Sgibbs * to just peek at host memory to determine 66165942Sgibbs * if more work is complete. cmd_valid is on 66265942Sgibbs * an 8 byte boundary to simplify setting 66365942Sgibbs * it on aic7880 hardware which only has 66465942Sgibbs * limited direct access to the DMA FIFO. 66565942Sgibbs */ 66663457Sgibbs uint8_t pad[7]; 66739220Sgibbs}; 66839220Sgibbs 66939220Sgibbs/* 67049933Sgibbs * Number of events we can buffer up if we run out 67149933Sgibbs * of immediate notify ccbs. 67249933Sgibbs */ 67349933Sgibbs#define AHC_TMODE_EVENT_BUFFER_SIZE 8 67449933Sgibbsstruct ahc_tmode_event { 67563457Sgibbs uint8_t initiator_id; 67663457Sgibbs uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 67749933Sgibbs#define EVENT_TYPE_BUS_RESET 0xFF 67863457Sgibbs uint8_t event_arg; 67949933Sgibbs}; 68049933Sgibbs 68149933Sgibbs/* 68265942Sgibbs * Per enabled lun target mode state. 68365942Sgibbs * As this state is directly influenced by the host OS'es target mode 68465942Sgibbs * environment, we let the OS module define it. Forward declare the 68565942Sgibbs * structure here so we can store arrays of them, etc. in OS neutral 68665942Sgibbs * data structures. 68739220Sgibbs */ 68865942Sgibbs#ifdef AHC_TARGET_MODE 68974972Sgibbsstruct ahc_tmode_lstate { 69049933Sgibbs struct cam_path *path; 69141816Sgibbs struct ccb_hdr_slist accept_tios; 69241816Sgibbs struct ccb_hdr_slist immed_notifies; 69349933Sgibbs struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 69463457Sgibbs uint8_t event_r_idx; 69563457Sgibbs uint8_t event_w_idx; 69639220Sgibbs}; 69765942Sgibbs#else 69874972Sgibbsstruct ahc_tmode_lstate; 69965942Sgibbs#endif 70039220Sgibbs 70165942Sgibbs/******************** Transfer Negotiation Datastructures *********************/ 70244507Sgibbs#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 70365942Sgibbs#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 70444507Sgibbs#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 70544507Sgibbs#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 70644507Sgibbs 707107420Sscottl#define AHC_WIDTH_UNKNOWN 0xFF 708107420Sscottl#define AHC_PERIOD_UNKNOWN 0xFF 709114621Sgibbs#define AHC_OFFSET_UNKNOWN 0xFF 710107420Sscottl#define AHC_PPR_OPTS_UNKNOWN 0xFF 711107420Sscottl 71265942Sgibbs/* 71365942Sgibbs * Transfer Negotiation Information. 71465942Sgibbs */ 71544507Sgibbsstruct ahc_transinfo { 71665942Sgibbs uint8_t protocol_version; /* SCSI Revision level */ 71765942Sgibbs uint8_t transport_version; /* SPI Revision level */ 71865942Sgibbs uint8_t width; /* Bus width */ 71965942Sgibbs uint8_t period; /* Sync rate factor */ 72065942Sgibbs uint8_t offset; /* Sync offset */ 72165942Sgibbs uint8_t ppr_options; /* Parallel Protocol Request options */ 72244507Sgibbs}; 72344507Sgibbs 72465942Sgibbs/* 72565942Sgibbs * Per-initiator current, goal and user transfer negotiation information. */ 72644507Sgibbsstruct ahc_initiator_tinfo { 72765942Sgibbs uint8_t scsirate; /* Computed value for SCSIRATE reg */ 72876634Sgibbs struct ahc_transinfo curr; 72944507Sgibbs struct ahc_transinfo goal; 73044507Sgibbs struct ahc_transinfo user; 73144507Sgibbs}; 73244507Sgibbs 73339220Sgibbs/* 73465942Sgibbs * Per enabled target ID state. 73565942Sgibbs * Pointers to lun target state as well as sync/wide negotiation information 73665942Sgibbs * for each initiator<->target mapping. For the initiator role we pretend 73765942Sgibbs * that we are the target and the targets are the initiators since the 73865942Sgibbs * negotiation is the same regardless of role. 73939220Sgibbs */ 74074972Sgibbsstruct ahc_tmode_tstate { 74174972Sgibbs struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 74270204Sgibbs struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 74344507Sgibbs 74444507Sgibbs /* 74544507Sgibbs * Per initiator state bitmasks. 74644507Sgibbs */ 74774972Sgibbs uint16_t auto_negotiate;/* Auto Negotiation Required */ 74874972Sgibbs uint16_t ultraenb; /* Using ultra sync rate */ 74974972Sgibbs uint16_t discenable; /* Disconnection allowed */ 75074972Sgibbs uint16_t tagenable; /* Tagged Queuing allowed */ 75139220Sgibbs}; 75239220Sgibbs 75339220Sgibbs/* 75465942Sgibbs * Data structure for our table of allowed synchronous transfer rates. 75539220Sgibbs */ 75665942Sgibbsstruct ahc_syncrate { 75765942Sgibbs u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 75865942Sgibbs u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 75965942Sgibbs#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 76065942Sgibbs#define ST_SXFR 0x010 /* Rate Single Transition Only */ 76165942Sgibbs#define DT_SXFR 0x040 /* Rate Double Transition Only */ 76265942Sgibbs uint8_t period; /* Period to send to SCSI target */ 76365942Sgibbs char *rate; 76465942Sgibbs}; 76539220Sgibbs 766107420Sscottl/* Safe and valid period for async negotiations. */ 767109590Sgibbs#define AHC_ASYNC_XFER_PERIOD 0x45 768107420Sscottl#define AHC_ULTRA2_XFER_PERIOD 0x0a 769107420Sscottl 77065942Sgibbs/* 771250460Seadler * Indexes into our table of synchronous transfer rates. 77265942Sgibbs */ 77365942Sgibbs#define AHC_SYNCRATE_DT 0 77465942Sgibbs#define AHC_SYNCRATE_ULTRA2 1 77565942Sgibbs#define AHC_SYNCRATE_ULTRA 3 77665942Sgibbs#define AHC_SYNCRATE_FAST 6 777109590Sgibbs#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 778109590Sgibbs#define AHC_SYNCRATE_MIN 13 77965942Sgibbs 78065942Sgibbs/***************************** Lookup Tables **********************************/ 78165942Sgibbs/* 78265942Sgibbs * Phase -> name and message out response 78365942Sgibbs * to parity errors in each phase table. 78465942Sgibbs */ 78574094Sgibbsstruct ahc_phase_table_entry { 78665942Sgibbs uint8_t phase; 78765942Sgibbs uint8_t mesg_out; /* Message response to parity errors */ 78865942Sgibbs char *phasemsg; 78965942Sgibbs}; 79065942Sgibbs 79165942Sgibbs/************************** Serial EEPROM Format ******************************/ 79265942Sgibbs 79339220Sgibbsstruct seeprom_config { 79439220Sgibbs/* 79565942Sgibbs * Per SCSI ID Configuration Flags 79639220Sgibbs */ 79763457Sgibbs uint16_t device_flags[16]; /* words 0-15 */ 79839220Sgibbs#define CFXFER 0x0007 /* synchronous transfer rate */ 79939220Sgibbs#define CFSYNCH 0x0008 /* enable synchronous transfer */ 80039220Sgibbs#define CFDISC 0x0010 /* enable disconnection */ 80139220Sgibbs#define CFWIDEB 0x0020 /* wide bus device */ 80239220Sgibbs#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 80355581Sgibbs#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 80439220Sgibbs#define CFSTART 0x0100 /* send start unit SCSI command */ 80539220Sgibbs#define CFINCBIOS 0x0200 /* include in BIOS scan */ 80639220Sgibbs#define CFRNFOUND 0x0400 /* report even if not found */ 80763457Sgibbs#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 80855581Sgibbs#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 80955581Sgibbs#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 81039220Sgibbs 81139220Sgibbs/* 81239220Sgibbs * BIOS Control Bits 81339220Sgibbs */ 81463457Sgibbs uint16_t bios_control; /* word 16 */ 81539220Sgibbs#define CFSUPREM 0x0001 /* support all removeable drives */ 81655581Sgibbs#define CFSUPREMB 0x0002 /* support removeable boot drives */ 81739220Sgibbs#define CFBIOSEN 0x0004 /* BIOS enabled */ 81876634Sgibbs#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 81939220Sgibbs#define CFSM2DRV 0x0010 /* support more than two drives */ 82076634Sgibbs#define CFSTPWLEVEL 0x0010 /* Termination level control */ 82139220Sgibbs#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 82276634Sgibbs#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 82376634Sgibbs#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 82439220Sgibbs#define CFEXTEND 0x0080 /* extended translation enabled */ 82563457Sgibbs#define CFSCAMEN 0x0100 /* SCAM enable */ 82676634Sgibbs#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 82776634Sgibbs#define CFMSG_VERBOSE 0x0000 82876634Sgibbs#define CFMSG_SILENT 0x0200 82976634Sgibbs#define CFMSG_DIAG 0x0400 83076634Sgibbs#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 83139220Sgibbs/* UNUSED 0xff00 */ 83239220Sgibbs 83339220Sgibbs/* 83439220Sgibbs * Host Adapter Control Bits 83539220Sgibbs */ 83663457Sgibbs uint16_t adapter_control; /* word 17 */ 83739220Sgibbs#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 83839220Sgibbs#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 83939220Sgibbs#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 84039220Sgibbs#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 84139220Sgibbs#define CFSTERM 0x0004 /* SCSI low byte termination */ 84239220Sgibbs#define CFWSTERM 0x0008 /* SCSI high byte termination */ 84339220Sgibbs#define CFSPARITY 0x0010 /* SCSI parity */ 84439220Sgibbs#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 84576634Sgibbs#define CFMULTILUN 0x0020 84639220Sgibbs#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 84763457Sgibbs#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 84874094Sgibbs#define CFBOOTCHAN 0x0300 /* probe this channel first */ 84974094Sgibbs#define CFBOOTCHANSHIFT 8 85063457Sgibbs#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 85163457Sgibbs#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 85263457Sgibbs#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 853107420Sscottl#define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 85439220Sgibbs 85539220Sgibbs/* 85665942Sgibbs * Bus Release Time, Host Adapter ID 85739220Sgibbs */ 85863457Sgibbs uint16_t brtime_id; /* word 18 */ 85939220Sgibbs#define CFSCSIID 0x000f /* host adapter SCSI ID */ 86039220Sgibbs/* UNUSED 0x00f0 */ 86139220Sgibbs#define CFBRTIME 0xff00 /* bus release time */ 86239220Sgibbs 86339220Sgibbs/* 86439220Sgibbs * Maximum targets 86539220Sgibbs */ 86663457Sgibbs uint16_t max_targets; /* word 19 */ 86739220Sgibbs#define CFMAXTARG 0x00ff /* maximum targets */ 86863457Sgibbs#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 86963457Sgibbs#define CFBOOTID 0xf000 /* Target to boot from */ 87063457Sgibbs uint16_t res_1[10]; /* words 20-29 */ 87163457Sgibbs uint16_t signature; /* Signature == 0x250 */ 87263457Sgibbs#define CFSIGNATURE 0x250 87374094Sgibbs#define CFSIGNATURE2 0x300 87463457Sgibbs uint16_t checksum; /* word 31 */ 87539220Sgibbs}; 87639220Sgibbs 87765942Sgibbs/**************************** Message Buffer *********************************/ 87839220Sgibbstypedef enum { 87939220Sgibbs MSG_TYPE_NONE = 0x00, 88039220Sgibbs MSG_TYPE_INITIATOR_MSGOUT = 0x01, 88141646Sgibbs MSG_TYPE_INITIATOR_MSGIN = 0x02, 88241646Sgibbs MSG_TYPE_TARGET_MSGOUT = 0x03, 88341646Sgibbs MSG_TYPE_TARGET_MSGIN = 0x04 88439220Sgibbs} ahc_msg_type; 88539220Sgibbs 88665942Sgibbstypedef enum { 88765942Sgibbs MSGLOOP_IN_PROG, 88865942Sgibbs MSGLOOP_MSGCOMPLETE, 88965942Sgibbs MSGLOOP_TERMINATED 89065942Sgibbs} msg_loop_stat; 89145965Sgibbs 89265942Sgibbs/*********************** Software Configuration Structure *********************/ 89363457SgibbsTAILQ_HEAD(scb_tailq, scb); 89463457Sgibbs 895114621Sgibbsstruct ahc_aic7770_softc { 896114621Sgibbs /* 897114621Sgibbs * Saved register state used for chip_init(). 898114621Sgibbs */ 899114621Sgibbs uint8_t busspd; 900114621Sgibbs uint8_t bustime; 90170693Sgibbs}; 90270693Sgibbs 903114621Sgibbsstruct ahc_pci_softc { 904114621Sgibbs /* 905114621Sgibbs * Saved register state used for chip_init(). 906114621Sgibbs */ 907114621Sgibbs uint32_t devconfig; 908114621Sgibbs uint16_t targcrccnt; 909114621Sgibbs uint8_t command; 910114621Sgibbs uint8_t csize_lattime; 911114621Sgibbs uint8_t optionmode; 912114621Sgibbs uint8_t crccontrol1; 913114621Sgibbs uint8_t dscommand0; 914114621Sgibbs uint8_t dspcistatus; 915114621Sgibbs uint8_t scbbaddr; 916114621Sgibbs uint8_t dff_thrsh; 91770204Sgibbs}; 91870204Sgibbs 919114621Sgibbsunion ahc_bus_softc { 920114621Sgibbs struct ahc_aic7770_softc aic7770_softc; 921114621Sgibbs struct ahc_pci_softc pci_softc; 922114621Sgibbs}; 923114621Sgibbs 92474972Sgibbstypedef void (*ahc_bus_intr_t)(struct ahc_softc *); 925114621Sgibbstypedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 926114621Sgibbstypedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 927114621Sgibbstypedef int (*ahc_bus_resume_t)(struct ahc_softc *); 928107420Sscottltypedef void ahc_callback_t (void *); 92974972Sgibbs 930133911Sgibbs#define AIC_SCB_DATA(softc) ((softc)->scb_data) 931133911Sgibbs 93239220Sgibbsstruct ahc_softc { 93365942Sgibbs bus_space_tag_t tag; 93465942Sgibbs bus_space_handle_t bsh; 93565942Sgibbs#ifndef __linux__ 93665942Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 93765942Sgibbs#endif 93865942Sgibbs struct scb_data *scb_data; 93939220Sgibbs 94066647Sgibbs struct scb *next_queued_scb; 94166647Sgibbs 94239220Sgibbs /* 94365942Sgibbs * SCBs that have been sent to the controller 94439220Sgibbs */ 94579874Sgibbs LIST_HEAD(, scb) pending_scbs; 94639220Sgibbs 94739220Sgibbs /* 948123579Sgibbs * SCBs whose timeout routine has been called. 949123579Sgibbs */ 950123579Sgibbs LIST_HEAD(, scb) timedout_scbs; 951123579Sgibbs 952123579Sgibbs /* 95363457Sgibbs * Counting lock for deferring the release of additional 95463457Sgibbs * untagged transactions from the untagged_queues. When 95563457Sgibbs * the lock is decremented to 0, all queues in the 95663457Sgibbs * untagged_queues array are run. 95763457Sgibbs */ 95865942Sgibbs u_int untagged_queue_lock; 95963457Sgibbs 96063457Sgibbs /* 96163457Sgibbs * Per-target queue of untagged-transactions. The 96263457Sgibbs * transaction at the head of the queue is the 96363457Sgibbs * currently pending untagged transaction for the 96463457Sgibbs * target. The driver only allows a single untagged 96563457Sgibbs * transaction per target. 96663457Sgibbs */ 96770204Sgibbs struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 96863457Sgibbs 96963457Sgibbs /* 970114621Sgibbs * Bus attachment specific data. 971114621Sgibbs */ 972114621Sgibbs union ahc_bus_softc bus_softc; 973114621Sgibbs 974114621Sgibbs /* 97565942Sgibbs * Platform specific data. 97665942Sgibbs */ 97765942Sgibbs struct ahc_platform_data *platform_data; 97865942Sgibbs 97965942Sgibbs /* 98065942Sgibbs * Platform specific device information. 98165942Sgibbs */ 982123579Sgibbs aic_dev_softc_t dev_softc; 98365942Sgibbs 98465942Sgibbs /* 98574972Sgibbs * Bus specific device information. 98674972Sgibbs */ 98774972Sgibbs ahc_bus_intr_t bus_intr; 98874972Sgibbs 98974972Sgibbs /* 990114621Sgibbs * Bus specific initialization required 991114621Sgibbs * after a chip reset. 992114621Sgibbs */ 993114621Sgibbs ahc_bus_chip_init_t bus_chip_init; 994114621Sgibbs 995114621Sgibbs /* 996114621Sgibbs * Bus specific suspend routine. 997114621Sgibbs */ 998114621Sgibbs ahc_bus_suspend_t bus_suspend; 999114621Sgibbs 1000114621Sgibbs /* 1001114621Sgibbs * Bus specific resume routine. 1002114621Sgibbs */ 1003114621Sgibbs ahc_bus_resume_t bus_resume; 1004114621Sgibbs 1005114621Sgibbs /* 100639220Sgibbs * Target mode related state kept on a per enabled lun basis. 100739220Sgibbs * Targets that are not enabled will have null entries. 100844507Sgibbs * As an initiator, we keep one target entry for our initiator 100944507Sgibbs * ID to store our sync/wide transfer settings. 101039220Sgibbs */ 101174972Sgibbs struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 101239220Sgibbs 101339220Sgibbs /* 101442652Sgibbs * The black hole device responsible for handling requests for 101542652Sgibbs * disabled luns on enabled targets. 101642652Sgibbs */ 101774972Sgibbs struct ahc_tmode_lstate *black_hole; 101842652Sgibbs 101942652Sgibbs /* 102039220Sgibbs * Device instance currently on the bus awaiting a continue TIO 102139220Sgibbs * for a command that was not given the disconnect priveledge. 102239220Sgibbs */ 102374972Sgibbs struct ahc_tmode_lstate *pending_device; 102439220Sgibbs 102539220Sgibbs /* 102639220Sgibbs * Card characteristics 102739220Sgibbs */ 102865942Sgibbs ahc_chip chip; 102965942Sgibbs ahc_feature features; 103065942Sgibbs ahc_bug bugs; 103165942Sgibbs ahc_flag flags; 1032102671Sgibbs struct seeprom_config *seep_config; 103339220Sgibbs 103439220Sgibbs /* Values to store in the SEQCTL register for pause and unpause */ 103565942Sgibbs uint8_t unpause; 103665942Sgibbs uint8_t pause; 103739220Sgibbs 103839220Sgibbs /* Command Queues */ 103965942Sgibbs uint8_t qoutfifonext; 104065942Sgibbs uint8_t qinfifonext; 104165942Sgibbs uint8_t *qoutfifo; 104265942Sgibbs uint8_t *qinfifo; 104339220Sgibbs 104466647Sgibbs /* Critical Section Data */ 104566647Sgibbs struct cs *critical_sections; 104666647Sgibbs u_int num_critical_sections; 104766647Sgibbs 104865942Sgibbs /* Links for chaining softcs */ 104965942Sgibbs TAILQ_ENTRY(ahc_softc) links; 105039220Sgibbs 105139220Sgibbs /* Channel Names ('A', 'B', etc.) */ 105265942Sgibbs char channel; 105365942Sgibbs char channel_b; 105439220Sgibbs 105539220Sgibbs /* Initiator Bus ID */ 105665942Sgibbs uint8_t our_id; 105765942Sgibbs uint8_t our_id_b; 105839220Sgibbs 105939220Sgibbs /* 106065942Sgibbs * PCI error detection. 106139220Sgibbs */ 106265942Sgibbs int unsolicited_ints; 106339220Sgibbs 106441299Sgibbs /* 106541299Sgibbs * Target incoming command FIFO. 106641299Sgibbs */ 106765942Sgibbs struct target_cmd *targetcmds; 106865942Sgibbs uint8_t tqinfifonext; 106939220Sgibbs 107039220Sgibbs /* 1071115332Sgibbs * Cached copy of the sequencer control register. 1072115332Sgibbs */ 1073115332Sgibbs uint8_t seqctl; 1074115332Sgibbs 1075115332Sgibbs /* 107639220Sgibbs * Incoming and outgoing message handling. 107739220Sgibbs */ 107865942Sgibbs uint8_t send_msg_perror; 107965942Sgibbs ahc_msg_type msg_type; 108066269Sgibbs uint8_t msgout_buf[12];/* Message we are sending */ 108166269Sgibbs uint8_t msgin_buf[12];/* Message we are receiving */ 108265942Sgibbs u_int msgout_len; /* Length of message to send */ 108365942Sgibbs u_int msgout_index; /* Current index in msgout */ 108465942Sgibbs u_int msgin_index; /* Current index in msgin */ 108539220Sgibbs 108665942Sgibbs /* 108765942Sgibbs * Mapping information for data structures shared 108865942Sgibbs * between the sequencer and kernel. 108965942Sgibbs */ 109065942Sgibbs bus_dma_tag_t parent_dmat; 109165942Sgibbs bus_dma_tag_t shared_data_dmat; 109265942Sgibbs bus_dmamap_t shared_data_dmamap; 109365942Sgibbs bus_addr_t shared_data_busaddr; 109445965Sgibbs 109565942Sgibbs /* 109665942Sgibbs * Bus address of the one byte buffer used to 109765942Sgibbs * work-around a DMA bug for chips <= aic7880 109865942Sgibbs * in target mode. 109965942Sgibbs */ 110065942Sgibbs bus_addr_t dma_bug_buf; 110165942Sgibbs 110244507Sgibbs /* Number of enabled target mode device on this card */ 110365942Sgibbs u_int enabled_luns; 110442652Sgibbs 110545965Sgibbs /* Initialization level of this data structure */ 110665942Sgibbs u_int init_level; 110749933Sgibbs 110865942Sgibbs /* PCI cacheline size. */ 110965942Sgibbs u_int pci_cachesize; 111039220Sgibbs 1111114621Sgibbs /* 1112114621Sgibbs * Count of parity errors we have seen as a target. 1113114621Sgibbs * We auto-disable parity error checking after seeing 1114114621Sgibbs * AHC_PCI_TARGET_PERR_THRESH number of errors. 1115114621Sgibbs */ 1116114621Sgibbs u_int pci_target_perr_count; 1117114621Sgibbs#define AHC_PCI_TARGET_PERR_THRESH 10 1118107420Sscottl 1119114621Sgibbs /* Maximum number of sequencer instructions supported. */ 1120114621Sgibbs u_int instruction_ram_size; 1121114621Sgibbs 112265942Sgibbs /* Per-Unit descriptive information */ 112365942Sgibbs const char *description; 112465942Sgibbs char *name; 112565942Sgibbs int unit; 112665942Sgibbs 112770693Sgibbs /* Selection Timer settings */ 112870693Sgibbs int seltime; 112970693Sgibbs int seltime_b; 113070693Sgibbs 113165942Sgibbs uint16_t user_discenable;/* Disconnection allowed */ 113265942Sgibbs uint16_t user_tagenable;/* Tagged Queuing allowed */ 113339220Sgibbs}; 113439220Sgibbs 113565942SgibbsTAILQ_HEAD(ahc_softc_tailq, ahc_softc); 113665942Sgibbsextern struct ahc_softc_tailq ahc_tailq; 113739220Sgibbs 113865942Sgibbs/************************ Active Device Information ***************************/ 113965942Sgibbstypedef enum { 114065942Sgibbs ROLE_UNKNOWN, 114165942Sgibbs ROLE_INITIATOR, 114265942Sgibbs ROLE_TARGET 114365942Sgibbs} role_t; 114439220Sgibbs 114565942Sgibbsstruct ahc_devinfo { 114665942Sgibbs int our_scsiid; 114765942Sgibbs int target_offset; 114865942Sgibbs uint16_t target_mask; 114965942Sgibbs u_int target; 115065942Sgibbs u_int lun; 115165942Sgibbs char channel; 115265942Sgibbs role_t role; /* 115365942Sgibbs * Only guaranteed to be correct if not 115465942Sgibbs * in the busfree state. 115565942Sgibbs */ 115665942Sgibbs}; 115763457Sgibbs 115865942Sgibbs/****************************** PCI Structures ********************************/ 1159123579Sgibbs#define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 1160123579Sgibbs#define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 1161123579Sgibbs 116279874Sgibbstypedef int (ahc_device_setup_t)(struct ahc_softc *); 116363457Sgibbs 116465942Sgibbsstruct ahc_pci_identity { 116565942Sgibbs uint64_t full_id; 116665942Sgibbs uint64_t id_mask; 116765942Sgibbs char *name; 116865942Sgibbs ahc_device_setup_t *setup; 116965942Sgibbs}; 1170115914Sgibbsextern struct ahc_pci_identity ahc_pci_ident_table[]; 117170204Sgibbsextern const u_int ahc_num_pci_devs; 117263457Sgibbs 117365942Sgibbs/***************************** VL/EISA Declarations ***************************/ 117465942Sgibbsstruct aic7770_identity { 117565942Sgibbs uint32_t full_id; 117665942Sgibbs uint32_t id_mask; 1177115914Sgibbs const char *name; 117865942Sgibbs ahc_device_setup_t *setup; 117965942Sgibbs}; 1180115914Sgibbsextern struct aic7770_identity aic7770_ident_table[]; 118165942Sgibbsextern const int ahc_num_aic7770_devs; 118263457Sgibbs 1183133964Sgibbs#define AHC_EISA_SLOT_SIZE 0x1000 118465942Sgibbs#define AHC_EISA_SLOT_OFFSET 0xc00 118565942Sgibbs#define AHC_EISA_IOSIZE 0x100 118639220Sgibbs 118765942Sgibbs/*************************** Function Declarations ****************************/ 118865942Sgibbs/******************************************************************************/ 118970204Sgibbsu_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 119070204Sgibbsvoid ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 119170204Sgibbsvoid ahc_busy_tcl(struct ahc_softc *ahc, 119270204Sgibbs u_int tcl, u_int busyid); 119339220Sgibbs 119465942Sgibbs/***************************** PCI Front End *********************************/ 1195123579Sgibbsstruct ahc_pci_identity *ahc_find_pci_device(aic_dev_softc_t); 119665942Sgibbsint ahc_pci_config(struct ahc_softc *, 119765942Sgibbs struct ahc_pci_identity *); 1198107420Sscottlint ahc_pci_test_register_access(struct ahc_softc *); 119939220Sgibbs 120065942Sgibbs/*************************** EISA/VL Front End ********************************/ 120165942Sgibbsstruct aic7770_identity *aic7770_find_device(uint32_t); 120265942Sgibbsint aic7770_config(struct ahc_softc *ahc, 120395378Sgibbs struct aic7770_identity *, 120495378Sgibbs u_int port); 120539220Sgibbs 120665942Sgibbs/************************** SCB and SCB queue management **********************/ 120765942Sgibbsint ahc_probe_scbs(struct ahc_softc *); 120865942Sgibbsvoid ahc_run_untagged_queues(struct ahc_softc *ahc); 120965942Sgibbsvoid ahc_run_untagged_queue(struct ahc_softc *ahc, 121065942Sgibbs struct scb_tailq *queue); 121168087Sgibbsvoid ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 121268087Sgibbs struct scb *scb); 121368087Sgibbsint ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 121468087Sgibbs int target, char channel, int lun, 121568087Sgibbs u_int tag, role_t role); 121639220Sgibbs 121765942Sgibbs/****************************** Initialization ********************************/ 121865942Sgibbsstruct ahc_softc *ahc_alloc(void *platform_arg, char *name); 121979874Sgibbsint ahc_softc_init(struct ahc_softc *); 122065942Sgibbsvoid ahc_controller_info(struct ahc_softc *ahc, char *buf); 1221114621Sgibbsint ahc_chip_init(struct ahc_softc *ahc); 122265942Sgibbsint ahc_init(struct ahc_softc *ahc); 122374972Sgibbsvoid ahc_intr_enable(struct ahc_softc *ahc, int enable); 122470204Sgibbsvoid ahc_pause_and_flushwork(struct ahc_softc *ahc); 122570204Sgibbsint ahc_suspend(struct ahc_softc *ahc); 122670204Sgibbsint ahc_resume(struct ahc_softc *ahc); 122765942Sgibbsvoid ahc_softc_insert(struct ahc_softc *); 122865942Sgibbsvoid ahc_set_unit(struct ahc_softc *, int); 122965942Sgibbsvoid ahc_set_name(struct ahc_softc *, char *); 1230168873Sscottlint ahc_alloc_scbs(struct ahc_softc *ahc); 123165942Sgibbsvoid ahc_free(struct ahc_softc *ahc); 1232115917Sgibbsint ahc_reset(struct ahc_softc *ahc, int reinit); 123365942Sgibbsvoid ahc_shutdown(void *arg); 123454211Sgibbs 123565942Sgibbs/*************************** Interrupt Services *******************************/ 123665942Sgibbsvoid ahc_clear_intstat(struct ahc_softc *ahc); 123765942Sgibbsvoid ahc_run_qoutfifo(struct ahc_softc *ahc); 123865942Sgibbs#ifdef AHC_TARGET_MODE 123965942Sgibbsvoid ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 124065942Sgibbs#endif 124165942Sgibbsvoid ahc_handle_brkadrint(struct ahc_softc *ahc); 124265942Sgibbsvoid ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 124365942Sgibbsvoid ahc_handle_scsiint(struct ahc_softc *ahc, 124465942Sgibbs u_int intstat); 124566647Sgibbsvoid ahc_clear_critical_section(struct ahc_softc *ahc); 124663457Sgibbs 124765942Sgibbs/***************************** Error Recovery *********************************/ 124865942Sgibbstypedef enum { 124965942Sgibbs SEARCH_COMPLETE, 125065942Sgibbs SEARCH_COUNT, 125165942Sgibbs SEARCH_REMOVE 125265942Sgibbs} ahc_search_action; 125365942Sgibbsint ahc_search_qinfifo(struct ahc_softc *ahc, int target, 125465942Sgibbs char channel, int lun, u_int tag, 125565942Sgibbs role_t role, uint32_t status, 125665942Sgibbs ahc_search_action action); 1257102671Sgibbsint ahc_search_untagged_queues(struct ahc_softc *ahc, 1258123579Sgibbs aic_io_ctx_t ctx, 1259102671Sgibbs int target, char channel, 1260102671Sgibbs int lun, uint32_t status, 1261102671Sgibbs ahc_search_action action); 126265942Sgibbsint ahc_search_disc_list(struct ahc_softc *ahc, int target, 126365942Sgibbs char channel, int lun, u_int tag, 126465942Sgibbs int stop_on_first, int remove, 126565942Sgibbs int save_state); 126665942Sgibbsvoid ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 126765942Sgibbsint ahc_reset_channel(struct ahc_softc *ahc, char channel, 126865942Sgibbs int initiate_reset); 126995378Sgibbsint ahc_abort_scbs(struct ahc_softc *ahc, int target, 127095378Sgibbs char channel, int lun, u_int tag, 127195378Sgibbs role_t role, uint32_t status); 127274094Sgibbsvoid ahc_restart(struct ahc_softc *ahc); 127395378Sgibbsvoid ahc_calc_residual(struct ahc_softc *ahc, 127495378Sgibbs struct scb *scb); 1275123579Sgibbsvoid ahc_timeout(struct scb *scb); 1276123579Sgibbsvoid ahc_recover_commands(struct ahc_softc *ahc); 127765942Sgibbs/*************************** Utility Functions ********************************/ 127874094Sgibbsstruct ahc_phase_table_entry* 127974094Sgibbs ahc_lookup_phase_entry(int phase); 128065942Sgibbsvoid ahc_compile_devinfo(struct ahc_devinfo *devinfo, 128165942Sgibbs u_int our_id, u_int target, 128265942Sgibbs u_int lun, char channel, 128365942Sgibbs role_t role); 128465942Sgibbs/************************** Transfer Negotiation ******************************/ 128565942Sgibbsstruct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 128665942Sgibbs u_int *ppr_options, u_int maxsync); 128765942Sgibbsu_int ahc_find_period(struct ahc_softc *ahc, 128865942Sgibbs u_int scsirate, u_int maxsync); 128965942Sgibbsvoid ahc_validate_offset(struct ahc_softc *ahc, 129068087Sgibbs struct ahc_initiator_tinfo *tinfo, 129165942Sgibbs struct ahc_syncrate *syncrate, 129268087Sgibbs u_int *offset, int wide, 129368087Sgibbs role_t role); 129465942Sgibbsvoid ahc_validate_width(struct ahc_softc *ahc, 129568087Sgibbs struct ahc_initiator_tinfo *tinfo, 129668087Sgibbs u_int *bus_width, 129768087Sgibbs role_t role); 1298107420Sscottl/* 1299107420Sscottl * Negotiation types. These are used to qualify if we should renegotiate 1300107420Sscottl * even if our goal and current transport parameters are identical. 1301107420Sscottl */ 1302107420Sscottltypedef enum { 1303107420Sscottl AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1304107420Sscottl AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1305107420Sscottl AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1306107420Sscottl} ahc_neg_type; 130774972Sgibbsint ahc_update_neg_request(struct ahc_softc*, 130874972Sgibbs struct ahc_devinfo*, 130974972Sgibbs struct ahc_tmode_tstate*, 131074972Sgibbs struct ahc_initiator_tinfo*, 1311107420Sscottl ahc_neg_type); 131265942Sgibbsvoid ahc_set_width(struct ahc_softc *ahc, 131365942Sgibbs struct ahc_devinfo *devinfo, 131465942Sgibbs u_int width, u_int type, int paused); 131565942Sgibbsvoid ahc_set_syncrate(struct ahc_softc *ahc, 131665942Sgibbs struct ahc_devinfo *devinfo, 131765942Sgibbs struct ahc_syncrate *syncrate, 131865942Sgibbs u_int period, u_int offset, 131965942Sgibbs u_int ppr_options, 132065942Sgibbs u_int type, int paused); 132176634Sgibbstypedef enum { 132276634Sgibbs AHC_QUEUE_NONE, 132376634Sgibbs AHC_QUEUE_BASIC, 132476634Sgibbs AHC_QUEUE_TAGGED 132576634Sgibbs} ahc_queue_alg; 132676634Sgibbs 132765942Sgibbsvoid ahc_set_tags(struct ahc_softc *ahc, 132876634Sgibbs struct ahc_devinfo *devinfo, 132976634Sgibbs ahc_queue_alg alg); 133063457Sgibbs 133165942Sgibbs/**************************** Target Mode *************************************/ 133265942Sgibbs#ifdef AHC_TARGET_MODE 133365942Sgibbsvoid ahc_send_lstate_events(struct ahc_softc *, 133474972Sgibbs struct ahc_tmode_lstate *); 133565942Sgibbsvoid ahc_handle_en_lun(struct ahc_softc *ahc, 133665942Sgibbs struct cam_sim *sim, union ccb *ccb); 133765942Sgibbscam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 133865942Sgibbs struct cam_sim *sim, union ccb *ccb, 133974972Sgibbs struct ahc_tmode_tstate **tstate, 134074972Sgibbs struct ahc_tmode_lstate **lstate, 134165942Sgibbs int notfound_failure); 134268087Sgibbs#ifndef AHC_TMODE_ENABLE 134368087Sgibbs#define AHC_TMODE_ENABLE 0 134465942Sgibbs#endif 134568087Sgibbs#endif 134665942Sgibbs/******************************* Debug ***************************************/ 134795378Sgibbs#ifdef AHC_DEBUG 1348102671Sgibbsextern uint32_t ahc_debug; 1349102671Sgibbs#define AHC_SHOW_MISC 0x0001 1350102671Sgibbs#define AHC_SHOW_SENSE 0x0002 1351102671Sgibbs#define AHC_DUMP_SEEPROM 0x0004 1352102671Sgibbs#define AHC_SHOW_TERMCTL 0x0008 1353102671Sgibbs#define AHC_SHOW_MEMORY 0x0010 1354102671Sgibbs#define AHC_SHOW_MESSAGES 0x0020 1355107420Sscottl#define AHC_SHOW_DV 0x0040 1356102671Sgibbs#define AHC_SHOW_SELTO 0x0080 1357102671Sgibbs#define AHC_SHOW_QFULL 0x0200 1358102671Sgibbs#define AHC_SHOW_QUEUE 0x0400 1359102671Sgibbs#define AHC_SHOW_TQIN 0x0800 1360109590Sgibbs#define AHC_SHOW_MASKED_ERRORS 0x1000 1361109590Sgibbs#define AHC_DEBUG_SEQUENCER 0x2000 136295378Sgibbs#endif 136365942Sgibbsvoid ahc_print_scb(struct scb *scb); 1364107420Sscottlvoid ahc_print_devinfo(struct ahc_softc *ahc, 1365107420Sscottl struct ahc_devinfo *dev); 136665942Sgibbsvoid ahc_dump_card_state(struct ahc_softc *ahc); 1367102671Sgibbsint ahc_print_register(ahc_reg_parse_entry_t *table, 1368102671Sgibbs u_int num_entries, 1369102671Sgibbs const char *name, 1370102671Sgibbs u_int address, 1371102671Sgibbs u_int value, 1372102671Sgibbs u_int *cur_column, 1373102671Sgibbs u_int wrap_point); 137495378Sgibbs/******************************* SEEPROM *************************************/ 137595378Sgibbsint ahc_acquire_seeprom(struct ahc_softc *ahc, 137695378Sgibbs struct seeprom_descriptor *sd); 137795378Sgibbsvoid ahc_release_seeprom(struct seeprom_descriptor *sd); 137865942Sgibbs#endif /* _AIC7XXX_H_ */ 1379