1139749Simp/*- 297883Sgibbs * Product specific probe and attach routines for: 397883Sgibbs * aic7901 and aic7902 SCSI controllers 497883Sgibbs * 597883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 6102686Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 797883Sgibbs * All rights reserved. 897883Sgibbs * 997883Sgibbs * Redistribution and use in source and binary forms, with or without 1097883Sgibbs * modification, are permitted provided that the following conditions 1197883Sgibbs * are met: 1297883Sgibbs * 1. Redistributions of source code must retain the above copyright 1397883Sgibbs * notice, this list of conditions, and the following disclaimer, 1497883Sgibbs * without modification. 1597883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1697883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1797883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1897883Sgibbs * including a substantially similar Disclaimer requirement for further 1997883Sgibbs * binary redistribution. 2097883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2197883Sgibbs * of any contributors may be used to endorse or promote products derived 2297883Sgibbs * from this software without specific prior written permission. 2397883Sgibbs * 2497883Sgibbs * Alternatively, this software may be distributed under the terms of the 2597883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2697883Sgibbs * Software Foundation. 2797883Sgibbs * 2897883Sgibbs * NO WARRANTY 2997883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3097883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3197883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3297883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3397883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3497883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3597883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3697883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3797883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3897883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3997883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 4097883Sgibbs * 41129134Sgibbs * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 4297883Sgibbs */ 4397883Sgibbs 4497883Sgibbs#ifdef __linux__ 4597883Sgibbs#include "aic79xx_osm.h" 4697883Sgibbs#include "aic79xx_inline.h" 4797883Sgibbs#else 48123579Sgibbs#include <sys/cdefs.h> 49123579Sgibbs__FBSDID("$FreeBSD$"); 5097883Sgibbs#include <dev/aic7xxx/aic79xx_osm.h> 5197883Sgibbs#include <dev/aic7xxx/aic79xx_inline.h> 5297883Sgibbs#endif 5397883Sgibbs 5497883Sgibbsstatic __inline uint64_t 5597883Sgibbsahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 5697883Sgibbs{ 5797883Sgibbs uint64_t id; 5897883Sgibbs 5997883Sgibbs id = subvendor 6097883Sgibbs | (subdevice << 16) 6197883Sgibbs | ((uint64_t)vendor << 32) 6297883Sgibbs | ((uint64_t)device << 48); 6397883Sgibbs 6497883Sgibbs return (id); 6597883Sgibbs} 6697883Sgibbs 6797883Sgibbs#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68125448Sgibbs#define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 6997883Sgibbs#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 7097883Sgibbs#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71125448Sgibbs#define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 7297883Sgibbs 7397883Sgibbs#define ID_AIC7901 0x800F9005FFFF9005ull 74115330Sgibbs#define ID_AHA_29320A 0x8000900500609005ull 75115330Sgibbs#define ID_AHA_29320ALP 0x8017900500449005ull 76115330Sgibbs 77102686Sgibbs#define ID_AIC7901A 0x801E9005FFFF9005ull 78107440Sscottl#define ID_AHA_29320LP 0x8014900500449005ull 7997883Sgibbs 8097883Sgibbs#define ID_AIC7902 0x801F9005FFFF9005ull 81107440Sscottl#define ID_AIC7902_B 0x801D9005FFFF9005ull 8297883Sgibbs#define ID_AHA_39320 0x8010900500409005ull 83123579Sgibbs#define ID_AHA_29320 0x8012900500429005ull 84123579Sgibbs#define ID_AHA_29320B 0x8013900500439005ull 85115330Sgibbs#define ID_AHA_39320_B 0x8015900500409005ull 86129134Sgibbs#define ID_AHA_39320_B_DELL 0x8015900501681028ull 87111653Sgibbs#define ID_AHA_39320A 0x8016900500409005ull 8897883Sgibbs#define ID_AHA_39320D 0x8011900500419005ull 89107440Sscottl#define ID_AHA_39320D_B 0x801C900500419005ull 90107440Sscottl#define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91107440Sscottl#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92198684Sbrueffer#define ID_AHA_39320LPE 0x8017900500459005ull 9397883Sgibbs#define ID_AIC7902_PCI_REV_A4 0x3 94102686Sgibbs#define ID_AIC7902_PCI_REV_B0 0x10 95107440Sscottl#define SUBID_HP 0x0E11 9697883Sgibbs 97125448Sgibbs#define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 98125448Sgibbs 9997883Sgibbs#define DEVID_9005_TYPE(id) ((id) & 0xF) 10097883Sgibbs#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 10197883Sgibbs#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 10297883Sgibbs#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 10397883Sgibbs 10497883Sgibbs#define DEVID_9005_MFUNC(id) ((id) & 0x10) 10597883Sgibbs 10697883Sgibbs#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 10797883Sgibbs 10897883Sgibbs#define SUBID_9005_TYPE(id) ((id) & 0xF) 10997883Sgibbs#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 11097883Sgibbs#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 11197883Sgibbs 11297883Sgibbs#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 11397883Sgibbs 11497883Sgibbs#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 11597883Sgibbs 11697883Sgibbs#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 11797883Sgibbs#define SUBID_9005_SEEPTYPE_NONE 0x0 11897883Sgibbs#define SUBID_9005_SEEPTYPE_4K 0x1 11997883Sgibbs 120115330Sgibbsstatic ahd_device_setup_t ahd_aic7901_setup; 121107440Sscottlstatic ahd_device_setup_t ahd_aic7901A_setup; 12297883Sgibbsstatic ahd_device_setup_t ahd_aic7902_setup; 123116933Sgibbsstatic ahd_device_setup_t ahd_aic790X_setup; 12497883Sgibbs 12597883Sgibbsstruct ahd_pci_identity ahd_pci_ident_table [] = 12697883Sgibbs{ 127115330Sgibbs /* aic7901 based controllers */ 128115330Sgibbs { 129115330Sgibbs ID_AHA_29320A, 130115330Sgibbs ID_ALL_MASK, 131115330Sgibbs "Adaptec 29320A Ultra320 SCSI adapter", 132115330Sgibbs ahd_aic7901_setup 133115330Sgibbs }, 134115330Sgibbs { 135115330Sgibbs ID_AHA_29320ALP, 136115330Sgibbs ID_ALL_MASK, 137115330Sgibbs "Adaptec 29320ALP Ultra320 SCSI adapter", 138115330Sgibbs ahd_aic7901_setup 139115330Sgibbs }, 140107440Sscottl /* aic7901A based controllers */ 14197883Sgibbs { 142123579Sgibbs ID_AHA_29320LP, 143123579Sgibbs ID_ALL_MASK, 144123579Sgibbs "Adaptec 29320LP Ultra320 SCSI adapter", 145123579Sgibbs ahd_aic7901A_setup 146123579Sgibbs }, 147123579Sgibbs /* aic7902 based controllers */ 148123579Sgibbs { 149115330Sgibbs ID_AHA_29320, 150107440Sscottl ID_ALL_MASK, 151115330Sgibbs "Adaptec 29320 Ultra320 SCSI adapter", 152123579Sgibbs ahd_aic7902_setup 153107440Sscottl }, 154107440Sscottl { 155115330Sgibbs ID_AHA_29320B, 15697883Sgibbs ID_ALL_MASK, 157115330Sgibbs "Adaptec 29320B Ultra320 SCSI adapter", 158123579Sgibbs ahd_aic7902_setup 15997883Sgibbs }, 160115330Sgibbs { 16197883Sgibbs ID_AHA_39320, 16297883Sgibbs ID_ALL_MASK, 16397883Sgibbs "Adaptec 39320 Ultra320 SCSI adapter", 16497883Sgibbs ahd_aic7902_setup 16597883Sgibbs }, 16697883Sgibbs { 167115330Sgibbs ID_AHA_39320_B, 168115330Sgibbs ID_ALL_MASK, 169115330Sgibbs "Adaptec 39320 Ultra320 SCSI adapter", 170115330Sgibbs ahd_aic7902_setup 171115330Sgibbs }, 172115330Sgibbs { 173129134Sgibbs ID_AHA_39320_B_DELL, 174129134Sgibbs ID_ALL_MASK, 175129134Sgibbs "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 176129134Sgibbs ahd_aic7902_setup 177129134Sgibbs }, 178129134Sgibbs { 179111653Sgibbs ID_AHA_39320A, 180111653Sgibbs ID_ALL_MASK, 181111653Sgibbs "Adaptec 39320A Ultra320 SCSI adapter", 182111653Sgibbs ahd_aic7902_setup 183111653Sgibbs }, 184111653Sgibbs { 18597883Sgibbs ID_AHA_39320D, 18697883Sgibbs ID_ALL_MASK, 18797883Sgibbs "Adaptec 39320D Ultra320 SCSI adapter", 18897883Sgibbs ahd_aic7902_setup 18997883Sgibbs }, 19097883Sgibbs { 191107440Sscottl ID_AHA_39320D_HP, 19297883Sgibbs ID_ALL_MASK, 193107440Sscottl "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 19497883Sgibbs ahd_aic7902_setup 19597883Sgibbs }, 196102686Sgibbs { 197107440Sscottl ID_AHA_39320D_B, 198102686Sgibbs ID_ALL_MASK, 199107440Sscottl "Adaptec 39320D Ultra320 SCSI adapter", 200102686Sgibbs ahd_aic7902_setup 201102686Sgibbs }, 202102686Sgibbs { 203107440Sscottl ID_AHA_39320D_B_HP, 204102686Sgibbs ID_ALL_MASK, 205107440Sscottl "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 206102686Sgibbs ahd_aic7902_setup 207102686Sgibbs }, 208198684Sbrueffer { 209198684Sbrueffer ID_AHA_39320LPE, 210198684Sbrueffer ID_ALL_MASK, 211198684Sbrueffer "Adaptec 39320LPE Ultra320 SCSI adapter", 212198684Sbrueffer ahd_aic7902_setup 213198684Sbrueffer }, 21497883Sgibbs /* Generic chip probes for devices we don't know 'exactly' */ 21597883Sgibbs { 216125448Sgibbs ID_AIC7901 & ID_9005_GENERIC_MASK, 217129134Sgibbs ID_9005_GENERIC_MASK, 218115330Sgibbs "Adaptec AIC7901 Ultra320 SCSI adapter", 219115330Sgibbs ahd_aic7901_setup 220115330Sgibbs }, 221115330Sgibbs { 222107623Sscottl ID_AIC7901A & ID_DEV_VENDOR_MASK, 223107623Sscottl ID_DEV_VENDOR_MASK, 224107440Sscottl "Adaptec AIC7901A Ultra320 SCSI adapter", 225107440Sscottl ahd_aic7901A_setup 22697883Sgibbs }, 22797883Sgibbs { 22897883Sgibbs ID_AIC7902 & ID_9005_GENERIC_MASK, 22997883Sgibbs ID_9005_GENERIC_MASK, 230107440Sscottl "Adaptec AIC7902 Ultra320 SCSI adapter", 23197883Sgibbs ahd_aic7902_setup 23297883Sgibbs } 23397883Sgibbs}; 23497883Sgibbs 23597883Sgibbsconst u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 23697883Sgibbs 23797883Sgibbs#define DEVCONFIG 0x40 23897883Sgibbs#define PCIXINITPAT 0x0000E000ul 23997883Sgibbs#define PCIXINIT_PCI33_66 0x0000E000ul 24097883Sgibbs#define PCIXINIT_PCIX50_66 0x0000C000ul 24197883Sgibbs#define PCIXINIT_PCIX66_100 0x0000A000ul 24297883Sgibbs#define PCIXINIT_PCIX100_133 0x00008000ul 24397883Sgibbs#define PCI_BUS_MODES_INDEX(devconfig) \ 24497883Sgibbs (((devconfig) & PCIXINITPAT) >> 13) 24597883Sgibbsstatic const char *pci_bus_modes[] = 24697883Sgibbs{ 24797883Sgibbs "PCI bus mode unknown", 24897883Sgibbs "PCI bus mode unknown", 24997883Sgibbs "PCI bus mode unknown", 25097883Sgibbs "PCI bus mode unknown", 251202161Sgavin "PCI-X 101-133MHz", 252202161Sgavin "PCI-X 67-100MHz", 253202161Sgavin "PCI-X 50-66MHz", 254202161Sgavin "PCI 33 or 66MHz" 25597883Sgibbs}; 25697883Sgibbs 25797883Sgibbs#define TESTMODE 0x00000800ul 25897883Sgibbs#define IRDY_RST 0x00000200ul 25997883Sgibbs#define FRAME_RST 0x00000100ul 26097883Sgibbs#define PCI64BIT 0x00000080ul 26197883Sgibbs#define MRDCEN 0x00000040ul 26297883Sgibbs#define ENDIANSEL 0x00000020ul 26397883Sgibbs#define MIXQWENDIANEN 0x00000008ul 26497883Sgibbs#define DACEN 0x00000004ul 26597883Sgibbs#define STPWLEVEL 0x00000002ul 26697883Sgibbs#define QWENDIANSEL 0x00000001ul 26797883Sgibbs 26897883Sgibbs#define DEVCONFIG1 0x44 26997883Sgibbs#define PREQDIS 0x01 27097883Sgibbs 27197883Sgibbs#define CSIZE_LATTIME 0x0c 27297883Sgibbs#define CACHESIZE 0x000000fful 27397883Sgibbs#define LATTIME 0x0000ff00ul 27497883Sgibbs 27597883Sgibbsstatic int ahd_check_extport(struct ahd_softc *ahd); 27697883Sgibbsstatic void ahd_configure_termination(struct ahd_softc *ahd, 27797883Sgibbs u_int adapter_control); 27897883Sgibbsstatic void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 27997883Sgibbs 28097883Sgibbsstruct ahd_pci_identity * 281123579Sgibbsahd_find_pci_device(aic_dev_softc_t pci) 28297883Sgibbs{ 28397883Sgibbs uint64_t full_id; 28497883Sgibbs uint16_t device; 28597883Sgibbs uint16_t vendor; 28697883Sgibbs uint16_t subdevice; 28797883Sgibbs uint16_t subvendor; 28897883Sgibbs struct ahd_pci_identity *entry; 28997883Sgibbs u_int i; 29097883Sgibbs 291123579Sgibbs vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 292123579Sgibbs device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 293123579Sgibbs subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 294123579Sgibbs subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 29597883Sgibbs full_id = ahd_compose_id(device, 29697883Sgibbs vendor, 29797883Sgibbs subdevice, 29897883Sgibbs subvendor); 29997883Sgibbs 300125448Sgibbs /* 301125448Sgibbs * If we are configured to attach to HostRAID 302125448Sgibbs * controllers, mask out the IROC/HostRAID bit 303125448Sgibbs * in the 304125448Sgibbs */ 305125448Sgibbs if (ahd_attach_to_HostRAID_controllers) 306125448Sgibbs full_id &= ID_ALL_IROC_MASK; 307125448Sgibbs 30897883Sgibbs for (i = 0; i < ahd_num_pci_devs; i++) { 30997883Sgibbs entry = &ahd_pci_ident_table[i]; 31097883Sgibbs if (entry->full_id == (full_id & entry->id_mask)) { 31197883Sgibbs /* Honor exclusion entries. */ 31297883Sgibbs if (entry->name == NULL) 31397883Sgibbs return (NULL); 31497883Sgibbs return (entry); 31597883Sgibbs } 31697883Sgibbs } 31797883Sgibbs return (NULL); 31897883Sgibbs} 31997883Sgibbs 32097883Sgibbsint 32197883Sgibbsahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 32297883Sgibbs{ 32397883Sgibbs struct scb_data *shared_scb_data; 32497883Sgibbs u_int command; 32597883Sgibbs uint32_t devconfig; 326125448Sgibbs uint16_t device; 32797883Sgibbs uint16_t subvendor; 32897883Sgibbs int error; 32997883Sgibbs 33097883Sgibbs shared_scb_data = NULL; 331107440Sscottl ahd->description = entry->name; 332107440Sscottl /* 333125448Sgibbs * Record if this is a HostRAID board. 334125448Sgibbs */ 335125448Sgibbs device = aic_pci_read_config(ahd->dev_softc, 336125448Sgibbs PCIR_DEVICE, /*bytes*/2); 337125448Sgibbs if (DEVID_9005_HOSTRAID(device)) 338125448Sgibbs ahd->flags |= AHD_HOSTRAID_BOARD; 339125448Sgibbs 340125448Sgibbs /* 341107440Sscottl * Record if this is an HP board. 342107440Sscottl */ 343123579Sgibbs subvendor = aic_pci_read_config(ahd->dev_softc, 344107440Sscottl PCIR_SUBVEND_0, /*bytes*/2); 345107440Sscottl if (subvendor == SUBID_HP) 346107440Sscottl ahd->flags |= AHD_HP_BOARD; 347107440Sscottl 34897883Sgibbs error = entry->setup(ahd); 34997883Sgibbs if (error != 0) 35097883Sgibbs return (error); 351166109Sjhb 352166109Sjhb /* 353166109Sjhb * Find the PCI-X cap pointer. If we don't find it, 354166109Sjhb * pcix_ptr will be 0. 355166109Sjhb */ 356219902Sjhb pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 357123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 35897883Sgibbs if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 35997883Sgibbs ahd->chip |= AHD_PCI; 36097883Sgibbs /* Disable PCIX workarounds when running in PCI mode. */ 36197883Sgibbs ahd->bugs &= ~AHD_PCIX_BUG_MASK; 36297883Sgibbs } else { 36397883Sgibbs ahd->chip |= AHD_PCIX; 364166109Sjhb if (ahd->pcix_ptr == 0) 365166109Sjhb return (ENXIO); 36697883Sgibbs } 36797883Sgibbs ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 36897883Sgibbs 369123579Sgibbs aic_power_state_change(ahd, AIC_POWER_STATE_D0); 37097883Sgibbs 37197883Sgibbs error = ahd_pci_map_registers(ahd); 37297883Sgibbs if (error != 0) 37397883Sgibbs return (error); 37497883Sgibbs 37597883Sgibbs /* 37697883Sgibbs * If we need to support high memory, enable dual 37797883Sgibbs * address cycles. This bit must be set to enable 37897883Sgibbs * high address bit generation even if we are on a 37997883Sgibbs * 64bit bus (PCI64BIT set in devconfig). 38097883Sgibbs */ 38197883Sgibbs if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 38297883Sgibbs uint32_t devconfig; 38397883Sgibbs 38497883Sgibbs if (bootverbose) 38597883Sgibbs printf("%s: Enabling 39Bit Addressing\n", 38697883Sgibbs ahd_name(ahd)); 387123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, 38897883Sgibbs DEVCONFIG, /*bytes*/4); 38997883Sgibbs devconfig |= DACEN; 390123579Sgibbs aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 39197883Sgibbs devconfig, /*bytes*/4); 39297883Sgibbs } 39397883Sgibbs 39497883Sgibbs /* Ensure busmastering is enabled */ 395123579Sgibbs command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 39697883Sgibbs command |= PCIM_CMD_BUSMASTEREN; 397123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 39897883Sgibbs 39997883Sgibbs error = ahd_softc_init(ahd); 40097883Sgibbs if (error != 0) 40197883Sgibbs return (error); 40297883Sgibbs 40397883Sgibbs ahd->bus_intr = ahd_pci_intr; 40497883Sgibbs 405115917Sgibbs error = ahd_reset(ahd, /*reinit*/FALSE); 40697883Sgibbs if (error != 0) 40797883Sgibbs return (ENXIO); 40897883Sgibbs 40997883Sgibbs ahd->pci_cachesize = 410123579Sgibbs aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 41197883Sgibbs /*bytes*/1) & CACHESIZE; 41297883Sgibbs ahd->pci_cachesize *= 4; 41397883Sgibbs 41497883Sgibbs ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 41597883Sgibbs /* See if we have a SEEPROM and perform auto-term */ 41697883Sgibbs error = ahd_check_extport(ahd); 41797883Sgibbs if (error != 0) 41897883Sgibbs return (error); 41997883Sgibbs 42097883Sgibbs /* Core initialization */ 42197883Sgibbs error = ahd_init(ahd); 42297883Sgibbs if (error != 0) 42397883Sgibbs return (error); 42497883Sgibbs 42597883Sgibbs /* 42697883Sgibbs * Allow interrupts now that we are completely setup. 42797883Sgibbs */ 42897883Sgibbs error = ahd_pci_map_int(ahd); 42997883Sgibbs if (error != 0) 43097883Sgibbs return (error); 43197883Sgibbs 432168807Sscottl ahd_lock(ahd); 43397883Sgibbs /* 43497883Sgibbs * Link this softc in with all other ahd instances. 43597883Sgibbs */ 43697883Sgibbs ahd_softc_insert(ahd); 437168807Sscottl ahd_unlock(ahd); 43897883Sgibbs return (0); 43997883Sgibbs} 44097883Sgibbs 44197883Sgibbs/* 442107440Sscottl * Perform some simple tests that should catch situations where 443107440Sscottl * our registers are invalidly mapped. 444107440Sscottl */ 445107440Sscottlint 446107440Sscottlahd_pci_test_register_access(struct ahd_softc *ahd) 447107440Sscottl{ 448115919Sgibbs uint32_t cmd; 449115919Sgibbs u_int targpcistat; 450115919Sgibbs u_int pci_status1; 451115919Sgibbs int error; 452115919Sgibbs uint8_t hcntrl; 453107440Sscottl 454107623Sscottl error = EIO; 455107623Sscottl 456109588Sgibbs /* 457109588Sgibbs * Enable PCI error interrupt status, but suppress NMIs 458109588Sgibbs * generated by SERR raised due to target aborts. 459109588Sgibbs */ 460123579Sgibbs cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 461123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 462109588Sgibbs cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 463107623Sscottl 464107440Sscottl /* 465107440Sscottl * First a simple test to see if any 466107440Sscottl * registers can be read. Reading 467107440Sscottl * HCNTRL has no side effects and has 468107440Sscottl * at least one bit that is guaranteed to 469107440Sscottl * be zero so it is a good register to 470107440Sscottl * use for this test. 471107440Sscottl */ 472109588Sgibbs hcntrl = ahd_inb(ahd, HCNTRL); 473109588Sgibbs if (hcntrl == 0xFF) 474107623Sscottl goto fail; 475107440Sscottl 476107440Sscottl /* 477107440Sscottl * Next create a situation where write combining 478107440Sscottl * or read prefetching could be initiated by the 479107440Sscottl * CPU or host bridge. Our device does not support 480107440Sscottl * either, so look for data corruption and/or flaged 481120445Sscottl * PCI errors. First pause without causing another 482120445Sscottl * chip reset. 483107440Sscottl */ 484120445Sscottl hcntrl &= ~CHIPRST; 485109588Sgibbs ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 486109588Sgibbs while (ahd_is_paused(ahd) == 0) 487109588Sgibbs ; 488115919Sgibbs 489115919Sgibbs /* Clear any PCI errors that occurred before our driver attached. */ 490115919Sgibbs ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 491115919Sgibbs targpcistat = ahd_inb(ahd, TARGPCISTAT); 492115919Sgibbs ahd_outb(ahd, TARGPCISTAT, targpcistat); 493123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 494115919Sgibbs PCIR_STATUS + 1, /*bytes*/1); 495123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 496115919Sgibbs pci_status1, /*bytes*/1); 497115919Sgibbs ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 498115919Sgibbs ahd_outb(ahd, CLRINT, CLRPCIINT); 499115919Sgibbs 500109588Sgibbs ahd_outb(ahd, SEQCTL0, PERRORDIS); 501107623Sscottl ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 502107623Sscottl if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 503107623Sscottl goto fail; 504107440Sscottl 505107623Sscottl if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 506107623Sscottl u_int targpcistat; 507107440Sscottl 508107623Sscottl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 509107623Sscottl targpcistat = ahd_inb(ahd, TARGPCISTAT); 510107623Sscottl if ((targpcistat & STA) != 0) 511107623Sscottl goto fail; 512107623Sscottl } 513107623Sscottl 514107623Sscottl error = 0; 515107623Sscottl 516107623Sscottlfail: 517107440Sscottl if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 518107440Sscottl 519107440Sscottl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 520107440Sscottl targpcistat = ahd_inb(ahd, TARGPCISTAT); 521107440Sscottl 522107440Sscottl /* Silently clear any latched errors. */ 523107440Sscottl ahd_outb(ahd, TARGPCISTAT, targpcistat); 524123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 525107440Sscottl PCIR_STATUS + 1, /*bytes*/1); 526123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 527107440Sscottl pci_status1, /*bytes*/1); 528107623Sscottl ahd_outb(ahd, CLRINT, CLRPCIINT); 529107440Sscottl } 530109588Sgibbs ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 531123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 532107623Sscottl return (error); 533107440Sscottl} 534107440Sscottl 535107440Sscottl/* 53697883Sgibbs * Check the external port logic for a serial eeprom 53797883Sgibbs * and termination/cable detection contrls. 53897883Sgibbs */ 53997883Sgibbsstatic int 54097883Sgibbsahd_check_extport(struct ahd_softc *ahd) 54197883Sgibbs{ 542114623Sgibbs struct vpd_config vpd; 54397883Sgibbs struct seeprom_config *sc; 54497883Sgibbs u_int adapter_control; 54597883Sgibbs int have_seeprom; 54697883Sgibbs int error; 54797883Sgibbs 54897883Sgibbs sc = ahd->seep_config; 54997883Sgibbs have_seeprom = ahd_acquire_seeprom(ahd); 55097883Sgibbs if (have_seeprom) { 55197883Sgibbs u_int start_addr; 55297883Sgibbs 553114623Sgibbs /* 554114623Sgibbs * Fetch VPD for this function and parse it. 555114623Sgibbs */ 55697883Sgibbs if (bootverbose) 557114623Sgibbs printf("%s: Reading VPD from SEEPROM...", 558114623Sgibbs ahd_name(ahd)); 559114623Sgibbs 560114623Sgibbs /* Address is always in units of 16bit words */ 561114623Sgibbs start_addr = ((2 * sizeof(*sc)) 562114623Sgibbs + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 563114623Sgibbs 564114623Sgibbs error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 565114623Sgibbs start_addr, sizeof(vpd)/2, 566114623Sgibbs /*bytestream*/TRUE); 567114623Sgibbs if (error == 0) 568114623Sgibbs error = ahd_parse_vpddata(ahd, &vpd); 569114623Sgibbs if (bootverbose) 570114623Sgibbs printf("%s: VPD parsing %s\n", 571114623Sgibbs ahd_name(ahd), 572114623Sgibbs error == 0 ? "successful" : "failed"); 573114623Sgibbs 574114623Sgibbs if (bootverbose) 57597883Sgibbs printf("%s: Reading SEEPROM...", ahd_name(ahd)); 57697883Sgibbs 57797883Sgibbs /* Address is always in units of 16bit words */ 57897883Sgibbs start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 57997883Sgibbs 58097883Sgibbs error = ahd_read_seeprom(ahd, (uint16_t *)sc, 581114623Sgibbs start_addr, sizeof(*sc)/2, 582114623Sgibbs /*bytestream*/FALSE); 58397883Sgibbs 58497883Sgibbs if (error != 0) { 58597883Sgibbs printf("Unable to read SEEPROM\n"); 58697883Sgibbs have_seeprom = 0; 58797883Sgibbs } else { 58897883Sgibbs have_seeprom = ahd_verify_cksum(sc); 58997883Sgibbs 59097883Sgibbs if (bootverbose) { 59197883Sgibbs if (have_seeprom == 0) 59297883Sgibbs printf ("checksum error\n"); 59397883Sgibbs else 59497883Sgibbs printf ("done.\n"); 59597883Sgibbs } 59697883Sgibbs } 59797883Sgibbs ahd_release_seeprom(ahd); 59897883Sgibbs } 59997883Sgibbs 60097883Sgibbs if (!have_seeprom) { 60197883Sgibbs u_int nvram_scb; 60297883Sgibbs 60397883Sgibbs /* 60497883Sgibbs * Pull scratch ram settings and treat them as 60597883Sgibbs * if they are the contents of an seeprom if 60697883Sgibbs * the 'ADPT', 'BIOS', or 'ASPI' signature is found 60797883Sgibbs * in SCB 0xFF. We manually compose the data as 16bit 60897883Sgibbs * values to avoid endian issues. 60997883Sgibbs */ 61097883Sgibbs ahd_set_scbptr(ahd, 0xFF); 61197883Sgibbs nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 61297883Sgibbs if (nvram_scb != 0xFF 61397883Sgibbs && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 61497883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 61597883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 61697883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 61797883Sgibbs || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 61897883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 61997883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 62097883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 62197883Sgibbs || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 62297883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 62397883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 62497883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 62597883Sgibbs uint16_t *sc_data; 62697883Sgibbs int i; 62797883Sgibbs 62897883Sgibbs ahd_set_scbptr(ahd, nvram_scb); 62997883Sgibbs sc_data = (uint16_t *)sc; 63097883Sgibbs for (i = 0; i < 64; i += 2) 63197883Sgibbs *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 63297883Sgibbs have_seeprom = ahd_verify_cksum(sc); 63397883Sgibbs if (have_seeprom) 63497883Sgibbs ahd->flags |= AHD_SCB_CONFIG_USED; 63597883Sgibbs } 63697883Sgibbs } 63797883Sgibbs 638153072Sru#ifdef AHD_DEBUG 63997883Sgibbs if (have_seeprom != 0 64097883Sgibbs && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 641114623Sgibbs uint16_t *sc_data; 642114623Sgibbs int i; 64397883Sgibbs 64497883Sgibbs printf("%s: Seeprom Contents:", ahd_name(ahd)); 645114623Sgibbs sc_data = (uint16_t *)sc; 64697883Sgibbs for (i = 0; i < (sizeof(*sc)); i += 2) 647114623Sgibbs printf("\n\t0x%.4x", sc_data[i]); 64897883Sgibbs printf("\n"); 64997883Sgibbs } 65097883Sgibbs#endif 65197883Sgibbs 65297883Sgibbs if (!have_seeprom) { 65397883Sgibbs if (bootverbose) 65497883Sgibbs printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 65597883Sgibbs ahd->flags |= AHD_USEDEFAULTS; 65697883Sgibbs error = ahd_default_config(ahd); 65797883Sgibbs adapter_control = CFAUTOTERM|CFSEAUTOTERM; 65897883Sgibbs free(ahd->seep_config, M_DEVBUF); 65997883Sgibbs ahd->seep_config = NULL; 66097883Sgibbs } else { 66197883Sgibbs error = ahd_parse_cfgdata(ahd, sc); 66297883Sgibbs adapter_control = sc->adapter_control; 66397883Sgibbs } 66497883Sgibbs if (error != 0) 66597883Sgibbs return (error); 66697883Sgibbs 66797883Sgibbs ahd_configure_termination(ahd, adapter_control); 66897883Sgibbs 66997883Sgibbs return (0); 67097883Sgibbs} 67197883Sgibbs 67297883Sgibbsstatic void 67397883Sgibbsahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 67497883Sgibbs{ 67597883Sgibbs int error; 67697883Sgibbs u_int sxfrctl1; 67797883Sgibbs uint8_t termctl; 67897883Sgibbs uint32_t devconfig; 67997883Sgibbs 680123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 68197883Sgibbs devconfig &= ~STPWLEVEL; 682102686Sgibbs if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 68397883Sgibbs devconfig |= STPWLEVEL; 684102686Sgibbs if (bootverbose) 685102686Sgibbs printf("%s: STPWLEVEL is %s\n", 686102686Sgibbs ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 687123579Sgibbs aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 68897883Sgibbs 68997883Sgibbs /* Make sure current sensing is off. */ 69097883Sgibbs if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 69197883Sgibbs (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 69297883Sgibbs } 69397883Sgibbs 69497883Sgibbs /* 69597883Sgibbs * Read to sense. Write to set. 69697883Sgibbs */ 69797883Sgibbs error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 69897883Sgibbs if ((adapter_control & CFAUTOTERM) == 0) { 69997883Sgibbs if (bootverbose) 70097883Sgibbs printf("%s: Manual Primary Termination\n", 70197883Sgibbs ahd_name(ahd)); 70297883Sgibbs termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 70397883Sgibbs if ((adapter_control & CFSTERM) != 0) 70497883Sgibbs termctl |= FLX_TERMCTL_ENPRILOW; 70597883Sgibbs if ((adapter_control & CFWSTERM) != 0) 70697883Sgibbs termctl |= FLX_TERMCTL_ENPRIHIGH; 70797883Sgibbs } else if (error != 0) { 70897883Sgibbs printf("%s: Primary Auto-Term Sensing failed! " 70997883Sgibbs "Using Defaults.\n", ahd_name(ahd)); 71097883Sgibbs termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 71197883Sgibbs } 71297883Sgibbs 71397883Sgibbs if ((adapter_control & CFSEAUTOTERM) == 0) { 71497883Sgibbs if (bootverbose) 71597883Sgibbs printf("%s: Manual Secondary Termination\n", 71697883Sgibbs ahd_name(ahd)); 71797883Sgibbs termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 71897883Sgibbs if ((adapter_control & CFSELOWTERM) != 0) 71997883Sgibbs termctl |= FLX_TERMCTL_ENSECLOW; 72097883Sgibbs if ((adapter_control & CFSEHIGHTERM) != 0) 72197883Sgibbs termctl |= FLX_TERMCTL_ENSECHIGH; 72297883Sgibbs } else if (error != 0) { 72397883Sgibbs printf("%s: Secondary Auto-Term Sensing failed! " 72497883Sgibbs "Using Defaults.\n", ahd_name(ahd)); 72597883Sgibbs termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 72697883Sgibbs } 72797883Sgibbs 72897883Sgibbs /* 72997883Sgibbs * Now set the termination based on what we found. 73097883Sgibbs */ 73197883Sgibbs sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 732123579Sgibbs ahd->flags &= ~AHD_TERM_ENB_A; 73397883Sgibbs if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 73497883Sgibbs ahd->flags |= AHD_TERM_ENB_A; 73597883Sgibbs sxfrctl1 |= STPWEN; 73697883Sgibbs } 73797883Sgibbs /* Must set the latch once in order to be effective. */ 73897883Sgibbs ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 73997883Sgibbs ahd_outb(ahd, SXFRCTL1, sxfrctl1); 74097883Sgibbs 74197883Sgibbs error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 74297883Sgibbs if (error != 0) { 74397883Sgibbs printf("%s: Unable to set termination settings!\n", 74497883Sgibbs ahd_name(ahd)); 74597883Sgibbs } else if (bootverbose) { 74697883Sgibbs printf("%s: Primary High byte termination %sabled\n", 74797883Sgibbs ahd_name(ahd), 74897883Sgibbs (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 74997883Sgibbs 75097883Sgibbs printf("%s: Primary Low byte termination %sabled\n", 75197883Sgibbs ahd_name(ahd), 75297883Sgibbs (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 75397883Sgibbs 75497883Sgibbs printf("%s: Secondary High byte termination %sabled\n", 75597883Sgibbs ahd_name(ahd), 75697883Sgibbs (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 75797883Sgibbs 75897883Sgibbs printf("%s: Secondary Low byte termination %sabled\n", 75997883Sgibbs ahd_name(ahd), 76097883Sgibbs (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 76197883Sgibbs } 76297883Sgibbs return; 76397883Sgibbs} 76497883Sgibbs 76597883Sgibbs#define DPE 0x80 76697883Sgibbs#define SSE 0x40 76797883Sgibbs#define RMA 0x20 76897883Sgibbs#define RTA 0x10 76997883Sgibbs#define STA 0x08 77097883Sgibbs#define DPR 0x01 77197883Sgibbs 77297883Sgibbsstatic const char *split_status_source[] = 77397883Sgibbs{ 77497883Sgibbs "DFF0", 77597883Sgibbs "DFF1", 77697883Sgibbs "OVLY", 77797883Sgibbs "CMC", 77897883Sgibbs}; 77997883Sgibbs 78097883Sgibbsstatic const char *pci_status_source[] = 78197883Sgibbs{ 78297883Sgibbs "DFF0", 78397883Sgibbs "DFF1", 78497883Sgibbs "SG", 78597883Sgibbs "CMC", 78697883Sgibbs "OVLY", 78797883Sgibbs "NONE", 78897883Sgibbs "MSI", 78997883Sgibbs "TARG" 79097883Sgibbs}; 79197883Sgibbs 79297883Sgibbsstatic const char *split_status_strings[] = 79397883Sgibbs{ 794111653Sgibbs "%s: Received split response in %s.\n", 79597883Sgibbs "%s: Received split completion error message in %s\n", 79697883Sgibbs "%s: Receive overrun in %s\n", 79797883Sgibbs "%s: Count not complete in %s\n", 79897883Sgibbs "%s: Split completion data bucket in %s\n", 79997883Sgibbs "%s: Split completion address error in %s\n", 80097883Sgibbs "%s: Split completion byte count error in %s\n", 801111653Sgibbs "%s: Signaled Target-abort to early terminate a split in %s\n" 80297883Sgibbs}; 80397883Sgibbs 80497883Sgibbsstatic const char *pci_status_strings[] = 80597883Sgibbs{ 80697883Sgibbs "%s: Data Parity Error has been reported via PERR# in %s\n", 80797883Sgibbs "%s: Target initial wait state error in %s\n", 80897883Sgibbs "%s: Split completion read data parity error in %s\n", 80997883Sgibbs "%s: Split completion address attribute parity error in %s\n", 81097883Sgibbs "%s: Received a Target Abort in %s\n", 81197883Sgibbs "%s: Received a Master Abort in %s\n", 81297883Sgibbs "%s: Signal System Error Detected in %s\n", 81397883Sgibbs "%s: Address or Write Phase Parity Error Detected in %s.\n" 81497883Sgibbs}; 81597883Sgibbs 81697883Sgibbsvoid 81797883Sgibbsahd_pci_intr(struct ahd_softc *ahd) 81897883Sgibbs{ 81997883Sgibbs uint8_t pci_status[8]; 82097883Sgibbs ahd_mode_state saved_modes; 82197883Sgibbs u_int pci_status1; 82297883Sgibbs u_int intstat; 82397883Sgibbs u_int i; 82497883Sgibbs u_int reg; 82597883Sgibbs 82697883Sgibbs intstat = ahd_inb(ahd, INTSTAT); 82797883Sgibbs 82897883Sgibbs if ((intstat & SPLTINT) != 0) 82997883Sgibbs ahd_pci_split_intr(ahd, intstat); 83097883Sgibbs 83197883Sgibbs if ((intstat & PCIINT) == 0) 83297883Sgibbs return; 83397883Sgibbs 83497883Sgibbs printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 83597883Sgibbs saved_modes = ahd_save_modes(ahd); 83697883Sgibbs ahd_dump_card_state(ahd); 83797883Sgibbs ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 83897883Sgibbs for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 83997883Sgibbs 84097883Sgibbs if (i == 5) 84197883Sgibbs continue; 84297883Sgibbs pci_status[i] = ahd_inb(ahd, reg); 843111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 84497883Sgibbs ahd_outb(ahd, reg, pci_status[i]); 84597883Sgibbs } 84697883Sgibbs 84797883Sgibbs for (i = 0; i < 8; i++) { 84897883Sgibbs u_int bit; 84997883Sgibbs 85097883Sgibbs if (i == 5) 85197883Sgibbs continue; 85297883Sgibbs 85397883Sgibbs for (bit = 0; bit < 8; bit++) { 85497883Sgibbs 85597883Sgibbs if ((pci_status[i] & (0x1 << bit)) != 0) { 85697883Sgibbs static const char *s; 85797883Sgibbs 85897883Sgibbs s = pci_status_strings[bit]; 85997883Sgibbs if (i == 7/*TARG*/ && bit == 3) 860107623Sscottl s = "%s: Signaled Target Abort\n"; 86197883Sgibbs printf(s, ahd_name(ahd), pci_status_source[i]); 86297883Sgibbs } 86397883Sgibbs } 86497883Sgibbs } 865123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 86697883Sgibbs PCIR_STATUS + 1, /*bytes*/1); 867123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 86897883Sgibbs pci_status1, /*bytes*/1); 86997883Sgibbs ahd_restore_modes(ahd, saved_modes); 870107623Sscottl ahd_outb(ahd, CLRINT, CLRPCIINT); 87197883Sgibbs ahd_unpause(ahd); 87297883Sgibbs} 87397883Sgibbs 87497883Sgibbsstatic void 87597883Sgibbsahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 87697883Sgibbs{ 87797883Sgibbs uint8_t split_status[4]; 87897883Sgibbs uint8_t split_status1[4]; 87997883Sgibbs uint8_t sg_split_status[2]; 88097883Sgibbs uint8_t sg_split_status1[2]; 88197883Sgibbs ahd_mode_state saved_modes; 88297883Sgibbs u_int i; 883166109Sjhb uint32_t pcix_status; 88497883Sgibbs 88597883Sgibbs /* 88697883Sgibbs * Check for splits in all modes. Modes 0 and 1 88797883Sgibbs * additionally have SG engine splits to look at. 88897883Sgibbs */ 889166109Sjhb pcix_status = aic_pci_read_config(ahd->dev_softc, 890166109Sjhb ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 89197883Sgibbs printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 892166109Sjhb ahd_name(ahd), pcix_status >> 16); 89397883Sgibbs saved_modes = ahd_save_modes(ahd); 89497883Sgibbs for (i = 0; i < 4; i++) { 89597883Sgibbs ahd_set_modes(ahd, i, i); 89697883Sgibbs 89797883Sgibbs split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 89897883Sgibbs split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 899111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 90097883Sgibbs ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 90197883Sgibbs ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 902114623Sgibbs if (i > 1) 90397883Sgibbs continue; 90497883Sgibbs sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 90597883Sgibbs sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 906111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 90797883Sgibbs ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 90897883Sgibbs ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 90997883Sgibbs } 91097883Sgibbs 91197883Sgibbs for (i = 0; i < 4; i++) { 91297883Sgibbs u_int bit; 91397883Sgibbs 91497883Sgibbs for (bit = 0; bit < 8; bit++) { 91597883Sgibbs 91697883Sgibbs if ((split_status[i] & (0x1 << bit)) != 0) { 91797883Sgibbs static const char *s; 91897883Sgibbs 91997883Sgibbs s = split_status_strings[bit]; 92097883Sgibbs printf(s, ahd_name(ahd), 92197883Sgibbs split_status_source[i]); 92297883Sgibbs } 92397883Sgibbs 924114623Sgibbs if (i > 1) 92597883Sgibbs continue; 92697883Sgibbs 92797883Sgibbs if ((sg_split_status[i] & (0x1 << bit)) != 0) { 92897883Sgibbs static const char *s; 92997883Sgibbs 93097883Sgibbs s = split_status_strings[bit]; 93197883Sgibbs printf(s, ahd_name(ahd), "SG"); 93297883Sgibbs } 93397883Sgibbs } 93497883Sgibbs } 93597883Sgibbs /* 93697883Sgibbs * Clear PCI-X status bits. 93797883Sgibbs */ 938166109Sjhb aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 939166109Sjhb pcix_status, /*bytes*/4); 940107623Sscottl ahd_outb(ahd, CLRINT, CLRSPLTINT); 94197883Sgibbs ahd_restore_modes(ahd, saved_modes); 94297883Sgibbs} 94397883Sgibbs 94497883Sgibbsstatic int 945115330Sgibbsahd_aic7901_setup(struct ahd_softc *ahd) 946115330Sgibbs{ 947115330Sgibbs 948115330Sgibbs ahd->chip = AHD_AIC7901; 949116933Sgibbs ahd->features = AHD_AIC7901_FE; 950116933Sgibbs return (ahd_aic790X_setup(ahd)); 951115330Sgibbs} 952115330Sgibbs 953115330Sgibbsstatic int 954107440Sscottlahd_aic7901A_setup(struct ahd_softc *ahd) 95597883Sgibbs{ 956107440Sscottl 957107440Sscottl ahd->chip = AHD_AIC7901A; 958116933Sgibbs ahd->features = AHD_AIC7901A_FE; 959116933Sgibbs return (ahd_aic790X_setup(ahd)); 96097883Sgibbs} 96197883Sgibbs 96297883Sgibbsstatic int 96397883Sgibbsahd_aic7902_setup(struct ahd_softc *ahd) 96497883Sgibbs{ 965116933Sgibbs ahd->chip = AHD_AIC7902; 966116933Sgibbs ahd->features = AHD_AIC7902_FE; 967116933Sgibbs return (ahd_aic790X_setup(ahd)); 968116933Sgibbs} 969116933Sgibbs 970116933Sgibbsstatic int 971116933Sgibbsahd_aic790X_setup(struct ahd_softc *ahd) 972116933Sgibbs{ 973123579Sgibbs aic_dev_softc_t pci; 97497883Sgibbs u_int rev; 97597883Sgibbs 97697883Sgibbs pci = ahd->dev_softc; 977123579Sgibbs rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 978102686Sgibbs if (rev < ID_AIC7902_PCI_REV_A4) { 97997883Sgibbs printf("%s: Unable to attach to unsupported chip revision %d\n", 98097883Sgibbs ahd_name(ahd), rev); 981123579Sgibbs aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 98297883Sgibbs return (ENXIO); 98397883Sgibbs } 984123579Sgibbs ahd->channel = aic_get_pci_function(pci) + 'A'; 98597883Sgibbs if (rev < ID_AIC7902_PCI_REV_B0) { 98697883Sgibbs /* 98797883Sgibbs * Enable A series workarounds. 98897883Sgibbs */ 98997883Sgibbs ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 99097883Sgibbs | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 99197883Sgibbs | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 99297883Sgibbs | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 99397883Sgibbs | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 994111954Sgibbs | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 995111954Sgibbs | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 996111954Sgibbs | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 997111954Sgibbs | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 998114623Sgibbs | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 999114623Sgibbs | AHD_FAINT_LED_BUG; 100097883Sgibbs 1001107440Sscottl /* 1002107440Sscottl * IO Cell paramter setup. 1003107440Sscottl */ 1004107440Sscottl AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1005102686Sgibbs 1006107440Sscottl if ((ahd->flags & AHD_HP_BOARD) == 0) 1007107440Sscottl AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1008107440Sscottl } else { 1009107440Sscottl u_int devconfig1; 1010102686Sgibbs 1011107440Sscottl ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1012134156Sgibbs | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1013141979Sgibbs ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1014107440Sscottl 1015107440Sscottl /* 1016116933Sgibbs * Some issues have been resolved in the 7901B. 1017116933Sgibbs */ 1018116933Sgibbs if ((ahd->features & AHD_MULTI_FUNC) != 0) 1019141979Sgibbs ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1020141979Sgibbs | AHD_BUSFREEREV_BUG; 1021116933Sgibbs 1022116933Sgibbs /* 1023107440Sscottl * IO Cell paramter setup. 1024107440Sscottl */ 1025107440Sscottl AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1026107440Sscottl AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1027107440Sscottl AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1028107440Sscottl 1029107440Sscottl /* 1030107440Sscottl * Set the PREQDIS bit for H2B which disables some workaround 1031107440Sscottl * that doesn't work on regular PCI busses. 1032107440Sscottl * XXX - Find out exactly what this does from the hardware 1033107440Sscottl * folks! 1034107440Sscottl */ 1035123579Sgibbs devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1036123579Sgibbs aic_pci_write_config(pci, DEVCONFIG1, 1037107440Sscottl devconfig1|PREQDIS, /*bytes*/1); 1038123579Sgibbs devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1039107440Sscottl } 1040107440Sscottl 1041102686Sgibbs return (0); 1042102686Sgibbs} 1043