aic79xx.h revision 107441
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#73 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 107441 2002-12-01 08:13:37Z scottl $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100/* 101 * TCLs have the following format: TTTTLLLLLLLL 102 */ 103#define TCL_TARGET_OFFSET(tcl) \ 104 ((((tcl) >> 4) & TID) >> 4) 105#define TCL_LUN(tcl) \ 106 (tcl & (AHD_NUM_LUNS - 1)) 107#define BUILD_TCL(scsiid, lun) \ 108 ((lun) | (((scsiid) & TID) << 4)) 109#define BUILD_TCL_RAW(target, channel, lun) \ 110 ((lun) | ((target) << 8)) 111 112#define SCB_GET_TAG(scb) \ 113 ahd_le16toh(scb->hscb->tag) 114 115#ifndef AHD_TARGET_MODE 116#undef AHD_TMODE_ENABLE 117#define AHD_TMODE_ENABLE 0 118#endif 119 120#define AHD_BUILD_COL_IDX(target, lun) \ 121 (((lun) << 4) | target) 122 123#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 124 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 125 126#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 127do { \ 128 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 129 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 130} while (0) 131 132#define AHD_COPY_SCB_COL_IDX(dst, src) \ 133do { \ 134 dst->hscb->scsiid = src->hscb->scsiid; \ 135 dst->hscb->lun = src->hscb->lun; \ 136} while (0) 137 138#define AHD_NEVER_COL_IDX 0xFFFF 139 140/**************************** Driver Constants ********************************/ 141/* 142 * The maximum number of supported targets. 143 */ 144#define AHD_NUM_TARGETS 16 145 146/* 147 * The maximum number of supported luns. 148 * The identify message only supports 64 luns in non-packetized transfers. 149 * You can have 2^64 luns when information unit transfers are enabled, 150 * but until we see a need to support that many, we support 256. 151 */ 152#define AHD_NUM_LUNS_NONPKT 64 153#define AHD_NUM_LUNS 256 154 155/* 156 * The maximum transfer per S/G segment. 157 */ 158#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 159 160/* 161 * The maximum amount of SCB storage in hardware on a controller. 162 * This value represents an upper bound. Due to software design, 163 * we may not be able to use this number. 164 */ 165#define AHD_SCB_MAX 512 166 167/* 168 * The maximum number of concurrent transactions supported per driver instance. 169 * Sequencer Control Blocks (SCBs) store per-transaction information. 170 */ 171#define AHD_MAX_QUEUE AHD_SCB_MAX 172 173/* 174 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 175 * in size and accomodate as many transactions as can be queued concurrently. 176 */ 177#define AHD_QIN_SIZE AHD_MAX_QUEUE 178#define AHD_QOUT_SIZE AHD_MAX_QUEUE 179 180#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 181/* 182 * The maximum amount of SCB storage we allocate in host memory. 183 */ 184#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 185 186/* 187 * Ring Buffer of incoming target commands. 188 * We allocate 256 to simplify the logic in the sequencer 189 * by using the natural wrap point of an 8bit counter. 190 */ 191#define AHD_TMODE_CMDS 256 192 193/* Reset line assertion time in us */ 194#define AHD_BUSRESET_DELAY 25 195 196/******************* Chip Characteristics/Operating Settings *****************/ 197/* 198 * Chip Type 199 * The chip order is from least sophisticated to most sophisticated. 200 */ 201typedef enum { 202 AHD_NONE = 0x0000, 203 AHD_CHIPID_MASK = 0x00FF, 204 AHD_AIC7901 = 0x0001, 205 AHD_AIC7902 = 0x0002, 206 AHD_AIC7901A = 0x0003, 207 AHD_PCI = 0x0100, /* Bus type PCI */ 208 AHD_PCIX = 0x0200, /* Bus type PCIX */ 209 AHD_BUS_MASK = 0x0F00 210} ahd_chip; 211 212/* 213 * Features available in each chip type. 214 */ 215typedef enum { 216 AHD_FENONE = 0x00000, 217 AHD_WIDE = 0x00001,/* Wide Channel */ 218 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 219 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 220 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 221 AHD_RTI = 0x04000,/* Retained Training Support */ 222 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 223 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 224 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 225 AHD_AIC7901_FE = AHD_FENONE, 226 AHD_AIC7902_FE = AHD_MULTI_FUNC 227} ahd_feature; 228 229/* 230 * Bugs in the silicon that we work around in software. 231 */ 232typedef enum { 233 AHD_BUGNONE = 0x0000, 234 /* 235 * Rev A hardware fails to update LAST/CURR/NEXTSCB 236 * correctly in certain packetized selection cases. 237 */ 238 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 239 /* The wrong SCB is accessed to check the abort pending bit. */ 240 AHD_ABORT_LQI_BUG = 0x0002, 241 /* Packetized bitbucket crosses packet boundaries. */ 242 AHD_PKT_BITBUCKET_BUG = 0x0004, 243 /* The selection timer runs twice as long as its setting. */ 244 AHD_LONG_SETIMO_BUG = 0x0008, 245 /* The Non-LQ CRC error status is delayed until phase change. */ 246 AHD_NLQICRC_DELAYED_BUG = 0x0010, 247 /* The chip must be reset for all outgoing bus resets. */ 248 AHD_SCSIRST_BUG = 0x0020, 249 /* Some PCIX fields must be saved and restored across chip reset. */ 250 AHD_PCIX_CHIPRST_BUG = 0x0040, 251 /* MMAPIO is not functional in PCI-X mode. */ 252 AHD_PCIX_MMAPIO_BUG = 0x0080, 253 /* Bug workarounds that can be disabled on non-PCIX busses. */ 254 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 255 | AHD_PCIX_MMAPIO_BUG, 256 /* 257 * LQOSTOP0 status set even for forced selections with ATN 258 * to perform non-packetized message delivery. 259 */ 260 AHD_LQO_ATNO_BUG = 0x0100, 261 /* FIFO auto-flush does not always trigger. */ 262 AHD_AUTOFLUSH_BUG = 0x0200, 263 /* The CLRLQO registers are not self-clearing. */ 264 AHD_CLRLQO_AUTOCLR_BUG = 0x0400, 265 /* The PACKETIZED status bit refers to the previous connection. */ 266 AHD_PKTIZED_STATUS_BUG = 0x0800, 267 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 268 AHD_PKT_LUN_BUG = 0x1000, 269 /* 270 * Only the FIFO allocated to the non-packetized connection may 271 * be in use during a non-packetzied connection. 272 */ 273 AHD_NONPACKFIFO_BUG = 0x2000, 274 /* 275 * Writing to a DFF SCBPTR register may fail if concurent with 276 * a hardware write to the other DFF SCBPTR register. This is 277 * not currently a concern in our sequencer since all chips with 278 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 279 * occur in non-packetized connections. 280 */ 281 AHD_MDFF_WSCBPTR_BUG = 0x4000, 282 /* SGHADDR updates are slow. */ 283 AHD_REG_SLOW_SETTLE_BUG = 0x8000, 284 /* 285 * Changing the MODE_PTR coincident with an interrupt that 286 * switches to a different mode will cause the interrupt to 287 * be in the mode written outside of interrupt context. 288 */ 289 AHD_SET_MODE_BUG = 0x10000, 290 /* Non-packetized busfree revision does not work. */ 291 AHD_BUSFREEREV_BUG = 0x20000, 292 /* 293 * Paced transfers are indicated with a non-standard PPR 294 * option bit in the neg table, 160MHz is indicated by 295 * sync factor 0x7, and the offset if off by a factor of 2. 296 */ 297 AHD_PACED_NEGTABLE_BUG = 0x40000, 298 /* LQOOVERRUN false positives. */ 299 AHD_LQOOVERRUN_BUG = 0x80000, 300 /* 301 * Controller write to INTSTAT will lose to a host 302 * write to CLRINT. 303 */ 304 AHD_INTCOLLISION_BUG = 0x100000 305} ahd_bug; 306 307/* 308 * Configuration specific settings. 309 * The driver determines these settings by probing the 310 * chip/controller's configuration. 311 */ 312typedef enum { 313 AHD_FNONE = 0x00000, 314 AHD_PRIMARY_CHANNEL = 0x00003,/* 315 * The channel that should 316 * be probed first. 317 */ 318 AHD_USEDEFAULTS = 0x00004,/* 319 * For cards without an seeprom 320 * or a BIOS to initialize the chip's 321 * SRAM, we use the default target 322 * settings. 323 */ 324 AHD_SEQUENCER_DEBUG = 0x00008, 325 AHD_RESET_BUS_A = 0x00010, 326 AHD_EXTENDED_TRANS_A = 0x00020, 327 AHD_TERM_ENB_A = 0x00040, 328 AHD_SPCHK_ENB_A = 0x00080, 329 AHD_STPWLEVEL_A = 0x00100, 330 AHD_INITIATORROLE = 0x00200,/* 331 * Allow initiator operations on 332 * this controller. 333 */ 334 AHD_TARGETROLE = 0x00400,/* 335 * Allow target operations on this 336 * controller. 337 */ 338 AHD_RESOURCE_SHORTAGE = 0x00800, 339 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 340 AHD_INT50_SPEEDFLEX = 0x02000,/* 341 * Internal 50pin connector 342 * sits behind an aic3860 343 */ 344 AHD_BIOS_ENABLED = 0x04000, 345 AHD_ALL_INTERRUPTS = 0x08000, 346 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 347 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 348 AHD_CURRENT_SENSING = 0x40000, 349 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 350 AHD_HP_BOARD = 0x100000, 351 AHD_RESET_POLL_ACTIVE = 0x200000 352} ahd_flag; 353 354/************************* Hardware SCB Definition ***************************/ 355 356/* 357 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 358 * consists of a "hardware SCB" mirroring the fields availible on the card 359 * and additional information the kernel stores for each transaction. 360 * 361 * To minimize space utilization, a portion of the hardware scb stores 362 * different data during different portions of a SCSI transaction. 363 * As initialized by the host driver for the initiator role, this area 364 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 365 * the cdb has been presented to the target, this area serves to store 366 * residual transfer information and the SCSI status byte. 367 * For the target role, the contents of this area do not change, but 368 * still serve a different purpose than for the initiator role. See 369 * struct target_data for details. 370 */ 371 372/* 373 * Status information embedded in the shared poriton of 374 * an SCB after passing the cdb to the target. The kernel 375 * driver will only read this data for transactions that 376 * complete abnormally. 377 */ 378struct initiator_status { 379 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 380 uint32_t residual_sgptr; /* The next S/G for this transfer */ 381 uint8_t scsi_status; /* Standard SCSI status byte */ 382}; 383 384struct target_status { 385 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 386 uint32_t residual_sgptr; /* The next S/G for this transfer */ 387 uint8_t scsi_status; /* SCSI status to give to initiator */ 388 uint8_t target_phases; /* Bitmap of phases to execute */ 389 uint8_t data_phase; /* Data-In or Data-Out */ 390 uint8_t initiator_tag; /* Initiator's transaction tag */ 391}; 392 393/* 394 * Initiator mode SCB shared data area. 395 * If the embedded CDB is 12 bytes or less, we embed 396 * the sense buffer address in the SCB. This allows 397 * us to retrieve sense information without interupting 398 * the host in packetized mode. 399 */ 400typedef uint32_t sense_addr_t; 401#define MAX_CDB_LEN 16 402#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 403union initiator_data { 404 uint64_t cdbptr; 405 uint8_t cdb[MAX_CDB_LEN]; 406 struct { 407 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 408 sense_addr_t sense_addr; 409 } cdb_plus_saddr; 410}; 411 412/* 413 * Target mode version of the shared data SCB segment. 414 */ 415struct target_data { 416 uint32_t spare[2]; 417 uint8_t scsi_status; /* SCSI status to give to initiator */ 418 uint8_t target_phases; /* Bitmap of phases to execute */ 419 uint8_t data_phase; /* Data-In or Data-Out */ 420 uint8_t initiator_tag; /* Initiator's transaction tag */ 421}; 422 423struct hardware_scb { 424/*0*/ union { 425 union initiator_data idata; 426 struct target_data tdata; 427 struct initiator_status istatus; 428 struct target_status tstatus; 429 } shared_data; 430/* 431 * A word about residuals. 432 * The scb is presented to the sequencer with the dataptr and datacnt 433 * fields initialized to the contents of the first S/G element to 434 * transfer. The sgptr field is initialized to the bus address for 435 * the S/G element that follows the first in the in core S/G array 436 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 437 * S/G entry for this transfer (single S/G element transfer with the 438 * first elements address and length preloaded in the dataptr/datacnt 439 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 440 * The SG_FULL_RESID flag ensures that the residual will be correctly 441 * noted even if no data transfers occur. Once the data phase is entered, 442 * the residual sgptr and datacnt are loaded from the sgptr and the 443 * datacnt fields. After each S/G element's dataptr and length are 444 * loaded into the hardware, the residual sgptr is advanced. After 445 * each S/G element is expired, its datacnt field is checked to see 446 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 447 * residual sg ptr and the transfer is considered complete. If the 448 * sequencer determines that there is a residual in the tranfer, or 449 * there is non-zero status, it will set the SG_STATUS_VALID flag in 450 * sgptr and dma the scb back into host memory. To sumarize: 451 * 452 * Sequencer: 453 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 454 * or residual_sgptr does not have SG_LIST_NULL set. 455 * 456 * o We are transfering the last segment if residual_datacnt has 457 * the SG_LAST_SEG flag set. 458 * 459 * Host: 460 * o A residual can only have occurred if a completed scb has the 461 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 462 * the residual_datacnt, and the residual_sgptr field will tell 463 * for sure. 464 * 465 * o residual_sgptr and sgptr refer to the "next" sg entry 466 * and so may point beyond the last valid sg entry for the 467 * transfer. 468 */ 469#define SG_PTR_MASK 0xFFFFFFF8 470/*16*/ uint16_t tag; 471/*18*/ uint8_t cdb_len; 472/*19*/ uint8_t task_management; 473/*20*/ uint32_t next_hscb_busaddr; 474/*24*/ uint64_t dataptr; 475/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 476/*36*/ uint32_t sgptr; 477/*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 478/*41*/ uint8_t scsiid; /* 479 * Selection out Id 480 * Our Id (bits 0-3) Their ID (bits 4-7) 481 */ 482/*42*/ uint8_t lun; 483/*43*/ uint8_t task_attribute; 484/*44*/ uint32_t hscb_busaddr; 485/******* Long lun field only downloaded for full 8 byte lun support *******/ 486/*48*/ uint8_t pkt_long_lun[8]; 487/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 488/*56*/ uint8_t spare[8]; 489}; 490 491/************************ Kernel SCB Definitions ******************************/ 492/* 493 * Some fields of the SCB are OS dependent. Here we collect the 494 * definitions for elements that all OS platforms need to include 495 * in there SCB definition. 496 */ 497 498/* 499 * Definition of a scatter/gather element as transfered to the controller. 500 * The aic7xxx chips only support a 24bit length. We use the top byte of 501 * the length to store additional address bits and a flag to indicate 502 * that a given segment terminates the transfer. This gives us an 503 * addressable range of 512GB on machines with 64bit PCI or with chips 504 * that can support dual address cycles on 32bit PCI busses. 505 */ 506struct ahd_dma_seg { 507 uint32_t addr; 508 uint32_t len; 509#define AHD_DMA_LAST_SEG 0x80000000 510#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 511#define AHD_SG_LEN_MASK 0x00FFFFFF 512}; 513 514struct ahd_dma64_seg { 515 uint64_t addr; 516 uint32_t len; 517 uint32_t pad; 518}; 519 520struct map_node { 521 bus_dmamap_t dmamap; 522 bus_addr_t physaddr; 523 uint8_t *vaddr; 524 SLIST_ENTRY(map_node) links; 525}; 526 527/* 528 * The current state of this SCB. 529 */ 530typedef enum { 531 SCB_FLAG_NONE = 0x00000, 532 SCB_TRANSMISSION_ERROR = 0x00001,/* 533 * We detected a parity or CRC 534 * error that has effected the 535 * payload of the command. This 536 * flag is checked when normal 537 * status is returned to catch 538 * the case of a target not 539 * responding to our attempt 540 * to report the error. 541 */ 542 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 543 * Another device was active 544 * during the first timeout for 545 * this SCB so we gave ourselves 546 * an additional timeout period 547 * in case it was hogging the 548 * bus. 549 */ 550 SCB_DEVICE_RESET = 0x00004, 551 SCB_SENSE = 0x00008, 552 SCB_CDB32_PTR = 0x00010, 553 SCB_RECOVERY_SCB = 0x00020, 554 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 555 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 556 SCB_ABORT = 0x00100, 557 SCB_ACTIVE = 0x00200, 558 SCB_TARGET_IMMEDIATE = 0x00400, 559 SCB_PACKETIZED = 0x00800, 560 SCB_EXPECT_PPR_BUSFREE = 0x01000, 561 SCB_PKT_SENSE = 0x02000, 562 SCB_CMDPHASE_ABORT = 0x04000, 563 SCB_ON_COL_LIST = 0x08000 564} scb_flag; 565 566struct scb { 567 struct hardware_scb *hscb; 568 union { 569 SLIST_ENTRY(scb) sle; 570 LIST_ENTRY(scb) le; 571 TAILQ_ENTRY(scb) tqe; 572 } links; 573 union { 574 SLIST_ENTRY(scb) sle; 575 LIST_ENTRY(scb) le; 576 TAILQ_ENTRY(scb) tqe; 577 } links2; 578#define pending_links links2.le 579#define collision_links links2.le 580 struct scb *col_scb; 581 ahd_io_ctx_t io_ctx; 582 struct ahd_softc *ahd_softc; 583 scb_flag flags; 584#ifndef __linux__ 585 bus_dmamap_t dmamap; 586#endif 587 struct scb_platform_data *platform_data; 588 struct map_node *hscb_map; 589 struct map_node *sg_map; 590 struct map_node *sense_map; 591 void *sg_list; 592 uint8_t *sense_data; 593 bus_addr_t sg_list_busaddr; 594 bus_addr_t sense_busaddr; 595 u_int sg_count;/* How full ahd_dma_seg is */ 596#define AHD_MAX_LQ_CRC_ERRORS 5 597 u_int crc_retry_count; 598}; 599 600TAILQ_HEAD(scb_tailq, scb); 601LIST_HEAD(scb_list, scb); 602 603struct scb_data { 604 /* 605 * TAILQ of lists of free SCBs grouped by device 606 * collision domains. 607 */ 608 struct scb_tailq free_scbs; 609 610 /* 611 * Per-device lists of SCBs whose tag ID would collide 612 * with an already active tag on the device. 613 */ 614 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 615 616 /* 617 * SCBs that will not collide with any active device. 618 */ 619 struct scb_list any_dev_free_scb_list; 620 621 /* 622 * Mapping from tag to SCB. 623 */ 624 struct scb *scbindex[AHD_SCB_MAX]; 625 626 /* 627 * "Bus" addresses of our data structures. 628 */ 629 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 630 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 631 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 632 SLIST_HEAD(, map_node) hscb_maps; 633 SLIST_HEAD(, map_node) sg_maps; 634 SLIST_HEAD(, map_node) sense_maps; 635 int scbs_left; /* unallocated scbs in head map_node */ 636 int sgs_left; /* unallocated sgs in head map_node */ 637 int sense_left; /* unallocated sense in head map_node */ 638 uint16_t numscbs; 639 uint16_t maxhscbs; /* Number of SCBs on the card */ 640 uint8_t init_level; /* 641 * How far we've initialized 642 * this structure. 643 */ 644}; 645 646/************************ Target Mode Definitions *****************************/ 647 648/* 649 * Connection desciptor for select-in requests in target mode. 650 */ 651struct target_cmd { 652 uint8_t scsiid; /* Our ID and the initiator's ID */ 653 uint8_t identify; /* Identify message */ 654 uint8_t bytes[22]; /* 655 * Bytes contains any additional message 656 * bytes terminated by 0xFF. The remainder 657 * is the cdb to execute. 658 */ 659 uint8_t cmd_valid; /* 660 * When a command is complete, the firmware 661 * will set cmd_valid to all bits set. 662 * After the host has seen the command, 663 * the bits are cleared. This allows us 664 * to just peek at host memory to determine 665 * if more work is complete. cmd_valid is on 666 * an 8 byte boundary to simplify setting 667 * it on aic7880 hardware which only has 668 * limited direct access to the DMA FIFO. 669 */ 670 uint8_t pad[7]; 671}; 672 673/* 674 * Number of events we can buffer up if we run out 675 * of immediate notify ccbs. 676 */ 677#define AHD_TMODE_EVENT_BUFFER_SIZE 8 678struct ahd_tmode_event { 679 uint8_t initiator_id; 680 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 681#define EVENT_TYPE_BUS_RESET 0xFF 682 uint8_t event_arg; 683}; 684 685/* 686 * Per enabled lun target mode state. 687 * As this state is directly influenced by the host OS'es target mode 688 * environment, we let the OS module define it. Forward declare the 689 * structure here so we can store arrays of them, etc. in OS neutral 690 * data structures. 691 */ 692#ifdef AHD_TARGET_MODE 693struct ahd_tmode_lstate { 694 struct cam_path *path; 695 struct ccb_hdr_slist accept_tios; 696 struct ccb_hdr_slist immed_notifies; 697 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 698 uint8_t event_r_idx; 699 uint8_t event_w_idx; 700}; 701#else 702struct ahd_tmode_lstate; 703#endif 704 705/******************** Transfer Negotiation Datastructures *********************/ 706#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 707#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 708#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 709#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 710#define AHD_PERIOD_ASYNC 0xFF 711#define AHD_PERIOD_10MHz 0x19 712 713#define AHD_WIDTH_UNKNOWN 0xFF 714#define AHD_PERIOD_UNKNOWN 0xFF 715#define AHD_OFFSET_UNKNOWN 0x0 716#define AHD_PPR_OPTS_UNKNOWN 0xFF 717 718/* 719 * Transfer Negotiation Information. 720 */ 721struct ahd_transinfo { 722 uint8_t protocol_version; /* SCSI Revision level */ 723 uint8_t transport_version; /* SPI Revision level */ 724 uint8_t width; /* Bus width */ 725 uint8_t period; /* Sync rate factor */ 726 uint8_t offset; /* Sync offset */ 727 uint8_t ppr_options; /* Parallel Protocol Request options */ 728}; 729 730/* 731 * Per-initiator current, goal and user transfer negotiation information. */ 732struct ahd_initiator_tinfo { 733 struct ahd_transinfo curr; 734 struct ahd_transinfo goal; 735 struct ahd_transinfo user; 736}; 737 738/* 739 * Per enabled target ID state. 740 * Pointers to lun target state as well as sync/wide negotiation information 741 * for each initiator<->target mapping. For the initiator role we pretend 742 * that we are the target and the targets are the initiators since the 743 * negotiation is the same regardless of role. 744 */ 745struct ahd_tmode_tstate { 746 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 747 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 748 749 /* 750 * Per initiator state bitmasks. 751 */ 752 uint16_t auto_negotiate;/* Auto Negotiation Required */ 753 uint16_t discenable; /* Disconnection allowed */ 754 uint16_t tagenable; /* Tagged Queuing allowed */ 755}; 756 757/* 758 * Points of interest along the negotiated transfer scale. 759 */ 760#define AHD_SYNCRATE_MAX 0x8 761#define AHD_SYNCRATE_160 0x8 762#define AHD_SYNCRATE_PACED 0x8 763#define AHD_SYNCRATE_DT 0x9 764#define AHD_SYNCRATE_ULTRA2 0xa 765#define AHD_SYNCRATE_ULTRA 0xc 766#define AHD_SYNCRATE_FAST 0x19 767#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 768#define AHD_SYNCRATE_SYNC 0x32 769#define AHD_SYNCRATE_MIN 0x60 770#define AHD_SYNCRATE_ASYNC 0xFF 771 772/* Safe and valid period for async negotiations. */ 773#define AHD_ASYNC_XFER_PERIOD 0x44 774 775/* 776 * In RevA, the synctable uses a 120MHz rate for the period 777 * factor 8 and 160MHz for the period factor 7. The 120MHz 778 * rate never made it into the official SCSI spec, so we must 779 * compensate when setting the negotiation table for Rev A 780 * parts. 781 */ 782#define AHD_SYNCRATE_REVA_120 0x8 783#define AHD_SYNCRATE_REVA_160 0x7 784 785/***************************** Lookup Tables **********************************/ 786/* 787 * Phase -> name and message out response 788 * to parity errors in each phase table. 789 */ 790struct ahd_phase_table_entry { 791 uint8_t phase; 792 uint8_t mesg_out; /* Message response to parity errors */ 793 char *phasemsg; 794}; 795 796/************************** Serial EEPROM Format ******************************/ 797 798struct seeprom_config { 799/* 800 * Per SCSI ID Configuration Flags 801 */ 802 uint16_t device_flags[16]; /* words 0-15 */ 803#define CFXFER 0x003F /* synchronous transfer rate */ 804#define CFXFER_ASYNC 0x3F 805#define CFQAS 0x0040 /* Negotiate QAS */ 806#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 807#define CFSTART 0x0100 /* send start unit SCSI command */ 808#define CFINCBIOS 0x0200 /* include in BIOS scan */ 809#define CFDISC 0x0400 /* enable disconnection */ 810#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 811#define CFWIDEB 0x1000 /* wide bus device */ 812#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 813 814/* 815 * BIOS Control Bits 816 */ 817 uint16_t bios_control; /* word 16 */ 818#define CFSUPREM 0x0001 /* support all removeable drives */ 819#define CFSUPREMB 0x0002 /* support removeable boot drives */ 820#define CFBIOSSTATE 0x000C /* BIOS Action State */ 821#define CFBS_DISABLED 0x00 822#define CFBS_ENABLED 0x04 823#define CFBS_DISABLED_SCAN 0x08 824#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 825#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 826#define CFSPARITY 0x0040 /* SCSI parity */ 827#define CFEXTEND 0x0080 /* extended translation enabled */ 828#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 829#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 830#define CFMSG_VERBOSE 0x0000 831#define CFMSG_SILENT 0x0200 832#define CFMSG_DIAG 0x0400 833#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 834/* UNUSED 0xf000 */ 835 836/* 837 * Host Adapter Control Bits 838 */ 839 uint16_t adapter_control; /* word 17 */ 840#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 841#define CFSTERM 0x0002 /* SCSI low byte termination */ 842#define CFWSTERM 0x0004 /* SCSI high byte termination */ 843#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 844#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 845#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 846#define CFSTPWLEVEL 0x0040 /* Termination level control */ 847#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 848#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 849#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 850 851/* 852 * Bus Release Time, Host Adapter ID 853 */ 854 uint16_t brtime_id; /* word 18 */ 855#define CFSCSIID 0x000f /* host adapter SCSI ID */ 856/* UNUSED 0x00f0 */ 857#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 858 859/* 860 * Maximum targets 861 */ 862 uint16_t max_targets; /* word 19 */ 863#define CFMAXTARG 0x00ff /* maximum targets */ 864#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 865#define CFBOOTID 0xf000 /* Target to boot from */ 866 uint16_t res_1[10]; /* words 20-29 */ 867 uint16_t signature; /* BIOS Signature */ 868#define CFSIGNATURE 0x400 869 uint16_t checksum; /* word 31 */ 870}; 871 872/****************************** Flexport Logic ********************************/ 873#define FLXADDR_TERMCTL 0x0 874#define FLX_TERMCTL_ENSECHIGH 0x8 875#define FLX_TERMCTL_ENSECLOW 0x4 876#define FLX_TERMCTL_ENPRIHIGH 0x2 877#define FLX_TERMCTL_ENPRILOW 0x1 878#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 879#define FLX_ROMSTAT_SEECFG 0xF0 880#define FLX_ROMSTAT_EECFG 0x0F 881#define FLX_ROMSTAT_SEE_93C66 0x00 882#define FLX_ROMSTAT_SEE_NONE 0xF0 883#define FLX_ROMSTAT_EE_512x8 0x0 884#define FLX_ROMSTAT_EE_1MBx8 0x1 885#define FLX_ROMSTAT_EE_2MBx8 0x2 886#define FLX_ROMSTAT_EE_4MBx8 0x3 887#define FLX_ROMSTAT_EE_16MBx8 0x4 888#define CURSENSE_ENB 0x1 889#define FLXADDR_FLEXSTAT 0x2 890#define FLX_FSTAT_BUSY 0x1 891#define FLXADDR_CURRENT_STAT 0x4 892#define FLX_CSTAT_SEC_HIGH 0xC0 893#define FLX_CSTAT_SEC_LOW 0x30 894#define FLX_CSTAT_PRI_HIGH 0x0C 895#define FLX_CSTAT_PRI_LOW 0x03 896#define FLX_CSTAT_MASK 0x03 897#define FLX_CSTAT_SHIFT 2 898#define FLX_CSTAT_OKAY 0x0 899#define FLX_CSTAT_OVER 0x1 900#define FLX_CSTAT_UNDER 0x2 901#define FLX_CSTAT_INVALID 0x3 902 903int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 904 u_int start_addr, u_int count); 905 906int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 907 u_int start_addr, u_int count); 908int ahd_wait_seeprom(struct ahd_softc *ahd); 909int ahd_verify_cksum(struct seeprom_config *sc); 910int ahd_acquire_seeprom(struct ahd_softc *ahd); 911void ahd_release_seeprom(struct ahd_softc *ahd); 912 913/**************************** Message Buffer *********************************/ 914typedef enum { 915 MSG_FLAG_NONE = 0x00, 916 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 917 MSG_FLAG_IU_REQ_CHANGED = 0x02, 918 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 919 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 920 MSG_FLAG_PACKETIZED = 0x10 921} ahd_msg_flags; 922 923typedef enum { 924 MSG_TYPE_NONE = 0x00, 925 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 926 MSG_TYPE_INITIATOR_MSGIN = 0x02, 927 MSG_TYPE_TARGET_MSGOUT = 0x03, 928 MSG_TYPE_TARGET_MSGIN = 0x04 929} ahd_msg_type; 930 931typedef enum { 932 MSGLOOP_IN_PROG, 933 MSGLOOP_MSGCOMPLETE, 934 MSGLOOP_TERMINATED 935} msg_loop_stat; 936 937/*********************** Software Configuration Structure *********************/ 938struct ahd_suspend_channel_state { 939 uint8_t scsiseq; 940 uint8_t sxfrctl0; 941 uint8_t sxfrctl1; 942 uint8_t simode0; 943 uint8_t simode1; 944 uint8_t seltimer; 945 uint8_t seqctl; 946}; 947 948struct ahd_suspend_state { 949 struct ahd_suspend_channel_state channel[2]; 950 uint8_t optionmode; 951 uint8_t dscommand0; 952 uint8_t dspcistatus; 953 /* hsmailbox */ 954 uint8_t crccontrol1; 955 uint8_t scbbaddr; 956 /* Host and sequencer SCB counts */ 957 uint8_t dff_thrsh; 958 uint8_t *scratch_ram; 959 uint8_t *btt; 960}; 961 962typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 963 964typedef enum { 965 AHD_MODE_DFF0, 966 AHD_MODE_DFF1, 967 AHD_MODE_CCHAN, 968 AHD_MODE_SCSI, 969 AHD_MODE_CFG, 970 AHD_MODE_UNKNOWN 971} ahd_mode; 972 973#define AHD_MK_MSK(x) (0x01 << (x)) 974#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 975#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 976#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 977#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 978#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 979#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 980#define AHD_MODE_ANY_MSK (~0) 981 982typedef uint8_t ahd_mode_state; 983 984typedef void ahd_callback_t (void *); 985 986struct ahd_softc { 987 bus_space_tag_t tags[2]; 988 bus_space_handle_t bshs[2]; 989#ifndef __linux__ 990 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 991#endif 992 struct scb_data scb_data; 993 994 struct hardware_scb *next_queued_hscb; 995 996 /* 997 * SCBs that have been sent to the controller 998 */ 999 LIST_HEAD(, scb) pending_scbs; 1000 1001 /* 1002 * Current register window mode information. 1003 */ 1004 ahd_mode dst_mode; 1005 ahd_mode src_mode; 1006 1007 /* 1008 * Saved register window mode information 1009 * used for restore on next unpause. 1010 */ 1011 ahd_mode saved_dst_mode; 1012 ahd_mode saved_src_mode; 1013 1014 /* 1015 * Platform specific data. 1016 */ 1017 struct ahd_platform_data *platform_data; 1018 1019 /* 1020 * Platform specific device information. 1021 */ 1022 ahd_dev_softc_t dev_softc; 1023 1024 /* 1025 * Bus specific device information. 1026 */ 1027 ahd_bus_intr_t bus_intr; 1028 1029 /* 1030 * Target mode related state kept on a per enabled lun basis. 1031 * Targets that are not enabled will have null entries. 1032 * As an initiator, we keep one target entry for our initiator 1033 * ID to store our sync/wide transfer settings. 1034 */ 1035 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1036 1037 /* 1038 * The black hole device responsible for handling requests for 1039 * disabled luns on enabled targets. 1040 */ 1041 struct ahd_tmode_lstate *black_hole; 1042 1043 /* 1044 * Device instance currently on the bus awaiting a continue TIO 1045 * for a command that was not given the disconnect priveledge. 1046 */ 1047 struct ahd_tmode_lstate *pending_device; 1048 1049 /* 1050 * Timer handles for timer driven callbacks. 1051 */ 1052 ahd_timer_t reset_timer; 1053 1054 /* 1055 * Card characteristics 1056 */ 1057 ahd_chip chip; 1058 ahd_feature features; 1059 ahd_bug bugs; 1060 ahd_flag flags; 1061 struct seeprom_config *seep_config; 1062 1063 /* Values to store in the SEQCTL register for pause and unpause */ 1064 uint8_t unpause; 1065 uint8_t pause; 1066 1067 /* Command Queues */ 1068 uint16_t qoutfifonext; 1069 uint16_t qoutfifonext_valid_tag; 1070 uint16_t qinfifonext; 1071 uint16_t qinfifo[AHD_SCB_MAX]; 1072 uint16_t *qoutfifo; 1073 1074 /* Critical Section Data */ 1075 struct cs *critical_sections; 1076 u_int num_critical_sections; 1077 1078 /* Buffer for handling packetized bitbucket. */ 1079 uint8_t *overrun_buf; 1080 1081 /* Links for chaining softcs */ 1082 TAILQ_ENTRY(ahd_softc) links; 1083 1084 /* Channel Names ('A', 'B', etc.) */ 1085 char channel; 1086 1087 /* Initiator Bus ID */ 1088 uint8_t our_id; 1089 1090 /* 1091 * Target incoming command FIFO. 1092 */ 1093 struct target_cmd *targetcmds; 1094 uint8_t tqinfifonext; 1095 1096 /* 1097 * Incoming and outgoing message handling. 1098 */ 1099 uint8_t send_msg_perror; 1100 ahd_msg_flags msg_flags; 1101 ahd_msg_type msg_type; 1102 uint8_t msgout_buf[12];/* Message we are sending */ 1103 uint8_t msgin_buf[12];/* Message we are receiving */ 1104 u_int msgout_len; /* Length of message to send */ 1105 u_int msgout_index; /* Current index in msgout */ 1106 u_int msgin_index; /* Current index in msgin */ 1107 1108 /* 1109 * Mapping information for data structures shared 1110 * between the sequencer and kernel. 1111 */ 1112 bus_dma_tag_t parent_dmat; 1113 bus_dma_tag_t shared_data_dmat; 1114 bus_dmamap_t shared_data_dmamap; 1115 bus_addr_t shared_data_busaddr; 1116 1117 /* Information saved through suspend/resume cycles */ 1118 struct ahd_suspend_state suspend_state; 1119 1120 /* Number of enabled target mode device on this card */ 1121 u_int enabled_luns; 1122 1123 /* Initialization level of this data structure */ 1124 u_int init_level; 1125 1126 /* PCI cacheline size. */ 1127 u_int pci_cachesize; 1128 1129 /* IO Cell Parameters */ 1130 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1131 1132 u_int stack_size; 1133 uint16_t *saved_stack; 1134 1135 /* Per-Unit descriptive information */ 1136 const char *description; 1137 const char *bus_description; 1138 char *name; 1139 int unit; 1140 1141 /* Selection Timer settings */ 1142 int seltime; 1143 1144 uint16_t user_discenable;/* Disconnection allowed */ 1145 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1146}; 1147 1148TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1149extern struct ahd_softc_tailq ahd_tailq; 1150 1151/*************************** IO Cell Configuration ****************************/ 1152#define AHD_PRECOMP_SLEW_INDEX \ 1153 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1154 1155#define AHD_AMPLITUDE_INDEX \ 1156 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1157 1158#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1159do { \ 1160 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1161 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1162 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1163} while (0) 1164 1165#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1166do { \ 1167 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1168 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1169 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1170} while (0) 1171 1172#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1173do { \ 1174 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1175 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1176 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1177} while (0) 1178 1179/************************ Active Device Information ***************************/ 1180typedef enum { 1181 ROLE_UNKNOWN, 1182 ROLE_INITIATOR, 1183 ROLE_TARGET 1184} role_t; 1185 1186struct ahd_devinfo { 1187 int our_scsiid; 1188 int target_offset; 1189 uint16_t target_mask; 1190 u_int target; 1191 u_int lun; 1192 char channel; 1193 role_t role; /* 1194 * Only guaranteed to be correct if not 1195 * in the busfree state. 1196 */ 1197}; 1198 1199/****************************** PCI Structures ********************************/ 1200#define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1201#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1202#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1203 1204typedef int (ahd_device_setup_t)(struct ahd_softc *); 1205 1206struct ahd_pci_identity { 1207 uint64_t full_id; 1208 uint64_t id_mask; 1209 char *name; 1210 ahd_device_setup_t *setup; 1211}; 1212extern struct ahd_pci_identity ahd_pci_ident_table []; 1213extern const u_int ahd_num_pci_devs; 1214 1215/***************************** VL/EISA Declarations ***************************/ 1216struct aic7770_identity { 1217 uint32_t full_id; 1218 uint32_t id_mask; 1219 char *name; 1220 ahd_device_setup_t *setup; 1221}; 1222extern struct aic7770_identity aic7770_ident_table []; 1223extern const int ahd_num_aic7770_devs; 1224 1225#define AHD_EISA_SLOT_OFFSET 0xc00 1226#define AHD_EISA_IOSIZE 0x100 1227 1228/*************************** Function Declarations ****************************/ 1229/******************************************************************************/ 1230u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1231void ahd_busy_tcl(struct ahd_softc *ahd, 1232 u_int tcl, u_int busyid); 1233static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1234static __inline void 1235ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1236{ 1237 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1238} 1239 1240/***************************** PCI Front End *********************************/ 1241struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1242int ahd_pci_config(struct ahd_softc *, 1243 struct ahd_pci_identity *); 1244int ahd_pci_test_register_access(struct ahd_softc *); 1245 1246/************************** SCB and SCB queue management **********************/ 1247int ahd_probe_scbs(struct ahd_softc *); 1248void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1249 struct scb *scb); 1250int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1251 int target, char channel, int lun, 1252 u_int tag, role_t role); 1253 1254/****************************** Initialization ********************************/ 1255struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1256int ahd_softc_init(struct ahd_softc *); 1257void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1258int ahd_init(struct ahd_softc *ahd); 1259int ahd_default_config(struct ahd_softc *ahd); 1260int ahd_parse_cfgdata(struct ahd_softc *ahd, 1261 struct seeprom_config *sc); 1262void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1263void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1264int ahd_suspend(struct ahd_softc *ahd); 1265int ahd_resume(struct ahd_softc *ahd); 1266void ahd_softc_insert(struct ahd_softc *); 1267struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1268void ahd_set_unit(struct ahd_softc *, int); 1269void ahd_set_name(struct ahd_softc *, char *); 1270struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1271void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1272void ahd_alloc_scbs(struct ahd_softc *ahd); 1273void ahd_free(struct ahd_softc *ahd); 1274int ahd_reset(struct ahd_softc *ahd); 1275void ahd_shutdown(void *arg); 1276int ahd_write_flexport(struct ahd_softc *ahd, 1277 u_int addr, u_int value); 1278int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1279 uint8_t *value); 1280int ahd_wait_flexport(struct ahd_softc *ahd); 1281 1282/*************************** Interrupt Services *******************************/ 1283void ahd_pci_intr(struct ahd_softc *ahd); 1284void ahd_clear_intstat(struct ahd_softc *ahd); 1285void ahd_run_qoutfifo(struct ahd_softc *ahd); 1286#ifdef AHD_TARGET_MODE 1287void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1288#endif 1289void ahd_handle_hwerrint(struct ahd_softc *ahd); 1290void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1291void ahd_handle_scsiint(struct ahd_softc *ahd, 1292 u_int intstat); 1293void ahd_clear_critical_section(struct ahd_softc *ahd); 1294 1295/***************************** Error Recovery *********************************/ 1296typedef enum { 1297 SEARCH_COMPLETE, 1298 SEARCH_COUNT, 1299 SEARCH_REMOVE, 1300 SEARCH_PRINT 1301} ahd_search_action; 1302int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1303 char channel, int lun, u_int tag, 1304 role_t role, uint32_t status, 1305 ahd_search_action action); 1306int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1307 char channel, int lun, u_int tag, 1308 int stop_on_first, int remove, 1309 int save_state); 1310void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1311int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1312 int initiate_reset); 1313int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1314 char channel, int lun, u_int tag, 1315 role_t role, uint32_t status); 1316void ahd_restart(struct ahd_softc *ahd); 1317void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1318void ahd_handle_scb_status(struct ahd_softc *ahd, 1319 struct scb *scb); 1320void ahd_handle_scsi_status(struct ahd_softc *ahd, 1321 struct scb *scb); 1322void ahd_calc_residual(struct ahd_softc *ahd, 1323 struct scb *scb); 1324/*************************** Utility Functions ********************************/ 1325struct ahd_phase_table_entry* 1326 ahd_lookup_phase_entry(int phase); 1327void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1328 u_int our_id, u_int target, 1329 u_int lun, char channel, 1330 role_t role); 1331/************************** Transfer Negotiation ******************************/ 1332void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1333 u_int *ppr_options, u_int maxsync); 1334void ahd_validate_offset(struct ahd_softc *ahd, 1335 struct ahd_initiator_tinfo *tinfo, 1336 u_int period, u_int *offset, 1337 int wide, role_t role); 1338void ahd_validate_width(struct ahd_softc *ahd, 1339 struct ahd_initiator_tinfo *tinfo, 1340 u_int *bus_width, 1341 role_t role); 1342/* 1343 * Negotiation types. These are used to qualify if we should renegotiate 1344 * even if our goal and current transport parameters are identical. 1345 */ 1346typedef enum { 1347 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1348 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1349 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1350} ahd_neg_type; 1351int ahd_update_neg_request(struct ahd_softc*, 1352 struct ahd_devinfo*, 1353 struct ahd_tmode_tstate*, 1354 struct ahd_initiator_tinfo*, 1355 ahd_neg_type); 1356void ahd_set_width(struct ahd_softc *ahd, 1357 struct ahd_devinfo *devinfo, 1358 u_int width, u_int type, int paused); 1359void ahd_set_syncrate(struct ahd_softc *ahd, 1360 struct ahd_devinfo *devinfo, 1361 u_int period, u_int offset, 1362 u_int ppr_options, 1363 u_int type, int paused); 1364typedef enum { 1365 AHD_QUEUE_NONE, 1366 AHD_QUEUE_BASIC, 1367 AHD_QUEUE_TAGGED 1368} ahd_queue_alg; 1369 1370void ahd_set_tags(struct ahd_softc *ahd, 1371 struct ahd_devinfo *devinfo, 1372 ahd_queue_alg alg); 1373 1374/**************************** Target Mode *************************************/ 1375#ifdef AHD_TARGET_MODE 1376void ahd_send_lstate_events(struct ahd_softc *, 1377 struct ahd_tmode_lstate *); 1378void ahd_handle_en_lun(struct ahd_softc *ahd, 1379 struct cam_sim *sim, union ccb *ccb); 1380cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1381 struct cam_sim *sim, union ccb *ccb, 1382 struct ahd_tmode_tstate **tstate, 1383 struct ahd_tmode_lstate **lstate, 1384 int notfound_failure); 1385#ifndef AHD_TMODE_ENABLE 1386#define AHD_TMODE_ENABLE 0 1387#endif 1388#endif 1389/******************************* Debug ***************************************/ 1390#ifdef AHD_DEBUG 1391extern uint32_t ahd_debug; 1392#define AHD_SHOW_MISC 0x00001 1393#define AHD_SHOW_SENSE 0x00002 1394#define AHD_SHOW_RECOVERY 0x00004 1395#define AHD_DUMP_SEEPROM 0x00008 1396#define AHD_SHOW_TERMCTL 0x00010 1397#define AHD_SHOW_MEMORY 0x00020 1398#define AHD_SHOW_MESSAGES 0x00040 1399#define AHD_SHOW_MODEPTR 0x00080 1400#define AHD_SHOW_SELTO 0x00100 1401#define AHD_SHOW_FIFOS 0x00200 1402#define AHD_SHOW_QFULL 0x00400 1403#define AHD_SHOW_DV 0x00800 1404#define AHD_SHOW_MASKED_ERRORS 0x01000 1405#define AHD_SHOW_QUEUE 0x02000 1406#define AHD_SHOW_TQIN 0x04000 1407#define AHD_SHOW_SG 0x08000 1408#define AHD_DEBUG_SEQUENCER 0x10000 1409#endif 1410void ahd_print_scb(struct scb *scb); 1411void ahd_print_devinfo(struct ahd_softc *ahd, 1412 struct ahd_devinfo *devinfo); 1413void ahd_dump_sglist(struct scb *scb); 1414void ahd_dump_all_cards_state(void); 1415void ahd_dump_card_state(struct ahd_softc *ahd); 1416int ahd_print_register(ahd_reg_parse_entry_t *table, 1417 u_int num_entries, 1418 const char *name, 1419 u_int address, 1420 u_int value, 1421 u_int *cur_column, 1422 u_int wrap_point); 1423void ahd_dump_scbs(struct ahd_softc *ahd); 1424#endif /* _AIC79XX_H_ */ 1425