cvmx-npi.h revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * PCI / PCIe packet engine related structures. 48210284Sjmallett * 49210284Sjmallett * <hr>$Revision: 41586 $<hr> 50210284Sjmallett */ 51210284Sjmallett 52210284Sjmallett#ifndef __CVMX_NPI_H__ 53210284Sjmallett#define __CVMX_NPI_H__ 54210284Sjmallett 55210284Sjmallett#ifdef __cplusplus 56210284Sjmallettextern "C" { 57210284Sjmallett#endif 58210284Sjmallett 59210284Sjmallett/** 60210284Sjmallett * PCI / PCIe packet instruction header format 61210284Sjmallett */ 62210284Sjmalletttypedef union 63210284Sjmallett{ 64210284Sjmallett uint64_t u64; 65210284Sjmallett struct 66210284Sjmallett { 67210284Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 68210284Sjmallett uint64_t r : 1; /**< Packet is RAW */ 69210284Sjmallett uint64_t g : 1; /**< Gather list is used */ 70210284Sjmallett uint64_t dlengsz : 14; /**< Data length / Gather list size */ 71210284Sjmallett uint64_t fsz : 6; /**< Front data size */ 72210284Sjmallett uint64_t qos : 3; /**< POW QoS queue */ 73210284Sjmallett uint64_t grp : 4; /**< POW Group */ 74210284Sjmallett uint64_t rs : 1; /**< Real short */ 75210284Sjmallett cvmx_pow_tag_type_t tt : 2; /**< POW Tag type */ 76210284Sjmallett uint64_t tag : 32; /**< POW 32 bit tag */ 77210284Sjmallett#else 78210284Sjmallett uint64_t tag : 32; 79210284Sjmallett cvmx_pow_tag_type_t tt : 2; 80210284Sjmallett uint64_t rs : 1; 81210284Sjmallett uint64_t grp : 4; 82210284Sjmallett uint64_t qos : 3; 83210284Sjmallett uint64_t fsz : 6; 84210284Sjmallett uint64_t dlengsz : 14; 85210284Sjmallett uint64_t g : 1; 86210284Sjmallett uint64_t r : 1; 87210284Sjmallett#endif 88210284Sjmallett } s; 89210284Sjmallett} cvmx_npi_inst_hdr_t; 90210284Sjmallett 91210284Sjmallett/** 92210284Sjmallett * PCI / PCIe packet data pointer formats 0-3 93210284Sjmallett */ 94210284Sjmalletttypedef union 95210284Sjmallett{ 96210284Sjmallett uint64_t dptr0; 97210284Sjmallett struct 98210284Sjmallett { 99210284Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 100210284Sjmallett uint64_t es : 2; /**< Endian swap mode */ 101210284Sjmallett uint64_t ns : 1; /**< No snoop */ 102210284Sjmallett uint64_t ro : 1; /**< Relaxed ordering */ 103210284Sjmallett uint64_t addr : 60; /**< PCI/PCIe address */ 104210284Sjmallett#else 105210284Sjmallett uint64_t addr : 60; 106210284Sjmallett uint64_t ro : 1; 107210284Sjmallett uint64_t ns : 1; 108210284Sjmallett uint64_t es : 2; 109210284Sjmallett#endif 110210284Sjmallett } dptr1; 111210284Sjmallett struct 112210284Sjmallett { 113210284Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 114210284Sjmallett uint64_t pm : 2; /**< Parse mode */ 115210284Sjmallett uint64_t sl : 7; /**< Skip length */ 116210284Sjmallett uint64_t addr : 55; /**< PCI/PCIe address */ 117210284Sjmallett#else 118210284Sjmallett uint64_t addr : 55; 119210284Sjmallett uint64_t sl : 7; 120210284Sjmallett uint64_t pm : 2; 121210284Sjmallett#endif 122210284Sjmallett } dptr2; 123210284Sjmallett struct 124210284Sjmallett { 125210284Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 126210284Sjmallett uint64_t es : 2; /**< Endian swap mode */ 127210284Sjmallett uint64_t ns : 1; /**< No snoop */ 128210284Sjmallett uint64_t ro : 1; /**< Relaxed ordering */ 129210284Sjmallett uint64_t pm : 2; /**< Parse mode */ 130210284Sjmallett uint64_t sl : 7; /**< Skip length */ 131210284Sjmallett uint64_t addr : 51; /**< PCI/PCIe address */ 132210284Sjmallett#else 133210284Sjmallett uint64_t addr : 51; 134210284Sjmallett uint64_t sl : 7; 135210284Sjmallett uint64_t pm : 2; 136210284Sjmallett uint64_t ro : 1; 137210284Sjmallett uint64_t ns : 1; 138210284Sjmallett uint64_t es : 2; 139210284Sjmallett#endif 140210284Sjmallett } dptr3; 141210284Sjmallett} cvmx_npi_dptr_t; 142210284Sjmallett 143210284Sjmallett#ifdef __cplusplus 144210284Sjmallett} 145210284Sjmallett#endif 146210284Sjmallett 147210284Sjmallett#endif /* __CVMX_NPI_H__ */ 148