1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian 18250003Sadrian /* Contains descriptor definitions for Osprey */ 19250003Sadrian 20250003Sadrian 21250003Sadrian#ifndef _ATH_AR9300_DESC_H_ 22250003Sadrian#define _ATH_AR9300_DESC_H_ 23250003Sadrian 24250008Sadrian#ifdef _KERNEL 25250008Sadrian#include "ar9300_freebsd_inc.h" 26250008Sadrian#endif 27250003Sadrian 28250003Sadrian/* Osprey Status Descriptor. */ 29250003Sadrianstruct ar9300_txs { 30250003Sadrian u_int32_t ds_info; 31250003Sadrian u_int32_t status1; 32250003Sadrian u_int32_t status2; 33250003Sadrian u_int32_t status3; 34250003Sadrian u_int32_t status4; 35250003Sadrian u_int32_t status5; 36250003Sadrian u_int32_t status6; 37250003Sadrian u_int32_t status7; 38250003Sadrian u_int32_t status8; 39250003Sadrian}; 40250003Sadrian 41250003Sadrianstruct ar9300_rxs { 42250003Sadrian u_int32_t ds_info; 43250003Sadrian u_int32_t status1; 44250003Sadrian u_int32_t status2; 45250003Sadrian u_int32_t status3; 46250003Sadrian u_int32_t status4; 47250003Sadrian u_int32_t status5; 48250003Sadrian u_int32_t status6; 49250003Sadrian u_int32_t status7; 50250003Sadrian u_int32_t status8; 51250003Sadrian u_int32_t status9; 52250003Sadrian u_int32_t status10; 53250003Sadrian u_int32_t status11; 54250003Sadrian}; 55250003Sadrian 56250003Sadrian/* Transmit Control Descriptor */ 57250003Sadrianstruct ar9300_txc { 58250003Sadrian u_int32_t ds_info; /* descriptor information */ 59250003Sadrian u_int32_t ds_link; /* link pointer */ 60250003Sadrian u_int32_t ds_data0; /* data pointer to 1st buffer */ 61250003Sadrian u_int32_t ds_ctl3; /* DMA control 3 */ 62250003Sadrian u_int32_t ds_data1; /* data pointer to 2nd buffer */ 63250003Sadrian u_int32_t ds_ctl5; /* DMA control 5 */ 64250003Sadrian u_int32_t ds_data2; /* data pointer to 3rd buffer */ 65250003Sadrian u_int32_t ds_ctl7; /* DMA control 7 */ 66250003Sadrian u_int32_t ds_data3; /* data pointer to 4th buffer */ 67250003Sadrian u_int32_t ds_ctl9; /* DMA control 9 */ 68250003Sadrian u_int32_t ds_ctl10; /* DMA control 10 */ 69250003Sadrian u_int32_t ds_ctl11; /* DMA control 11 */ 70250003Sadrian u_int32_t ds_ctl12; /* DMA control 12 */ 71250003Sadrian u_int32_t ds_ctl13; /* DMA control 13 */ 72250003Sadrian u_int32_t ds_ctl14; /* DMA control 14 */ 73250003Sadrian u_int32_t ds_ctl15; /* DMA control 15 */ 74250003Sadrian u_int32_t ds_ctl16; /* DMA control 16 */ 75250003Sadrian u_int32_t ds_ctl17; /* DMA control 17 */ 76250003Sadrian u_int32_t ds_ctl18; /* DMA control 18 */ 77250003Sadrian u_int32_t ds_ctl19; /* DMA control 19 */ 78250003Sadrian u_int32_t ds_ctl20; /* DMA control 20 */ 79250003Sadrian u_int32_t ds_ctl21; /* DMA control 21 */ 80250003Sadrian u_int32_t ds_ctl22; /* DMA control 22 */ 81250003Sadrian u_int32_t ds_pad[9]; /* pad to cache line (128 bytes/32 dwords) */ 82250003Sadrian}; 83250003Sadrian 84250003Sadrian 85250003Sadrian#define AR9300RXS(_rxs) ((struct ar9300_rxs *)(_rxs)) 86250003Sadrian#define AR9300TXS(_txs) ((struct ar9300_txs *)(_txs)) 87250003Sadrian#define AR9300TXC(_ds) ((struct ar9300_txc *)(_ds)) 88250003Sadrian 89250003Sadrian#define AR9300TXC_CONST(_ds) ((const struct ar9300_txc *)(_ds)) 90250003Sadrian 91250003Sadrian 92250003Sadrian/* ds_info */ 93250003Sadrian#define AR_desc_len 0x000000ff 94250003Sadrian#define AR_rx_priority 0x00000100 95250003Sadrian#define AR_tx_qcu_num 0x00000f00 96250003Sadrian#define AR_tx_qcu_num_S 8 97250003Sadrian#define AR_ctrl_stat 0x00004000 98250003Sadrian#define AR_ctrl_stat_S 14 99250003Sadrian#define AR_tx_rx_desc 0x00008000 100250003Sadrian#define AR_tx_rx_desc_S 15 101250003Sadrian#define AR_desc_id 0xffff0000 102250003Sadrian#define AR_desc_id_S 16 103250003Sadrian 104250003Sadrian/*********** 105250003Sadrian * TX Desc * 106250003Sadrian ***********/ 107250003Sadrian 108250003Sadrian/* ds_ctl3 */ 109250003Sadrian/* ds_ctl5 */ 110250003Sadrian/* ds_ctl7 */ 111250003Sadrian/* ds_ctl9 */ 112250003Sadrian#define AR_buf_len 0x0fff0000 113250003Sadrian#define AR_buf_len_S 16 114250003Sadrian 115250003Sadrian/* ds_ctl10 */ 116250003Sadrian#define AR_tx_desc_id 0xffff0000 117250003Sadrian#define AR_tx_desc_id_S 16 118250003Sadrian#define AR_tx_ptr_chk_sum 0x0000ffff 119250003Sadrian 120250003Sadrian/* ds_ctl11 */ 121250003Sadrian#define AR_frame_len 0x00000fff 122250003Sadrian#define AR_virt_more_frag 0x00001000 123250003Sadrian#define AR_tx_ctl_rsvd00 0x00002000 124250003Sadrian#define AR_low_rx_chain 0x00004000 125250003Sadrian#define AR_tx_clear_retry 0x00008000 126250003Sadrian#define AR_xmit_power0 0x003f0000 127250003Sadrian#define AR_xmit_power0_S 16 128250003Sadrian#define AR_rts_enable 0x00400000 129250003Sadrian#define AR_veol 0x00800000 130250003Sadrian#define AR_clr_dest_mask 0x01000000 131250003Sadrian#define AR_tx_bf0 0x02000000 132250003Sadrian#define AR_tx_bf1 0x04000000 133250003Sadrian#define AR_tx_bf2 0x08000000 134250003Sadrian#define AR_tx_bf3 0x10000000 135250003Sadrian#define AR_TxBfSteered 0x1e000000 /* for tx_bf*/ 136250003Sadrian#define AR_tx_intr_req 0x20000000 137250003Sadrian#define AR_dest_idx_valid 0x40000000 138250003Sadrian#define AR_cts_enable 0x80000000 139250003Sadrian 140250003Sadrian/* ds_ctl12 */ 141250003Sadrian#define AR_tx_ctl_rsvd02 0x000001ff 142250003Sadrian#define AR_paprd_chain_mask 0x00000e00 143250003Sadrian#define AR_paprd_chain_mask_S 9 144250003Sadrian#define AR_tx_more 0x00001000 145250003Sadrian#define AR_dest_idx 0x000fe000 146250003Sadrian#define AR_dest_idx_S 13 147250003Sadrian#define AR_frame_type 0x00f00000 148250003Sadrian#define AR_frame_type_S 20 149250003Sadrian#define AR_no_ack 0x01000000 150250003Sadrian#define AR_insert_ts 0x02000000 151250003Sadrian#define AR_corrupt_fcs 0x04000000 152250003Sadrian#define AR_ext_only 0x08000000 153250003Sadrian#define AR_ext_and_ctl 0x10000000 154250003Sadrian#define AR_more_aggr 0x20000000 155250003Sadrian#define AR_is_aggr 0x40000000 156250003Sadrian#define AR_more_rifs 0x80000000 157250003Sadrian#define AR_loc_mode 0x00000100 /* Positioning bit in TX desc */ 158250003Sadrian 159250003Sadrian/* ds_ctl13 */ 160250003Sadrian#define AR_burst_dur 0x00007fff 161250003Sadrian#define AR_burst_dur_S 0 162250003Sadrian#define AR_dur_update_ena 0x00008000 163250003Sadrian#define AR_xmit_data_tries0 0x000f0000 164250003Sadrian#define AR_xmit_data_tries0_S 16 165250003Sadrian#define AR_xmit_data_tries1 0x00f00000 166250003Sadrian#define AR_xmit_data_tries1_S 20 167250003Sadrian#define AR_xmit_data_tries2 0x0f000000 168250003Sadrian#define AR_xmit_data_tries2_S 24 169250003Sadrian#define AR_xmit_data_tries3 0xf0000000 170250003Sadrian#define AR_xmit_data_tries3_S 28 171250003Sadrian 172250003Sadrian/* ds_ctl14 */ 173250003Sadrian#define AR_xmit_rate0 0x000000ff 174250003Sadrian#define AR_xmit_rate0_S 0 175250003Sadrian#define AR_xmit_rate1 0x0000ff00 176250003Sadrian#define AR_xmit_rate1_S 8 177250003Sadrian#define AR_xmit_rate2 0x00ff0000 178250003Sadrian#define AR_xmit_rate2_S 16 179250003Sadrian#define AR_xmit_rate3 0xff000000 180250003Sadrian#define AR_xmit_rate3_S 24 181250003Sadrian 182250003Sadrian/* ds_ctl15 */ 183250003Sadrian#define AR_packet_dur0 0x00007fff 184250003Sadrian#define AR_packet_dur0_S 0 185250003Sadrian#define AR_rts_cts_qual0 0x00008000 186250003Sadrian#define AR_packet_dur1 0x7fff0000 187250003Sadrian#define AR_packet_dur1_S 16 188250003Sadrian#define AR_rts_cts_qual1 0x80000000 189250003Sadrian 190250003Sadrian/* ds_ctl16 */ 191250003Sadrian#define AR_packet_dur2 0x00007fff 192250003Sadrian#define AR_packet_dur2_S 0 193250003Sadrian#define AR_rts_cts_qual2 0x00008000 194250003Sadrian#define AR_packet_dur3 0x7fff0000 195250003Sadrian#define AR_packet_dur3_S 16 196250003Sadrian#define AR_rts_cts_qual3 0x80000000 197250003Sadrian 198250003Sadrian/* ds_ctl17 */ 199250003Sadrian#define AR_aggr_len 0x0000ffff 200250003Sadrian#define AR_aggr_len_S 0 201250003Sadrian#define AR_tx_ctl_rsvd60 0x00030000 202250003Sadrian#define AR_pad_delim 0x03fc0000 203250003Sadrian#define AR_pad_delim_S 18 204250003Sadrian#define AR_encr_type 0x1c000000 205250003Sadrian#define AR_encr_type_S 26 206250003Sadrian#define AR_tx_dc_ap_sta_sel 0x40000000 207250003Sadrian#define AR_tx_ctl_rsvd61 0xc0000000 208250003Sadrian#define AR_calibrating 0x40000000 209250003Sadrian#define AR_ldpc 0x80000000 210250003Sadrian 211250003Sadrian/* ds_ctl18 */ 212250003Sadrian#define AR_2040_0 0x00000001 213250003Sadrian#define AR_gi0 0x00000002 214250003Sadrian#define AR_chain_sel0 0x0000001c 215250003Sadrian#define AR_chain_sel0_S 2 216250003Sadrian#define AR_2040_1 0x00000020 217250003Sadrian#define AR_gi1 0x00000040 218250003Sadrian#define AR_chain_sel1 0x00000380 219250003Sadrian#define AR_chain_sel1_S 7 220250003Sadrian#define AR_2040_2 0x00000400 221250003Sadrian#define AR_gi2 0x00000800 222250003Sadrian#define AR_chain_sel2 0x00007000 223250003Sadrian#define AR_chain_sel2_S 12 224250003Sadrian#define AR_2040_3 0x00008000 225250003Sadrian#define AR_gi3 0x00010000 226250003Sadrian#define AR_chain_sel3 0x000e0000 227250003Sadrian#define AR_chain_sel3_S 17 228250003Sadrian#define AR_rts_cts_rate 0x0ff00000 229250003Sadrian#define AR_rts_cts_rate_S 20 230250003Sadrian#define AR_stbc0 0x10000000 231250003Sadrian#define AR_stbc1 0x20000000 232250003Sadrian#define AR_stbc2 0x40000000 233250003Sadrian#define AR_stbc3 0x80000000 234250003Sadrian 235250003Sadrian/* ds_ctl19 */ 236250003Sadrian#define AR_tx_ant0 0x00ffffff 237250003Sadrian#define AR_tx_ant_sel0 0x80000000 238250003Sadrian#define AR_RTS_HTC_TRQ 0x10000000 /* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/ 239250003Sadrian#define AR_not_sounding 0x20000000 240250003Sadrian#define AR_ness 0xc0000000 241250003Sadrian#define AR_ness_S 30 242250003Sadrian 243250003Sadrian/* ds_ctl20 */ 244250003Sadrian#define AR_tx_ant1 0x00ffffff 245250003Sadrian#define AR_xmit_power1 0x3f000000 246250003Sadrian#define AR_xmit_power1_S 24 247250003Sadrian#define AR_tx_ant_sel1 0x80000000 248250003Sadrian#define AR_ness1 0xc0000000 249250003Sadrian#define AR_ness1_S 30 250250003Sadrian 251250003Sadrian/* ds_ctl21 */ 252250003Sadrian#define AR_tx_ant2 0x00ffffff 253250003Sadrian#define AR_xmit_power2 0x3f000000 254250003Sadrian#define AR_xmit_power2_S 24 255250003Sadrian#define AR_tx_ant_sel2 0x80000000 256250003Sadrian#define AR_ness2 0xc0000000 257250003Sadrian#define AR_ness2_S 30 258250003Sadrian 259250003Sadrian/* ds_ctl22 */ 260250003Sadrian#define AR_tx_ant3 0x00ffffff 261250003Sadrian#define AR_xmit_power3 0x3f000000 262250003Sadrian#define AR_xmit_power3_S 24 263250003Sadrian#define AR_tx_ant_sel3 0x80000000 264250003Sadrian#define AR_ness3 0xc0000000 265250003Sadrian#define AR_ness3_S 30 266250003Sadrian 267250003Sadrian/************* 268250003Sadrian * TX Status * 269250003Sadrian *************/ 270250003Sadrian 271250003Sadrian/* ds_status1 */ 272250003Sadrian#define AR_tx_status_rsvd 0x0000ffff 273250003Sadrian 274250003Sadrian/* ds_status2 */ 275250003Sadrian#define AR_tx_rssi_ant00 0x000000ff 276250003Sadrian#define AR_tx_rssi_ant00_S 0 277250003Sadrian#define AR_tx_rssi_ant01 0x0000ff00 278250003Sadrian#define AR_tx_rssi_ant01_S 8 279250003Sadrian#define AR_tx_rssi_ant02 0x00ff0000 280250003Sadrian#define AR_tx_rssi_ant02_S 16 281250003Sadrian#define AR_tx_status_rsvd00 0x3f000000 282250003Sadrian#define AR_tx_ba_status 0x40000000 283250003Sadrian#define AR_tx_status_rsvd01 0x80000000 284250003Sadrian 285250003Sadrian/* ds_status3 */ 286250003Sadrian#define AR_frm_xmit_ok 0x00000001 287250003Sadrian#define AR_excessive_retries 0x00000002 288250003Sadrian#define AR_fifounderrun 0x00000004 289250003Sadrian#define AR_filtered 0x00000008 290250003Sadrian#define AR_rts_fail_cnt 0x000000f0 291250003Sadrian#define AR_rts_fail_cnt_S 4 292250003Sadrian#define AR_data_fail_cnt 0x00000f00 293250003Sadrian#define AR_data_fail_cnt_S 8 294250003Sadrian#define AR_virt_retry_cnt 0x0000f000 295250003Sadrian#define AR_virt_retry_cnt_S 12 296250003Sadrian#define AR_tx_delim_underrun 0x00010000 297250003Sadrian#define AR_tx_data_underrun 0x00020000 298250003Sadrian#define AR_desc_cfg_err 0x00040000 299250003Sadrian#define AR_tx_timer_expired 0x00080000 300250003Sadrian#define AR_tx_status_rsvd10 0xfff00000 301250003Sadrian 302250003Sadrian/* ds_status7 */ 303250003Sadrian#define AR_tx_rssi_ant10 0x000000ff 304250003Sadrian#define AR_tx_rssi_ant10_S 0 305250003Sadrian#define AR_tx_rssi_ant11 0x0000ff00 306250003Sadrian#define AR_tx_rssi_ant11_S 8 307250003Sadrian#define AR_tx_rssi_ant12 0x00ff0000 308250003Sadrian#define AR_tx_rssi_ant12_S 16 309250003Sadrian#define AR_tx_rssi_combined 0xff000000 310250003Sadrian#define AR_tx_rssi_combined_S 24 311250003Sadrian 312250003Sadrian/* ds_status8 */ 313250003Sadrian#define AR_tx_done 0x00000001 314250003Sadrian#define AR_seq_num 0x00001ffe 315250003Sadrian#define AR_seq_num_S 1 316250003Sadrian#define AR_tx_status_rsvd80 0x0001e000 317250003Sadrian#define AR_tx_op_exceeded 0x00020000 318250003Sadrian#define AR_tx_status_rsvd81 0x001c0000 319250003Sadrian#define AR_TXBFStatus 0x001c0000 320250003Sadrian#define AR_TXBFStatus_S 18 321250003Sadrian#define AR_tx_bf_bw_mismatch 0x00040000 322250003Sadrian#define AR_tx_bf_stream_miss 0x00080000 323250003Sadrian#define AR_final_tx_idx 0x00600000 324250003Sadrian#define AR_final_tx_idx_S 21 325250003Sadrian#define AR_tx_bf_dest_miss 0x00800000 326250003Sadrian#define AR_tx_bf_expired 0x01000000 327250003Sadrian#define AR_power_mgmt 0x02000000 328250003Sadrian#define AR_tx_status_rsvd83 0x0c000000 329250003Sadrian#define AR_tx_tid 0xf0000000 330250003Sadrian#define AR_tx_tid_S 28 331250003Sadrian#define AR_tx_fast_ts 0x08000000 /* 27th bit for locationing */ 332250003Sadrian 333250003Sadrian 334250003Sadrian/************* 335250003Sadrian * Rx Status * 336250003Sadrian *************/ 337250003Sadrian 338250003Sadrian/* ds_status1 */ 339250003Sadrian#define AR_rx_rssi_ant00 0x000000ff 340250003Sadrian#define AR_rx_rssi_ant00_S 0 341250003Sadrian#define AR_rx_rssi_ant01 0x0000ff00 342250003Sadrian#define AR_rx_rssi_ant01_S 8 343250003Sadrian#define AR_rx_rssi_ant02 0x00ff0000 344250003Sadrian#define AR_rx_rssi_ant02_S 16 345250003Sadrian#define AR_rx_rate 0xff000000 346250003Sadrian#define AR_rx_rate_S 24 347250003Sadrian 348250003Sadrian/* ds_status2 */ 349250003Sadrian#define AR_data_len 0x00000fff 350250003Sadrian#define AR_rx_more 0x00001000 351250003Sadrian#define AR_num_delim 0x003fc000 352250003Sadrian#define AR_num_delim_S 14 353250003Sadrian#define AR_hw_upload_data 0x00400000 354250003Sadrian#define AR_hw_upload_data_S 22 355250003Sadrian#define AR_rx_status_rsvd10 0xff800000 356250003Sadrian 357250003Sadrian 358250003Sadrian/* ds_status4 */ 359250003Sadrian#define AR_gi 0x00000001 360250003Sadrian#define AR_2040 0x00000002 361250003Sadrian#define AR_parallel40 0x00000004 362250003Sadrian#define AR_parallel40_S 2 363250003Sadrian#define AR_rx_stbc 0x00000008 364250003Sadrian#define AR_rx_not_sounding 0x00000010 365250003Sadrian#define AR_rx_ness 0x00000060 366250003Sadrian#define AR_rx_ness_S 5 367250003Sadrian#define AR_hw_upload_data_valid 0x00000080 368250003Sadrian#define AR_hw_upload_data_valid_S 7 369250003Sadrian#define AR_rx_antenna 0xffffff00 370250003Sadrian#define AR_rx_antenna_S 8 371250003Sadrian 372250003Sadrian/* ds_status5 */ 373250003Sadrian#define AR_rx_rssi_ant10 0x000000ff 374250003Sadrian#define AR_rx_rssi_ant10_S 0 375250003Sadrian#define AR_rx_rssi_ant11 0x0000ff00 376250003Sadrian#define AR_rx_rssi_ant11_S 8 377250003Sadrian#define AR_rx_rssi_ant12 0x00ff0000 378250003Sadrian#define AR_rx_rssi_ant12_S 16 379250003Sadrian#define AR_rx_rssi_combined 0xff000000 380250003Sadrian#define AR_rx_rssi_combined_S 24 381250003Sadrian 382250003Sadrian/* ds_status6 */ 383250003Sadrian#define AR_rx_evm0 status6 384250003Sadrian 385250003Sadrian/* ds_status7 */ 386250003Sadrian#define AR_rx_evm1 status7 387250003Sadrian 388250003Sadrian/* ds_status8 */ 389250003Sadrian#define AR_rx_evm2 status8 390250003Sadrian 391250003Sadrian/* ds_status9 */ 392250003Sadrian#define AR_rx_evm3 status9 393250003Sadrian 394250003Sadrian/* ds_status11 */ 395250003Sadrian#define AR_rx_done 0x00000001 396250003Sadrian#define AR_rx_frame_ok 0x00000002 397250003Sadrian#define AR_crc_err 0x00000004 398250003Sadrian#define AR_decrypt_crc_err 0x00000008 399250003Sadrian#define AR_phyerr 0x00000010 400250003Sadrian#define AR_michael_err 0x00000020 401250003Sadrian#define AR_pre_delim_crc_err 0x00000040 402250003Sadrian#define AR_apsd_trig 0x00000080 403250003Sadrian#define AR_rx_key_idx_valid 0x00000100 404250003Sadrian#define AR_key_idx 0x0000fe00 405250003Sadrian#define AR_key_idx_S 9 406250003Sadrian#define AR_phy_err_code 0x0000ff00 407250003Sadrian#define AR_phy_err_code_S 8 408250003Sadrian#define AR_rx_more_aggr 0x00010000 409250003Sadrian#define AR_rx_aggr 0x00020000 410250003Sadrian#define AR_post_delim_crc_err 0x00040000 411250003Sadrian#define AR_rx_status_rsvd71 0x01f80000 412250003Sadrian#define AR_hw_upload_data_type 0x06000000 413250003Sadrian#define AR_hw_upload_data_type_S 25 414250003Sadrian#define AR_position_bit 0x08000000 /* positioning bit */ 415250003Sadrian#define AR_hi_rx_chain 0x10000000 416250003Sadrian#define AR_rx_first_aggr 0x20000000 417250003Sadrian#define AR_decrypt_busy_err 0x40000000 418250003Sadrian#define AR_key_miss 0x80000000 419250003Sadrian 420250003Sadrian#define TXCTL_OFFSET(ah) 11 421250003Sadrian#define TXCTL_NUMWORDS(ah) 12 422250003Sadrian#define TXSTATUS_OFFSET(ah) 2 423250003Sadrian#define TXSTATUS_NUMWORDS(ah) 7 424250003Sadrian 425250003Sadrian#define RXCTL_OFFSET(ah) 0 426250003Sadrian#define RXCTL_NUMWORDS(ah) 0 427250003Sadrian#define RXSTATUS_OFFSET(ah) 1 428250003Sadrian#define RXSTATUS_NUMWORDS(ah) 11 429250003Sadrian 430250003Sadrian 431250003Sadrian#define TXC_INFO(_qcu) (ATHEROS_VENDOR_ID << AR_desc_id_S) \ 432250003Sadrian | (1 << AR_tx_rx_desc_S) \ 433250003Sadrian | (1 << AR_ctrl_stat_S) \ 434250003Sadrian | (_qcu << AR_tx_qcu_num_S) \ 435250003Sadrian | (0x17) 436250003Sadrian 437250003Sadrian#define VALID_KEY_TYPES \ 438250003Sadrian ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\ 439250003Sadrian (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP)) 440250003Sadrian#define is_valid_key_type(_t) ((1 << (_t)) & VALID_KEY_TYPES) 441250003Sadrian 442250003Sadrian#define set_11n_tries(_series, _index) \ 443250003Sadrian (SM((_series)[_index].Tries, AR_xmit_data_tries##_index)) 444250003Sadrian 445250003Sadrian#define set_11n_rate(_series, _index) \ 446250003Sadrian (SM((_series)[_index].Rate, AR_xmit_rate##_index)) 447250003Sadrian 448250003Sadrian#define set_11n_pkt_dur_rts_cts(_series, _index) \ 449250003Sadrian (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\ 450250003Sadrian ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ 451250003Sadrian AR_rts_cts_qual##_index : 0)) 452250003Sadrian 453250003Sadrian#define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88)) 454250003Sadrian 455250003Sadrian#define set_11n_tx_bf_ldpc( _series) \ 456250003Sadrian ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \ 457250003Sadrian (!(_series)[1].Tries)) && (not_two_stream_rate((_series)[2].Rate)||(!(_series)[2].Tries)) \ 458250003Sadrian && (not_two_stream_rate((_series)[3].Rate)||(!(_series)[3].Tries)))) \ 459250003Sadrian ? AR_ldpc : 0) 460250003Sadrian 461250003Sadrian#define set_11n_rate_flags(_series, _index) \ 462250003Sadrian ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ 463250003Sadrian |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \ 464250003Sadrian |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \ 465250008Sadrian |SM((_series)[_index].ChSel, AR_chain_sel##_index) 466250003Sadrian 467250003Sadrian#define set_11n_tx_power(_index, _txpower) \ 468250003Sadrian SM(_txpower, AR_xmit_power##_index) 469250003Sadrian 470250003Sadrian#define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7) 471250003Sadrian/* 472250003Sadrian * Descriptor Access Functions 473250003Sadrian */ 474250003Sadrian/* XXX valid Tx rates will change for 3 stream support */ 475250003Sadrian#define VALID_PKT_TYPES \ 476250003Sadrian ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\ 477250003Sadrian (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\ 478250003Sadrian (1<<HAL_PKT_TYPE_BEACON)) 479250003Sadrian#define is_valid_pkt_type(_t) ((1<<(_t)) & VALID_PKT_TYPES) 480250003Sadrian#define VALID_TX_RATES \ 481250003Sadrian ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\ 482250003Sadrian (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\ 483250003Sadrian (1<<0x1d)|(1<<0x18)|(1<<0x1c)) 484250003Sadrian#define is_valid_tx_rate(_r) ((1<<(_r)) & VALID_TX_RATES) 485250003Sadrian 486250008Sadrian 487250008Sadrian#ifdef _KERNEL 488250003Sadrian /* TX common functions */ 489250003Sadrian 490250003Sadrianextern HAL_BOOL ar9300_update_tx_trig_level(struct ath_hal *, 491250003Sadrian HAL_BOOL IncTrigLevel); 492250003Sadrianextern u_int16_t ar9300_get_tx_trig_level(struct ath_hal *); 493250003Sadrianextern HAL_BOOL ar9300_set_tx_queue_props(struct ath_hal *ah, int q, 494250003Sadrian const HAL_TXQ_INFO *q_info); 495250003Sadrianextern HAL_BOOL ar9300_get_tx_queue_props(struct ath_hal *ah, int q, 496250003Sadrian HAL_TXQ_INFO *q_info); 497250003Sadrianextern int ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 498250003Sadrian const HAL_TXQ_INFO *q_info); 499250003Sadrianextern HAL_BOOL ar9300_release_tx_queue(struct ath_hal *ah, u_int q); 500250003Sadrianextern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q); 501250003Sadrianextern u_int32_t ar9300_get_tx_dp(struct ath_hal *ah, u_int q); 502250003Sadrianextern HAL_BOOL ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp); 503250003Sadrianextern HAL_BOOL ar9300_start_tx_dma(struct ath_hal *ah, u_int q); 504250003Sadrianextern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q); 505250003Sadrianextern HAL_BOOL ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout); 506250003Sadrianextern HAL_BOOL ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout); 507250003Sadrianextern HAL_BOOL ar9300_abort_tx_dma(struct ath_hal *ah); 508250003Sadrianextern void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *); 509250003Sadrian 510250003Sadrianextern void ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds); 511250008Sadrianextern HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, HAL_DMA_ADDR *buf_addr, 512250003Sadrian u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg, 513250003Sadrian HAL_BOOL last_seg, const void *ds0); 514250003Sadrianextern void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link); 515250003Sadrianextern void ar9300_get_desc_link_ptr(struct ath_hal *, void *ds, u_int32_t **link); 516250003Sadrianextern void ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds); 517250003Sadrian#ifdef ATH_SWRETRY 518250003Sadrianextern void ar9300_clear_dest_mask(struct ath_hal *ah, void *ds); 519250003Sadrian#endif 520250003Sadrianextern HAL_STATUS ar9300_proc_tx_desc(struct ath_hal *ah, void *); 521250003Sadrianextern void ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *); 522250003Sadrianextern void ar9300_get_tx_rate_code(struct ath_hal *ah, void *, struct ath_tx_status *); 523250003Sadrianextern u_int32_t ar9300_calc_tx_airtime(struct ath_hal *ah, void *, struct ath_tx_status *, 524250003Sadrian HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes); 525250003Sadrianextern void ar9300_setup_tx_status_ring(struct ath_hal *ah, void *, u_int32_t , u_int16_t); 526250003Sadrianextern void ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num); 527250003SadrianHAL_STATUS ar9300_is_tx_done(struct ath_hal *ah); 528250003Sadrianextern void ar9300_set_11n_tx_desc(struct ath_hal *ah, void *ds, 529250003Sadrian u_int pkt_len, HAL_PKT_TYPE type, u_int tx_power, 530250003Sadrian u_int key_ix, HAL_KEY_TYPE key_type, u_int flags); 531250003Sadrianextern void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask); 532250003Sadrianextern void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit); 533250003Sadrian 534250003Sadrian/* for tx_bf*/ 535250003Sadrian#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 536250003Sadrian/* for tx_bf*/ 537250003Sadrian 538250003Sadrianextern void ar9300_set_11n_rate_scenario(struct ath_hal *ah, void *ds, 539250003Sadrian void *lastds, u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration, HAL_11N_RATE_SERIES series[], 540250003Sadrian u_int nseries, u_int flags, u_int32_t smartAntenna); 541250008Sadrianextern void ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 542250008Sadrian u_int aggr_len, u_int num_delims); 543250008Sadrianextern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 544250003Sadrian u_int num_delims); 545250008Sadrianextern void ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); 546250008Sadrianextern void ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds); 547250008Sadrianextern void ar9300_set_11n_burst_duration(struct ath_hal *ah, 548250008Sadrian struct ath_desc *ds, u_int burst_duration); 549250003Sadrianextern void ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds); 550250003Sadrianextern void ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds); 551250003Sadrianextern void ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds); 552250003Sadrianextern void ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds); 553250008Sadrianextern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, 554250008Sadrian struct ath_desc *ds, u_int vmf); 555250003Sadrian#ifdef AH_PRIVATE_DIAG 556250003Sadrianextern void ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode); 557250003Sadrian#endif 558250003Sadrian 559250003Sadrian /* RX common functions */ 560250003Sadrian 561250003Sadrianextern u_int32_t ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype); 562250003Sadrianextern void ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype); 563250003Sadrianextern void ar9300_enable_receive(struct ath_hal *ah); 564250003Sadrianextern HAL_BOOL ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout); 565250003Sadrianextern void ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning); 566250003Sadrianextern void ar9300_stop_pcu_receive(struct ath_hal *ah); 567250003Sadrianextern void ar9300_set_multicast_filter(struct ath_hal *ah, 568250003Sadrian u_int32_t filter0, u_int32_t filter1); 569250003Sadrianextern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah); 570250003Sadrianextern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits); 571250003Sadrianextern HAL_BOOL ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL, HAL_BOOL); 572250008Sadrianextern HAL_BOOL ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL); 573250003Sadrian 574250003Sadrianextern HAL_STATUS ar9300_proc_rx_desc(struct ath_hal *ah, 575250003Sadrian struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *); 576250003Sadrianextern HAL_STATUS ar9300_get_rx_key_idx(struct ath_hal *ah, 577250003Sadrian struct ath_desc *, u_int8_t *, u_int8_t *); 578250003Sadrianextern HAL_STATUS ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *, 579250003Sadrian u_int32_t, struct ath_desc *, struct ath_rx_status *, void *); 580250003Sadrian 581250003Sadrianextern void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable); 582250003Sadrianextern void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 583250003Sadrianextern void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t ); 584250003Sadrian 585250003Sadrian#endif 586250003Sadrian 587250008Sadrian#endif /* _ATH_AR9300_DESC_H_ */ 588