1259267Sbz/*- 2259267Sbz * Copyright (c) 2012-2013 Robert N. M. Watson 3259267Sbz * Copyright (c) 2013 SRI International 4270061Sbz * Copyright (c) 2013-2014 Bjoern A. Zeeb 5259267Sbz * All rights reserved. 6259267Sbz * 7259267Sbz * This software was developed by SRI International and the University of 8259267Sbz * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 9259267Sbz * ("CTSRD"), as part of the DARPA CRASH research programme. 10259267Sbz * 11259267Sbz * This software was developed by SRI International and the University of 12259267Sbz * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 13259267Sbz * ("MRC2"), as part of the DARPA MRC research programme. 14259267Sbz * 15259267Sbz * Redistribution and use in source and binary forms, with or without 16259267Sbz * modification, are permitted provided that the following conditions 17259267Sbz * are met: 18259267Sbz * 1. Redistributions of source code must retain the above copyright 19259267Sbz * notice, this list of conditions and the following disclaimer. 20259267Sbz * 2. Redistributions in binary form must reproduce the above copyright 21259267Sbz * notice, this list of conditions and the following disclaimer in the 22259267Sbz * documentation and/or other materials provided with the distribution. 23259267Sbz * 24259267Sbz * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25259267Sbz * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26259267Sbz * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27259267Sbz * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28259267Sbz * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29259267Sbz * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30259267Sbz * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31259267Sbz * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32259267Sbz * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33259267Sbz * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34259267Sbz * SUCH DAMAGE. 35259267Sbz * 36259267Sbz * $FreeBSD$ 37259267Sbz */ 38259267Sbz 39259267Sbz/dts-v1/; 40259267Sbz 41259267Sbz/* 42259267Sbz * Device names here have been largely made up on the spot, especially for the 43259267Sbz * "compatible" strings, and might want to be revised. 44259267Sbz */ 45259267Sbz 46259267Sbz/ { 47259267Sbz model = "SRI/Cambridge Beri (NetFPGA)"; 48259267Sbz compatible = "sri-cambridge,beri-netfpga"; 49259267Sbz #address-cells = <1>; 50259267Sbz #size-cells = <1>; 51259267Sbz 52259267Sbz cpus { 53259267Sbz #address-cells = <1>; 54259267Sbz #size-cells = <1>; 55259267Sbz 56259267Sbz /* 57259267Sbz * Secondary CPUs all start disabled and use the 58259267Sbz * spin-table enable method. cpu-release-addr must be 59259267Sbz * specified for each cpu other than cpu@0. Values of 60259267Sbz * cpu-release-addr grow down from 0x100000 (kernel). 61259267Sbz */ 62259267Sbz status = "disabled"; 63259267Sbz enable-method = "spin-table"; 64259267Sbz 65259267Sbz cpu@0 { 66259267Sbz device-type = "cpu"; 67259267Sbz compatible = "sri-cambridge,beri"; 68259267Sbz 69266251Sian reg = <0 1>; 70259267Sbz status = "okay"; 71259267Sbz }; 72259267Sbz 73259267Sbz/* 74259267Sbz cpu@1 { 75259267Sbz device-type = "cpu"; 76259267Sbz compatible = "sri-cambridge,beri"; 77259267Sbz 78266251Sian reg = <1 1>; 79259267Sbz // XXX: should we need cached prefix? 80259267Sbz cpu-release-addr = <0xffffffff 0x800fffe0>; 81259267Sbz }; 82259267Sbz*/ 83259267Sbz }; 84259267Sbz 85259267Sbz soc { 86259267Sbz #address-cells = <1>; 87259267Sbz #size-cells = <1>; 88259267Sbz #interrupt-cells = <1>; 89259267Sbz 90259267Sbz /* 91259267Sbz * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so 92259267Sbz * we use mips4k coprocessor 0 interrupt management directly. 93259267Sbz */ 94259267Sbz compatible = "simple-bus", "mips,mips4k"; 95259267Sbz ranges = <>; 96259267Sbz 97259267Sbz memory { 98259267Sbz device_type = "memory"; 99259267Sbz reg = <0x0 0x0FFFFFFF>; // ~256M at 0x0 100259267Sbz }; 101259267Sbz 102259267Sbz beripic: beripic@7f804000 { 103259267Sbz compatible = "sri-cambridge,beri-pic"; 104259267Sbz interrupt-controller; 105259267Sbz #address-cells = <0>; 106259267Sbz #interrupt-cells = <1>; 107259267Sbz reg = <0x7f804000 0x400 108259267Sbz 0x7f806000 0x10 109259267Sbz 0x7f806080 0x10 110259267Sbz 0x7f806100 0x10>; 111259267Sbz interrupts = <0 1 2 3 4>; 112259267Sbz hard-interrupt-sources = <64>; 113259267Sbz soft-interrupt-sources = <64>; 114259267Sbz }; 115259267Sbz 116270060Sbz serial0: serial@7f000000 { 117270060Sbz compatible = "altera,jtag_uart-11_0"; 118270060Sbz reg = <0x7f000000 0x40>; 119270060Sbz interrupts = <0>; 120270060Sbz interrupt-parent = <&beripic>; 121270060Sbz }; 122270060Sbz 123270060Sbz/* 124259267Sbz serial0: serial@7f002100 { 125259267Sbz compatible = "ns16550"; 126259267Sbz reg = <0x7f002100 0x20>; 127259267Sbz reg-shift = <2>; 128259267Sbz clock-frequency = <100000000>; 129259267Sbz interrupts = <8>; 130259267Sbz interrupt-parent = <&beripic>; 131259267Sbz }; 132270060Sbz*/ 133270061Sbz 134270061Sbz ethernet@7f005000 { 135270061Sbz compatible = "netfpag10g,nf10bmac"; 136270061Sbz // LOOP, TX, RX, INTR 137270061Sbz reg = <0x7f005000 0x20 138270061Sbz 0x7f005020 0x30 139270061Sbz 0x7f005050 0x30 140270061Sbz 0x7f005100 0x10>; 141270061Sbz // RX 142270061Sbz interrupts = <1>; 143270061Sbz interrupt-parent = <&beripic>; 144270061Sbz }; 145259267Sbz }; 146259267Sbz 147259267Sbz aliases { 148259267Sbz serial0 = &serial0; 149259267Sbz }; 150259267Sbz 151259267Sbz chosen { 152259267Sbz stdin = "serial0"; 153259267Sbz stdout = "serial0"; 154259267Sbz bootargs = "-v"; 155259267Sbz }; 156259267Sbz}; 157