db88f6281.dts revision 235609
1208561Sraj/* 2208561Sraj * Copyright (c) 2009-2010 The FreeBSD Foundation 3208561Sraj * All rights reserved. 4208561Sraj * 5208561Sraj * This software was developed by Semihalf under sponsorship from 6208561Sraj * the FreeBSD Foundation. 7208561Sraj * 8208561Sraj * Redistribution and use in source and binary forms, with or without 9208561Sraj * modification, are permitted provided that the following conditions 10208561Sraj * are met: 11208561Sraj * 1. Redistributions of source code must retain the above copyright 12208561Sraj * notice, this list of conditions and the following disclaimer. 13208561Sraj * 2. Redistributions in binary form must reproduce the above copyright 14208561Sraj * notice, this list of conditions and the following disclaimer in the 15208561Sraj * documentation and/or other materials provided with the distribution. 16208561Sraj * 17208561Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18208561Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19208561Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20208561Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21208561Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22208561Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23208561Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24208561Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25208561Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26208561Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27208561Sraj * SUCH DAMAGE. 28208561Sraj * 29208561Sraj * Marvell DB-88F6281 Device Tree Source. 30208561Sraj * 31208561Sraj * $FreeBSD: head/sys/boot/fdt/dts/db88f6281.dts 235609 2012-05-18 14:41:14Z gber $ 32208561Sraj */ 33208561Sraj 34208561Sraj/dts-v1/; 35208561Sraj 36208561Sraj/ { 37208561Sraj model = "mrvl,DB-88F6281"; 38208561Sraj compatible = "DB-88F6281-BP", "DB-88F6281-BP-A"; 39208561Sraj #address-cells = <1>; 40208561Sraj #size-cells = <1>; 41208561Sraj 42208561Sraj aliases { 43208561Sraj ethernet0 = &enet0; 44208561Sraj mpp = &MPP; 45208561Sraj pci0 = &pci0; 46208561Sraj serial0 = &serial0; 47208561Sraj serial1 = &serial1; 48208561Sraj soc = &SOC; 49208561Sraj sram = &SRAM; 50208561Sraj }; 51208561Sraj 52208561Sraj cpus { 53208561Sraj #address-cells = <1>; 54208561Sraj #size-cells = <0>; 55208561Sraj 56208561Sraj cpu@0 { 57208561Sraj device_type = "cpu"; 58208561Sraj compatible = "ARM,88FR131"; 59208561Sraj reg = <0x0>; 60208561Sraj d-cache-line-size = <32>; // 32 bytes 61208561Sraj i-cache-line-size = <32>; // 32 bytes 62208561Sraj d-cache-size = <0x4000>; // L1, 16K 63208561Sraj i-cache-size = <0x4000>; // L1, 16K 64208561Sraj timebase-frequency = <0>; 65208561Sraj bus-frequency = <0>; 66208561Sraj clock-frequency = <0>; 67208561Sraj }; 68208561Sraj }; 69208561Sraj 70208561Sraj memory { 71208561Sraj device_type = "memory"; 72208561Sraj reg = <0x0 0x20000000>; // 512M at 0x0 73208561Sraj }; 74208561Sraj 75235609Sgber localbus@0 { 76208561Sraj #address-cells = <2>; 77208561Sraj #size-cells = <1>; 78208561Sraj compatible = "mrvl,lbc"; 79235609Sgber bank-count = <3>; 80208561Sraj 81208561Sraj /* This reflects CPU decode windows setup. */ 82235609Sgber ranges = <0x0 0x2f 0xf9300000 0x00100000>; 83208561Sraj 84235609Sgber nand@0,0 { 85208561Sraj #address-cells = <1>; 86208561Sraj #size-cells = <1>; 87235609Sgber compatible = "mrvl,nfc"; 88208561Sraj reg = <0x0 0x0 0x00100000>; 89208561Sraj bank-width = <2>; 90208561Sraj device-width = <1>; 91208561Sraj 92208561Sraj 93208561Sraj }; 94208561Sraj }; 95208561Sraj 96208561Sraj SOC: soc88f6281@f1000000 { 97208561Sraj #address-cells = <1>; 98208561Sraj #size-cells = <1>; 99208561Sraj compatible = "simple-bus"; 100208561Sraj ranges = <0x0 0xf1000000 0x00100000>; 101208561Sraj bus-frequency = <0>; 102208561Sraj 103208561Sraj PIC: pic@20200 { 104208561Sraj interrupt-controller; 105208561Sraj #address-cells = <0>; 106208561Sraj #interrupt-cells = <1>; 107208561Sraj reg = <0x20200 0x3c>; 108208561Sraj compatible = "mrvl,pic"; 109208561Sraj }; 110208561Sraj 111208561Sraj timer@20300 { 112208561Sraj compatible = "mrvl,timer"; 113208561Sraj reg = <0x20300 0x30>; 114208561Sraj interrupts = <1>; 115208561Sraj interrupt-parent = <&PIC>; 116208561Sraj mrvl,has-wdt; 117208561Sraj }; 118208561Sraj 119208561Sraj MPP: mpp@10000 { 120208561Sraj #pin-cells = <2>; 121208561Sraj compatible = "mrvl,mpp"; 122208561Sraj reg = <0x10000 0x34>; 123208561Sraj pin-count = <50>; 124208561Sraj pin-map = < 125208561Sraj 0 1 /* MPP[0]: NF_IO[2] */ 126208561Sraj 1 1 /* MPP[1]: NF_IO[3] */ 127208561Sraj 2 1 /* MPP[2]: NF_IO[4] */ 128208561Sraj 3 1 /* MPP[3]: NF_IO[5] */ 129208561Sraj 4 1 /* MPP[4]: NF_IO[6] */ 130208561Sraj 5 1 /* MPP[5]: NF_IO[7] */ 131208561Sraj 6 1 /* MPP[6]: SYSRST_OUTn */ 132208561Sraj 7 2 /* MPP[7]: SPI_SCn */ 133208561Sraj 8 1 /* MPP[8]: TW_SDA */ 134208561Sraj 9 1 /* MPP[9]: TW_SCK */ 135208561Sraj 10 3 /* MPP[10]: UA0_TXD */ 136208561Sraj 11 3 /* MPP[11]: UA0_RXD */ 137208561Sraj 12 1 /* MPP[12]: SD_CLK */ 138208561Sraj 13 1 /* MPP[13]: SD_CMD */ 139208561Sraj 14 1 /* MPP[14]: SD_D[0] */ 140208561Sraj 15 1 /* MPP[15]: SD_D[1] */ 141208561Sraj 16 1 /* MPP[16]: SD_D[2] */ 142208561Sraj 17 1 /* MPP[17]: SD_D[3] */ 143208561Sraj 18 1 /* MPP[18]: NF_IO[0] */ 144208561Sraj 19 1 /* MPP[19]: NF_IO[1] */ 145208561Sraj 20 5 /* MPP[20]: SATA1_AC */ 146208561Sraj 21 5 >; /* MPP[21]: SATA0_AC */ 147208561Sraj }; 148208561Sraj 149208561Sraj GPIO: gpio@10100 { 150208561Sraj #gpio-cells = <3>; 151208561Sraj compatible = "mrvl,gpio"; 152208561Sraj reg = <0x10100 0x20>; 153208561Sraj gpio-controller; 154208561Sraj interrupts = <35 36 37 38 39 40 41>; 155208561Sraj interrupt-parent = <&PIC>; 156208561Sraj }; 157208561Sraj 158208561Sraj rtc@10300 { 159208561Sraj compatible = "mrvl,rtc"; 160208561Sraj reg = <0x10300 0x08>; 161208561Sraj }; 162208561Sraj 163208561Sraj twsi@11000 { 164208561Sraj #address-cells = <1>; 165208561Sraj #size-cells = <0>; 166208561Sraj compatible = "mrvl,twsi"; 167208561Sraj reg = <0x11000 0x20>; 168208561Sraj interrupts = <43>; 169208561Sraj interrupt-parent = <&PIC>; 170208561Sraj }; 171208561Sraj 172208561Sraj enet0: ethernet@72000 { 173208561Sraj #address-cells = <1>; 174208561Sraj #size-cells = <1>; 175208561Sraj model = "V2"; 176208561Sraj compatible = "mrvl,ge"; 177208561Sraj reg = <0x72000 0x2000>; 178208561Sraj ranges = <0x0 0x72000 0x2000>; 179208561Sraj local-mac-address = [ 00 00 00 00 00 00 ]; 180208561Sraj interrupts = <12 13 14 11 46>; 181208561Sraj interrupt-parent = <&PIC>; 182208561Sraj phy-handle = <&phy0>; 183208561Sraj 184208561Sraj mdio@0 { 185208561Sraj #address-cells = <1>; 186208561Sraj #size-cells = <0>; 187208561Sraj compatible = "mrvl,mdio"; 188208561Sraj 189208561Sraj phy0: ethernet-phy@0 { 190208561Sraj reg = <0x8>; 191208561Sraj }; 192208561Sraj }; 193208561Sraj }; 194208561Sraj 195208561Sraj serial0: serial@12000 { 196208561Sraj compatible = "ns16550"; 197208561Sraj reg = <0x12000 0x20>; 198208561Sraj reg-shift = <2>; 199208561Sraj clock-frequency = <0>; 200208561Sraj interrupts = <33>; 201208561Sraj interrupt-parent = <&PIC>; 202208561Sraj }; 203208561Sraj 204208561Sraj serial1: serial@12100 { 205208561Sraj compatible = "ns16550"; 206208561Sraj reg = <0x12100 0x20>; 207208561Sraj reg-shift = <2>; 208208561Sraj clock-frequency = <0>; 209208561Sraj interrupts = <34>; 210208561Sraj interrupt-parent = <&PIC>; 211208561Sraj }; 212208561Sraj 213208561Sraj crypto@30000 { 214208561Sraj compatible = "mrvl,cesa"; 215208561Sraj reg = <0x30000 0x10000>; 216208561Sraj interrupts = <22>; 217208561Sraj interrupt-parent = <&PIC>; 218227730Sraj 219227730Sraj sram-handle = <&SRAM>; 220208561Sraj }; 221208561Sraj 222208561Sraj usb@50000 { 223208561Sraj compatible = "mrvl,usb-ehci", "usb-ehci"; 224208561Sraj reg = <0x50000 0x1000>; 225208561Sraj interrupts = <48 19>; 226208561Sraj interrupt-parent = <&PIC>; 227208561Sraj }; 228208561Sraj 229208561Sraj xor@60000 { 230208561Sraj compatible = "mrvl,xor"; 231208561Sraj reg = <0x60000 0x1000>; 232208561Sraj interrupts = <5 6 7 8>; 233208561Sraj interrupt-parent = <&PIC>; 234208561Sraj }; 235208561Sraj 236208561Sraj sata@80000 { 237208561Sraj compatible = "mrvl,sata"; 238208561Sraj reg = <0x80000 0x6000>; 239208561Sraj interrupts = <21>; 240208561Sraj interrupt-parent = <&PIC>; 241208561Sraj }; 242208561Sraj }; 243208561Sraj 244208561Sraj SRAM: sram@fd000000 { 245208561Sraj compatible = "mrvl,cesa-sram"; 246208561Sraj reg = <0xfd000000 0x00100000>; 247208561Sraj }; 248208561Sraj 249208561Sraj pci0: pcie@f1040000 { 250208561Sraj compatible = "mrvl,pcie"; 251208561Sraj device_type = "pci"; 252208561Sraj #interrupt-cells = <1>; 253208561Sraj #size-cells = <2>; 254208561Sraj #address-cells = <3>; 255208561Sraj reg = <0xf1040000 0x2000>; 256208561Sraj bus-range = <0 255>; 257208561Sraj ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000 258208561Sraj 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>; 259208561Sraj clock-frequency = <33333333>; 260208561Sraj interrupt-parent = <&PIC>; 261208561Sraj interrupts = <44>; 262208561Sraj interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 263208561Sraj interrupt-map = < 264208561Sraj /* IDSEL 0x1 */ 265208561Sraj 0x0800 0x0 0x0 0x1 &PIC 0x9 266208561Sraj 0x0800 0x0 0x0 0x2 &PIC 0x9 267208561Sraj 0x0800 0x0 0x0 0x3 &PIC 0x9 268208561Sraj 0x0800 0x0 0x0 0x4 &PIC 0x9 269208561Sraj >; 270208561Sraj pcie@0 { 271208561Sraj reg = <0x0 0x0 0x0 0x0 0x0>; 272208561Sraj #size-cells = <2>; 273208561Sraj #address-cells = <3>; 274208561Sraj device_type = "pci"; 275208561Sraj ranges = <0x02000000 0x0 0xf1300000 276208561Sraj 0x02000000 0x0 0xf1300000 277208561Sraj 0x0 0x04000000 278208561Sraj 279208561Sraj 0x01000000 0x0 0x0 280208561Sraj 0x01000000 0x0 0x0 281208561Sraj 0x0 0x00100000>; 282208561Sraj }; 283208561Sraj }; 284235609Sgber 285235609Sgber chosen { 286235609Sgber stdin = "serial0"; 287235609Sgber stdout = "serial0"; 288235609Sgber }; 289208561Sraj}; 290