at91rm9200_lowlevel.c revision 157873
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * This software is derived from software provide by Kwikbyte who specifically 25 * disclaimed copyright on the code. 26 * 27 * $FreeBSD: head/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 157873 2006-04-19 17:16:49Z imp $ 28 */ 29 30#include "at91rm9200.h" 31#include "at91rm9200_lowlevel.h" 32 33#define BAUD 115200 34#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \ 35 AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK) 36 37/* 38 * void DefaultSystemInit(void) 39 * Load the system with sane values based on how the system is configured. 40 * at91rm9200_lowlevel.h is expected to define the necessary parameters. 41 */ 42void 43_init(void) 44{ 45 AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU; 46 AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR); 47 48 register unsigned value; 49 volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE; 50 51#ifdef BOOT_TSC 52 // For the TSC board, we turn ON the one LED we have while 53 // early in boot. 54 AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10; 55 AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10; 56 AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10; 57#endif 58 59 // configure clocks 60 // assume: 61 // main osc = 10Mhz 62 // PLLB configured for 96MHz (48MHz after div) 63 // CSS = PLLB 64 // set PLLA = 180MHz 65 // assume main osc = 10Mhz 66 // div = 5 , out = 2 (150MHz = 240MHz) 67 value = AT91C_BASE_CKGR->CKGR_PLLAR; 68 value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA); 69 value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA | 70 ((OSC_MAIN_MULT - 1) << 16); 71 AT91C_BASE_CKGR->CKGR_PLLAR = value; 72 73 // wait for lock 74 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)) 75 continue; 76 77 // change divider = 3, pres = 1 78 value = AT91C_BASE_PMC->PMC_MCKR; 79 value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES); 80 value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK; 81 AT91C_BASE_PMC->PMC_MCKR = value; 82 83 // wait for update 84 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 85 continue; 86 87 // change CSS = PLLA 88 value &= ~AT91C_PMC_CSS; 89 value |= AT91C_PMC_CSS_PLLA_CLK; 90 AT91C_BASE_PMC->PMC_MCKR = value; 91 92 // wait for update 93 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 94 continue; 95 96 // setup SDRAM access 97 // EBI chip-select register (CS1 = SDRAM controller) 98 // 9 col, 13row, 4 bank, CAS2 99 // write recovery = 2 (Twr) 100 // row cycle = 5 (Trc) 101 // precharge delay = 2 (Trp) 102 // row to col delay 2 (Trcd) 103 // active to precharge = 4 (Tras) 104 // exit self refresh to active = 6 (Txsr) 105 value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA; 106 value &= ~AT91C_EBI_CS1A; 107 value |= AT91C_EBI_CS1A_SDRAMC; 108 AT91C_BASE_EBI->EBI_CSA = value; 109 110 AT91C_BASE_SDRC->SDRC_CR = 111 AT91C_SDRC_NC_9 | 112 AT91C_SDRC_NR_13 | 113 AT91C_SDRC_NB_4_BANKS | 114 AT91C_SDRC_CAS_2 | 115 ((2 << 7) & AT91C_SDRC_TWR) | 116 ((5 << 11) & AT91C_SDRC_TRC) | 117 ((2 << 15) & AT91C_SDRC_TRP) | 118 ((2 << 19) & AT91C_SDRC_TRCD) | 119 ((4 << 23) & AT91C_SDRC_TRAS) | 120 ((6 << 27) & AT91C_SDRC_TXSR); 121 122 // Step 1: We assume 200us of idle time. 123 // Step 2: Issue an all banks precharge command 124 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD; 125 *p = 0; 126 127 // Step 3: Issue 8 Auto-refresh (CBR) cycles 128 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD; 129 *p = 0; 130 *p = 0; 131 *p = 0; 132 *p = 0; 133 *p = 0; 134 *p = 0; 135 *p = 0; 136 *p = 0; 137 138 // Step 4: Issue an Mode Set Register (MRS) cycle to program in 139 // the parameters that we setup in the SDRC_CR register above. 140 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD; 141 *p = 0; 142 143 // Step 5: set the refresh timer and access memory to start it 144 // running. We have to wait 3 clocks after the LMR_CMD above, 145 // and this fits the bill nicely. 146 AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000; 147 *p = 0; 148 149 // Step 6: Set normal mode. 150 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD; 151 *p = 0; 152 153#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS 154 // Turn on the upper 16 bits on the SDRAM bus. 155 AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; 156 AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; 157#endif 158 // Configure DBGU -use local routine optimized for space 159 AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 160 AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 161 pUSART->US_IDR = (unsigned int) -1; 162 pUSART->US_CR = 163 AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; 164 pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10); 165 pUSART->US_TTGR = 0; 166 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 167 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 168 pPDC->PDC_TNPR = 0; 169 pPDC->PDC_TNCR = 0; 170 171 pPDC->PDC_RNPR = 0; 172 pPDC->PDC_RNCR = 0; 173 174 pPDC->PDC_TPR = 0; 175 pPDC->PDC_TCR = 0; 176 177 pPDC->PDC_RPR = 0; 178 pPDC->PDC_RCR = 0; 179 180 pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 181 pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 182 183 pUSART->US_MR = AT91C_US_ASYNC_MODE; 184 pUSART->US_CR = AT91C_US_TXEN; 185 pUSART->US_CR = AT91C_US_RXEN; 186} 187