1164426Ssam/*- 2164426Ssam * Copyright (c) 2006 Sam Leffler, Errno Consulting 3164426Ssam * All rights reserved. 4164426Ssam * 5164426Ssam * Redistribution and use in source and binary forms, with or without 6164426Ssam * modification, are permitted provided that the following conditions 7164426Ssam * are met: 8164426Ssam * 1. Redistributions of source code must retain the above copyright 9164426Ssam * notice, this list of conditions and the following disclaimer, 10164426Ssam * without modification. 11164426Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12164426Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13164426Ssam * redistribution must be conditioned upon including a substantially 14164426Ssam * similar Disclaimer requirement for further binary redistribution. 15164426Ssam * 16164426Ssam * NO WARRANTY 17164426Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18164426Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19164426Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20164426Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21164426Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22164426Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23164426Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24164426Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25164426Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26164426Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27164426Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28164426Ssam * 29164426Ssam * $FreeBSD$ 30164426Ssam */ 31164426Ssam 32164426Ssam/*- 33164426Ssam * Copyright (c) 2001-2005, Intel Corporation. 34164426Ssam * All rights reserved. 35236987Simp * 36164426Ssam * Redistribution and use in source and binary forms, with or without 37164426Ssam * modification, are permitted provided that the following conditions 38164426Ssam * are met: 39164426Ssam * 1. Redistributions of source code must retain the above copyright 40164426Ssam * notice, this list of conditions and the following disclaimer. 41164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 42164426Ssam * notice, this list of conditions and the following disclaimer in the 43164426Ssam * documentation and/or other materials provided with the distribution. 44164426Ssam * 3. Neither the name of the Intel Corporation nor the names of its contributors 45164426Ssam * may be used to endorse or promote products derived from this software 46164426Ssam * without specific prior written permission. 47236987Simp * 48236987Simp * 49164426Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50164426Ssam * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51164426Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52164426Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53164426Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54164426Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55164426Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56164426Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57164426Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58164426Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59164426Ssam * SUCH DAMAGE. 60164426Ssam*/ 61164426Ssam 62164426Ssam#ifndef ARM_XSCALE_IXP425_QMGR_H 63164426Ssam#define ARM_XSCALE_IXP425_QMGR_H 64164426Ssam 65164426Ssam#define IX_QMGR_MAX_NUM_QUEUES 64 66164426Ssam#define IX_QMGR_MIN_QUEUPP_QID 32 67164426Ssam 68164426Ssam#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16 69164426Ssam 70164426Ssam/* Total size of SRAM */ 71164426Ssam#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000 72164426Ssam 73164426Ssam#define IX_QMGR_Q_PRIORITY_0 0 74164426Ssam#define IX_QMGR_Q_PRIORITY_1 1 75164426Ssam#define IX_QMGR_Q_PRIORITY_2 2 76164426Ssam#define IX_QMGR_NUM_PRIORITY_LEVELS 3 /* number of priority levels */ 77164426Ssam 78164426Ssam#define IX_QMGR_Q_STATUS_E_BIT_MASK 0x1 /* Empty */ 79164426Ssam#define IX_QMGR_Q_STATUS_NE_BIT_MASK 0x2 /* Nearly Empty */ 80164426Ssam#define IX_QMGR_Q_STATUS_NF_BIT_MASK 0x4 /* Nearly Full */ 81164426Ssam#define IX_QMGR_Q_STATUS_F_BIT_MASK 0x8 /* Full */ 82164426Ssam#define IX_QMGR_Q_STATUS_UF_BIT_MASK 0x10 /* Underflow */ 83164426Ssam#define IX_QMGR_Q_STATUS_OF_BIT_MASK 0x20 /* Overflow */ 84164426Ssam 85164426Ssam#define IX_QMGR_Q_SOURCE_ID_E 0 /* Q Empty after last read */ 86164426Ssam#define IX_QMGR_Q_SOURCE_ID_NE 1 /* Q Nearly Empty after last read */ 87164426Ssam#define IX_QMGR_Q_SOURCE_ID_NF 2 /* Q Nearly Full after last write */ 88164426Ssam#define IX_QMGR_Q_SOURCE_ID_F 3 /* Q Full after last write */ 89164426Ssam#define IX_QMGR_Q_SOURCE_ID_NOT_E 4 /* Q !Empty after last write */ 90164426Ssam#define IX_QMGR_Q_SOURCE_ID_NOT_NE 5 /* Q !Nearly Empty after last write */ 91164426Ssam#define IX_QMGR_Q_SOURCE_ID_NOT_NF 6 /* Q !Nearly Full after last read */ 92164426Ssam#define IX_QMGR_Q_SOURCE_ID_NOT_F 7 /* Q !Full after last read */ 93164426Ssam 94164426Ssam#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0 /* underflow bit mask */ 95164426Ssam#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1 /* overflow bit mask */ 96164426Ssam 97164426Ssam#define IX_QMGR_QUEACC0_OFFSET 0x0000 /* q 0 access register */ 98164426Ssam#define IX_QMGR_QUEACC_SIZE 0x4/*words*/ 99164426Ssam 100164426Ssam#define IX_QMGR_QUELOWSTAT0_OFFSET 0x400 /* Q status, q's 0-7 */ 101164426Ssam#define IX_QMGR_QUELOWSTAT1_OFFSET 0x404 /* Q status, q's 8-15 */ 102164426Ssam#define IX_QMGR_QUELOWSTAT2_OFFSET 0x408 /* Q status, q's 16-23 */ 103164426Ssam#define IX_QMGR_QUELOWSTAT3_OFFSET 0x40c /* Q status, q's 24-31 */ 104164426Ssam 105164426Ssam/* Queue status register Q status bits mask */ 106164426Ssam#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF 107164426Ssam/* Size of queue 0-31 status register */ 108164426Ssam#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/ 109164426Ssam#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 8 /* # status/word */ 110164426Ssam 111164426Ssam#define IX_QMGR_QUEUOSTAT0_OFFSET 0x410 /* Q UF/OF status, q's 0-15 */ 112164426Ssam#define IX_QMGR_QUEUOSTAT1_OFFSET 0x414 /* Q UF/OF status, q's 16-31 */ 113164426Ssam 114164426Ssam#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 16 /* # UF/OF status/word */ 115164426Ssam 116164426Ssam#define IX_QMGR_QUEUPPSTAT0_OFFSET 0x418 /* NE status, q's 32-63 */ 117164426Ssam#define IX_QMGR_QUEUPPSTAT1_OFFSET 0x41c /* F status, q's 32-63 */ 118164426Ssam 119164426Ssam#define IX_QMGR_INT0SRCSELREG0_OFFSET 0x420 /* INT src select, q's 0-7 */ 120164426Ssam#define IX_QMGR_INT0SRCSELREG1_OFFSET 0x424 /* INT src select, q's 8-15 */ 121164426Ssam#define IX_QMGR_INT0SRCSELREG2_OFFSET 0x428 /* INT src select, q's 16-23 */ 122164426Ssam#define IX_QMGR_INT0SRCSELREG3_OFFSET 0x42c /* INT src select, q's 24-31 */ 123164426Ssam 124164426Ssam#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 8 /* # INT src select/word */ 125164426Ssam 126164426Ssam#define IX_QMGR_QUEIEREG0_OFFSET 0x430 /* INT enable, q's 0-31 */ 127164426Ssam#define IX_QMGR_QUEIEREG1_OFFSET 0x434 /* INT enable, q's 32-63 */ 128164426Ssam#define IX_QMGR_QINTREG0_OFFSET 0x438 /* INT status, q's 0-31 */ 129164426Ssam#define IX_QMGR_QINTREG1_OFFSET 0x43c /* INT status, q's 32-63 */ 130164426Ssam 131164426Ssam#define IX_QMGR_QUECONFIG_BASE_OFFSET 0x2000 /* Q config register, q 0 */ 132164426Ssam 133164426Ssam#define IX_QMGR_QUECONFIG_SIZE 0x100 /* total size of Q config regs*/ 134164426Ssam 135164426Ssam#define IX_QMGR_QUEBUFFER_SPACE_OFFSET 0x2100 /* start of SRAM */ 136164426Ssam 137164426Ssam/* Total bits in a word */ 138164426Ssam#define BITS_PER_WORD 32 139164426Ssam 140164426Ssam/* Size of queue buffer space */ 141164426Ssam#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00 142164426Ssam 143164426Ssam/* 144164426Ssam * This macro will return the address of the access register for the 145164426Ssam * queue specified by qId 146164426Ssam */ 147164426Ssam#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\ 148164426Ssam (((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\ 149164426Ssam + IX_QMGR_QUEACC0_OFFSET) 150164426Ssam 151236987Simp/* 152164426Ssam * Bit location of bit-3 of INT0SRCSELREG0 register to enabled 153164426Ssam * sticky interrupt register. 154164426Ssam */ 155164426Ssam#define IX_QMGR_INT0SRCSELREG0_BIT3 3 156164426Ssam 157164426Ssam/* 158164426Ssam * These defines are the bit offsets of the various fields of 159164426Ssam * the queue configuration register. 160164426Ssam */ 161164426Ssam#if 0 162164426Ssam#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00 163164426Ssam#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07 164164426Ssam#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E 165164426Ssam#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16 166164426Ssam#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18 167164426Ssam#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A 168164426Ssam#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D 169164426Ssam 170164426Ssam#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF 171164426Ssam#define IX_QMGR_NE_MASK 0x7 172164426Ssam#define IX_QMGR_NF_MASK 0x7 173164426Ssam#define IX_QMGR_SIZE_MASK 0x3 174164426Ssam#define IX_QMGR_ENTRY_SIZE_MASK 0x3 175164426Ssam#define IX_QMGR_BADDR_MASK 0x003FC000 176164426Ssam#define IX_QMGR_RDPTR_MASK 0x7F 177164426Ssam#define IX_QMGR_WRPTR_MASK 0x7F 178164426Ssam#define IX_QMGR_RDWRPTR_MASK 0x00003FFF 179164426Ssam#else 180164426Ssam#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0 181164426Ssam#define IX_QMGR_WRPTR_MASK 0x7F 182164426Ssam#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 7 183164426Ssam#define IX_QMGR_RDPTR_MASK 0x7F 184164426Ssam#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 14 185164426Ssam#define IX_QMGR_BADDR_MASK 0x3FC000 /* XXX not used */ 186164426Ssam#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 22 187164426Ssam#define IX_QMGR_ENTRY_SIZE_MASK 0x3 188164426Ssam#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 24 189164426Ssam#define IX_QMGR_SIZE_MASK 0x3 190164426Ssam#define IX_QMGR_Q_CONFIG_NE_OFFSET 26 191164426Ssam#define IX_QMGR_NE_MASK 0x7 192164426Ssam#define IX_QMGR_Q_CONFIG_NF_OFFSET 29 193164426Ssam#define IX_QMGR_NF_MASK 0x7 194164426Ssam 195164426Ssam#define IX_QMGR_RDWRPTR_MASK 0x00003FFF 196164426Ssam#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF 197164426Ssam#endif 198164426Ssam 199164426Ssam#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 64 200164426Ssam#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 6 201164426Ssam 202164426Ssam#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000 203164426Ssam 204164426Ssam/* Base address of AQM SRAM */ 205164426Ssam#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \ 206164426Ssam((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE)) 207164426Ssam 208164426Ssam/* Min buffer size used for generating buffer size in QUECONFIG */ 209164426Ssam#define IX_QMGR_MIN_BUFFER_SIZE 16 210164426Ssam 211164426Ssam/* Reset values of QMgr hardware registers */ 212164426Ssam#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333 213164426Ssam#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000 214164426Ssam#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF 215164426Ssam#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000 216164426Ssam#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000 217164426Ssam#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000 218164426Ssam#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF 219164426Ssam#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000 220164426Ssam 221164426Ssam#define IX_QMGR_QUELOWSTAT_BITS_PER_Q \ 222164426Ssam (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) 223164426Ssam 224164426Ssam#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7 225164426Ssam#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\ 226164426Ssam (((qId) * sizeof(uint32_t)) + IX_QMGR_QUECONFIG_BASE_OFFSET) 227164426Ssam 228164426Ssam#define IX_QMGR_ENTRY1_OFFSET 0 229164426Ssam#define IX_QMGR_ENTRY2_OFFSET 1 230164426Ssam#define IX_QMGR_ENTRY4_OFFSET 3 231164426Ssam 232193096Sattiliotypedef void qconfig_hand_t(int, void *); 233193096Sattilio 234164426Ssamint ixpqmgr_qconfig(int qId, int qSizeInWords, int ne, int nf, int srcSel, 235193096Sattilio qconfig_hand_t *cb, void *cbarg); 236164426Ssamint ixpqmgr_qwrite(int qId, uint32_t entry); 237164426Ssamint ixpqmgr_qread(int qId, uint32_t *entry); 238164426Ssamint ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p); 239164426Ssamuint32_t ixpqmgr_getqstatus(int qId); 240164426Ssamuint32_t ixpqmgr_getqconfig(int qId); 241164426Ssamvoid ixpqmgr_notify_enable(int qId, int srcSel); 242164426Ssamvoid ixpqmgr_notify_disable(int qId); 243164426Ssamvoid ixpqmgr_dump(void); 244164426Ssam 245164426Ssam#endif /* ARM_XSCALE_IXP425_QMGR_H */ 246