if_npe.c revision 186420
1/*- 2 * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 186420 2008-12-23 04:51:46Z sam $"); 27 28/* 29 * Intel XScale NPE Ethernet driver. 30 * 31 * This driver handles the two ports present on the IXP425. 32 * Packet processing is done by the Network Processing Engines 33 * (NPE's) that work together with a MAC and PHY. The MAC 34 * is also mapped to the XScale cpu; the PHY is accessed via 35 * the MAC. NPE-XScale communication happens through h/w 36 * queues managed by the Q Manager block. 37 * 38 * The code here replaces the ethAcc, ethMii, and ethDB classes 39 * in the Intel Access Library (IAL) and the OS-specific driver. 40 * 41 * XXX add vlan support 42 */ 43#ifdef HAVE_KERNEL_OPTION_HEADERS 44#include "opt_device_polling.h" 45#endif 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/bus.h> 50#include <sys/kernel.h> 51#include <sys/mbuf.h> 52#include <sys/malloc.h> 53#include <sys/module.h> 54#include <sys/rman.h> 55#include <sys/socket.h> 56#include <sys/sockio.h> 57#include <sys/sysctl.h> 58#include <sys/endian.h> 59#include <machine/bus.h> 60 61#include <net/ethernet.h> 62#include <net/if.h> 63#include <net/if_arp.h> 64#include <net/if_dl.h> 65#include <net/if_media.h> 66#include <net/if_mib.h> 67#include <net/if_types.h> 68 69#ifdef INET 70#include <netinet/in.h> 71#include <netinet/in_systm.h> 72#include <netinet/in_var.h> 73#include <netinet/ip.h> 74#endif 75 76#include <net/bpf.h> 77#include <net/bpfdesc.h> 78 79#include <arm/xscale/ixp425/ixp425reg.h> 80#include <arm/xscale/ixp425/ixp425var.h> 81#include <arm/xscale/ixp425/ixp425_qmgr.h> 82#include <arm/xscale/ixp425/ixp425_npevar.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86#include <arm/xscale/ixp425/if_npereg.h> 87 88#include <machine/armreg.h> 89 90#include "miibus_if.h" 91 92/* 93 * XXX: For the main bus dma tag. Can go away if the new method to get the 94 * dma tag from the parent got MFC'd into RELENG_6. 95 */ 96extern struct ixp425_softc *ixp425_softc; 97 98struct npebuf { 99 struct npebuf *ix_next; /* chain to next buffer */ 100 void *ix_m; /* backpointer to mbuf */ 101 bus_dmamap_t ix_map; /* bus dma map for associated data */ 102 struct npehwbuf *ix_hw; /* associated h/w block */ 103 uint32_t ix_neaddr; /* phys address of ix_hw */ 104}; 105 106struct npedma { 107 const char* name; 108 int nbuf; /* # npebuf's allocated */ 109 bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 110 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 111 bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 112 bus_dmamap_t buf_map; 113 bus_addr_t buf_phys; /* phys addr of buffers */ 114 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 115}; 116 117struct npe_softc { 118 /* XXX mii requires this be first; do not move! */ 119 struct ifnet *sc_ifp; /* ifnet pointer */ 120 struct mtx sc_mtx; /* basically a perimeter lock */ 121 device_t sc_dev; 122 bus_space_tag_t sc_iot; 123 bus_space_handle_t sc_ioh; /* MAC register window */ 124 device_t sc_mii; /* child miibus */ 125 bus_space_handle_t sc_miih; /* MII register window */ 126 int sc_npeid; 127 struct ixpnpe_softc *sc_npe; /* NPE support */ 128 int sc_debug; /* DPRINTF* control */ 129 int sc_tickinterval; 130 struct callout tick_ch; /* Tick callout */ 131 int npe_watchdog_timer; 132 struct npedma txdma; 133 struct npebuf *tx_free; /* list of free tx buffers */ 134 struct npedma rxdma; 135 bus_addr_t buf_phys; /* XXX for returning a value */ 136 int rx_qid; /* rx qid */ 137 int rx_freeqid; /* rx free buffers qid */ 138 int tx_qid; /* tx qid */ 139 int tx_doneqid; /* tx completed qid */ 140 int sc_phy; /* PHY id */ 141 struct ifmib_iso_8802_3 mibdata; 142 bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 143 struct npestats *sc_stats; 144 bus_dmamap_t sc_stats_map; 145 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 146}; 147 148/* 149 * Static configuration for IXP425. The tx and 150 * rx free Q id's are fixed by the NPE microcode. The 151 * rx Q id's are programmed to be separate to simplify 152 * multi-port processing. It may be better to handle 153 * all traffic through one Q (as done by the Intel drivers). 154 * 155 * Note that the PHY's are accessible only from MAC A 156 * on the IXP425. This and other platform-specific 157 * assumptions probably need to be handled through hints. 158 */ 159static const struct { 160 uint32_t macbase; 161 uint32_t miibase; 162 int phy; /* phy id */ 163 uint8_t rx_qid; 164 uint8_t rx_freeqid; 165 uint8_t tx_qid; 166 uint8_t tx_doneqid; 167} npeconfig[NPE_MAX] = { 168 [NPE_A] = { 169 .macbase = IXP435_MAC_A_HWBASE, 170 .miibase = IXP425_MAC_C_HWBASE, 171 .phy = 2, 172 .rx_qid = 4, 173 .rx_freeqid = 26, 174 .tx_qid = 23, 175 .tx_doneqid = 31 176 }, 177 [NPE_B] = { 178 .macbase = IXP425_MAC_B_HWBASE, 179 .miibase = IXP425_MAC_C_HWBASE, 180 .phy = 0, 181 .rx_qid = 4, 182 .rx_freeqid = 27, 183 .tx_qid = 24, 184 .tx_doneqid = 31 185 }, 186 [NPE_C] = { 187 .macbase = IXP425_MAC_C_HWBASE, 188 .miibase = IXP425_MAC_C_HWBASE, 189 .phy = 1, 190 .rx_qid = 12, 191 .rx_freeqid = 28, 192 .tx_qid = 25, 193 .tx_doneqid = 31 194 }, 195}; 196static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 197 198static __inline uint32_t 199RD4(struct npe_softc *sc, bus_size_t off) 200{ 201 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 202} 203 204static __inline void 205WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 206{ 207 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 208} 209 210#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 211#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 212#define NPE_LOCK_INIT(_sc) \ 213 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 214 MTX_NETWORK_LOCK, MTX_DEF) 215#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 216#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 217#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 218 219static devclass_t npe_devclass; 220 221static int override_npeid(device_t, const char *resname, int *val); 222static int npe_activate(device_t dev); 223static void npe_deactivate(device_t dev); 224static int npe_ifmedia_update(struct ifnet *ifp); 225static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 226static void npe_setmac(struct npe_softc *sc, u_char *eaddr); 227static void npe_getmac(struct npe_softc *sc, u_char *eaddr); 228static void npe_txdone(int qid, void *arg); 229static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 230 struct mbuf *); 231static void npe_rxdone(int qid, void *arg); 232static void npeinit(void *); 233static void npestart_locked(struct ifnet *); 234static void npestart(struct ifnet *); 235static void npestop(struct npe_softc *); 236static void npewatchdog(struct npe_softc *); 237static int npeioctl(struct ifnet * ifp, u_long, caddr_t); 238 239static int npe_setrxqosentry(struct npe_softc *, int classix, 240 int trafclass, int qid); 241static int npe_setfirewallmode(struct npe_softc *, int onoff); 242static int npe_updatestats(struct npe_softc *); 243#if 0 244static int npe_getstats(struct npe_softc *); 245static uint32_t npe_getimageid(struct npe_softc *); 246static int npe_setloopback(struct npe_softc *, int ena); 247#endif 248 249/* NB: all tx done processing goes through one queue */ 250static int tx_doneqid = -1; 251 252SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters"); 253 254static int npe_debug = 0; 255SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug, 256 0, "IXP4XX NPE network interface debug msgs"); 257TUNABLE_INT("hw.npe.debug", &npe_debug); 258#define DPRINTF(sc, fmt, ...) do { \ 259 if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 260} while (0) 261#define DPRINTFn(n, sc, fmt, ...) do { \ 262 if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 263} while (0) 264static int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 265SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval, 266 0, "periodic work interval (secs)"); 267TUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval); 268 269static int npe_rxbuf = 64; /* # rx buffers to allocate */ 270SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf, 271 0, "rx buffers allocated"); 272TUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf); 273static int npe_txbuf = 128; /* # tx buffers to allocate */ 274SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf, 275 0, "tx buffers allocated"); 276TUNABLE_INT("hw.npe.txbuf", &npe_txbuf); 277 278static int 279unit2npeid(int unit) 280{ 281 static const int npeidmap[2][3] = { 282 /* on 425 A is for HSS, B & C are for Ethernet */ 283 { NPE_B, NPE_C, -1 }, /* IXP425 */ 284 /* 435 only has A & C, order C then A */ 285 { NPE_C, NPE_A, -1 }, /* IXP435 */ 286 }; 287 /* XXX check feature register instead */ 288 return (unit < 3 ? npeidmap[ 289 (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 290} 291 292static int 293npe_probe(device_t dev) 294{ 295 static const char *desc[NPE_MAX] = { 296 [NPE_A] = "IXP NPE-A", 297 [NPE_B] = "IXP NPE-B", 298 [NPE_C] = "IXP NPE-C" 299 }; 300 int unit = device_get_unit(dev); 301 int npeid; 302 303 if (unit > 2 || 304 (ixp4xx_read_feature_bits() & 305 (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 306 return EINVAL; 307 308 npeid = -1; 309 if (!override_npeid(dev, "npeid", &npeid)) 310 npeid = unit2npeid(unit); 311 if (npeid == -1) { 312 device_printf(dev, "unit %d not supported\n", unit); 313 return EINVAL; 314 } 315 device_set_desc(dev, desc[npeid]); 316 return 0; 317} 318 319static int 320npe_attach(device_t dev) 321{ 322 struct npe_softc *sc = device_get_softc(dev); 323 struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 324 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 325 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 326 struct ifnet *ifp; 327 int error; 328 u_char eaddr[6]; 329 330 sc->sc_dev = dev; 331 sc->sc_iot = sa->sc_iot; 332 NPE_LOCK_INIT(sc); 333 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 334 sc->sc_debug = npe_debug; 335 sc->sc_tickinterval = npe_tickinterval; 336 337 ifp = if_alloc(IFT_ETHER); 338 if (ifp == NULL) { 339 device_printf(dev, "cannot allocate ifnet\n"); 340 error = EIO; /* XXX */ 341 goto out; 342 } 343 /* NB: must be setup prior to invoking mii code */ 344 sc->sc_ifp = ifp; 345 346 error = npe_activate(dev); 347 if (error) { 348 device_printf(dev, "cannot activate npe\n"); 349 goto out; 350 } 351 352 npe_getmac(sc, eaddr); 353 354 ifp->if_softc = sc; 355 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 356 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 357 ifp->if_start = npestart; 358 ifp->if_ioctl = npeioctl; 359 ifp->if_init = npeinit; 360 IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 361 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 362 IFQ_SET_READY(&ifp->if_snd); 363 ifp->if_linkmib = &sc->mibdata; 364 ifp->if_linkmiblen = sizeof(sc->mibdata); 365 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 366#ifdef DEVICE_POLLING 367 ifp->if_capabilities |= IFCAP_POLLING; 368#endif 369 370 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 371 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 372 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 373 CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 374 375 ether_ifattach(ifp, eaddr); 376 return 0; 377out: 378 if (ifp != NULL) 379 if_free(ifp); 380 NPE_LOCK_DESTROY(sc); 381 npe_deactivate(dev); 382 return error; 383} 384 385static int 386npe_detach(device_t dev) 387{ 388 struct npe_softc *sc = device_get_softc(dev); 389 struct ifnet *ifp = sc->sc_ifp; 390 391#ifdef DEVICE_POLLING 392 if (ifp->if_capenable & IFCAP_POLLING) 393 ether_poll_deregister(ifp); 394#endif 395 npestop(sc); 396 if (ifp != NULL) { 397 ether_ifdetach(ifp); 398 if_free(ifp); 399 } 400 NPE_LOCK_DESTROY(sc); 401 npe_deactivate(dev); 402 return 0; 403} 404 405/* 406 * Compute and install the multicast filter. 407 */ 408static void 409npe_setmcast(struct npe_softc *sc) 410{ 411 struct ifnet *ifp = sc->sc_ifp; 412 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 413 int i; 414 415 if (ifp->if_flags & IFF_PROMISC) { 416 memset(mask, 0, ETHER_ADDR_LEN); 417 memset(addr, 0, ETHER_ADDR_LEN); 418 } else if (ifp->if_flags & IFF_ALLMULTI) { 419 static const uint8_t allmulti[ETHER_ADDR_LEN] = 420 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 421 memcpy(mask, allmulti, ETHER_ADDR_LEN); 422 memcpy(addr, allmulti, ETHER_ADDR_LEN); 423 } else { 424 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 425 struct ifmultiaddr *ifma; 426 const uint8_t *mac; 427 428 memset(clr, 0, ETHER_ADDR_LEN); 429 memset(set, 0xff, ETHER_ADDR_LEN); 430 431 IF_ADDR_LOCK(ifp); 432 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 433 if (ifma->ifma_addr->sa_family != AF_LINK) 434 continue; 435 mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 436 for (i = 0; i < ETHER_ADDR_LEN; i++) { 437 clr[i] |= mac[i]; 438 set[i] &= mac[i]; 439 } 440 } 441 IF_ADDR_UNLOCK(ifp); 442 443 for (i = 0; i < ETHER_ADDR_LEN; i++) { 444 mask[i] = set[i] | ~clr[i]; 445 addr[i] = set[i]; 446 } 447 } 448 449 /* 450 * Write the mask and address registers. 451 */ 452 for (i = 0; i < ETHER_ADDR_LEN; i++) { 453 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 454 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 455 } 456} 457 458static void 459npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 460{ 461 struct npe_softc *sc; 462 463 if (error != 0) 464 return; 465 sc = (struct npe_softc *)arg; 466 sc->buf_phys = segs[0].ds_addr; 467} 468 469static int 470npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 471 const char *name, int nbuf, int maxseg) 472{ 473 int error, i; 474 475 memset(dma, 0, sizeof(*dma)); 476 477 dma->name = name; 478 dma->nbuf = nbuf; 479 480 /* DMA tag for mapped mbufs */ 481 error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 482 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 483 MCLBYTES, maxseg, MCLBYTES, 0, 484 busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 485 if (error != 0) { 486 device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 487 "error %u\n", dma->name, error); 488 return error; 489 } 490 491 /* DMA tag and map for the NPE buffers */ 492 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 493 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 494 nbuf * sizeof(struct npehwbuf), 1, 495 nbuf * sizeof(struct npehwbuf), 0, 496 busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 497 if (error != 0) { 498 device_printf(sc->sc_dev, 499 "unable to create %s npebuf dma tag, error %u\n", 500 dma->name, error); 501 return error; 502 } 503 /* XXX COHERENT for now */ 504 if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 505 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 506 &dma->buf_map) != 0) { 507 device_printf(sc->sc_dev, 508 "unable to allocate memory for %s h/w buffers, error %u\n", 509 dma->name, error); 510 return error; 511 } 512 /* XXX M_TEMP */ 513 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 514 if (dma->buf == NULL) { 515 device_printf(sc->sc_dev, 516 "unable to allocate memory for %s s/w buffers\n", 517 dma->name); 518 return error; 519 } 520 if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 521 dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 522 device_printf(sc->sc_dev, 523 "unable to map memory for %s h/w buffers, error %u\n", 524 dma->name, error); 525 return error; 526 } 527 dma->buf_phys = sc->buf_phys; 528 for (i = 0; i < dma->nbuf; i++) { 529 struct npebuf *npe = &dma->buf[i]; 530 struct npehwbuf *hw = &dma->hwbuf[i]; 531 532 /* calculate offset to shared area */ 533 npe->ix_neaddr = dma->buf_phys + 534 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 535 KASSERT((npe->ix_neaddr & 0x1f) == 0, 536 ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 537 error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 538 &npe->ix_map); 539 if (error != 0) { 540 device_printf(sc->sc_dev, 541 "unable to create dmamap for %s buffer %u, " 542 "error %u\n", dma->name, i, error); 543 return error; 544 } 545 npe->ix_hw = hw; 546 } 547 bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 548 return 0; 549} 550 551static void 552npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 553{ 554 int i; 555 556 if (dma->hwbuf != NULL) { 557 for (i = 0; i < dma->nbuf; i++) { 558 struct npebuf *npe = &dma->buf[i]; 559 bus_dmamap_destroy(dma->mtag, npe->ix_map); 560 } 561 bus_dmamap_unload(dma->buf_tag, dma->buf_map); 562 bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 563 } 564 if (dma->buf != NULL) 565 free(dma->buf, M_TEMP); 566 if (dma->buf_tag) 567 bus_dma_tag_destroy(dma->buf_tag); 568 if (dma->mtag) 569 bus_dma_tag_destroy(dma->mtag); 570 memset(dma, 0, sizeof(*dma)); 571} 572 573static int 574override_addr(device_t dev, const char *resname, int *base) 575{ 576 int unit = device_get_unit(dev); 577 const char *resval; 578 579 /* XXX warn for wrong hint type */ 580 if (resource_string_value("npe", unit, resname, &resval) != 0) 581 return 0; 582 switch (resval[0]) { 583 case 'A': 584 *base = IXP435_MAC_A_HWBASE; 585 break; 586 case 'B': 587 *base = IXP425_MAC_B_HWBASE; 588 break; 589 case 'C': 590 *base = IXP425_MAC_C_HWBASE; 591 break; 592 default: 593 device_printf(dev, "Warning, bad value %s for " 594 "npe.%d.%s ignored\n", resval, unit, resname); 595 return 0; 596 } 597 if (bootverbose) 598 device_printf(dev, "using npe.%d.%s=%s override\n", 599 unit, resname, resval); 600 return 1; 601} 602 603static int 604override_npeid(device_t dev, const char *resname, int *npeid) 605{ 606 int unit = device_get_unit(dev); 607 const char *resval; 608 609 /* XXX warn for wrong hint type */ 610 if (resource_string_value("npe", unit, resname, &resval) != 0) 611 return 0; 612 switch (resval[0]) { 613 case 'A': *npeid = NPE_A; break; 614 case 'B': *npeid = NPE_B; break; 615 case 'C': *npeid = NPE_C; break; 616 default: 617 device_printf(dev, "Warning, bad value %s for " 618 "npe.%d.%s ignored\n", resval, unit, resname); 619 return 0; 620 } 621 if (bootverbose) 622 device_printf(dev, "using npe.%d.%s=%s override\n", 623 unit, resname, resval); 624 return 1; 625} 626 627static int 628override_unit(device_t dev, const char *resname, int *val, int min, int max) 629{ 630 int unit = device_get_unit(dev); 631 int resval; 632 633 if (resource_int_value("npe", unit, resname, &resval) != 0) 634 return 0; 635 if (!(min <= resval && resval <= max)) { 636 device_printf(dev, "Warning, bad value %d for npe.%d.%s " 637 "ignored (value must be [%d-%d])\n", resval, unit, 638 resname, min, max); 639 return 0; 640 } 641 if (bootverbose) 642 device_printf(dev, "using npe.%d.%s=%d override\n", 643 unit, resname, resval); 644 *val = resval; 645 return 1; 646} 647 648static void 649npe_mac_reset(struct npe_softc *sc) 650{ 651 /* 652 * Reset MAC core. 653 */ 654 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 655 DELAY(NPE_MAC_RESET_DELAY); 656 /* configure MAC to generate MDC clock */ 657 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 658} 659 660static int 661npe_activate(device_t dev) 662{ 663 struct npe_softc * sc = device_get_softc(dev); 664 int error, i, macbase, miibase; 665 666 /* 667 * Setup NEP ID, MAC, and MII bindings. We allow override 668 * via hints to handle unexpected board configs. 669 */ 670 if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 671 sc->sc_npeid = unit2npeid(device_get_unit(dev)); 672 sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 673 if (sc->sc_npe == NULL) { 674 device_printf(dev, "cannot attach ixpnpe\n"); 675 return EIO; /* XXX */ 676 } 677 678 /* MAC */ 679 if (!override_addr(dev, "mac", &macbase)) 680 macbase = npeconfig[sc->sc_npeid].macbase; 681 device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 682 if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 683 device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 684 macbase, IXP425_REG_SIZE); 685 return ENOMEM; 686 } 687 688 /* PHY */ 689 if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1)) 690 sc->sc_phy = npeconfig[sc->sc_npeid].phy; 691 if (!override_addr(dev, "mii", &miibase)) 692 miibase = npeconfig[sc->sc_npeid].miibase; 693 device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 694 if (miibase != macbase) { 695 /* 696 * PHY is mapped through a different MAC, setup an 697 * additional mapping for frobbing the PHY registers. 698 */ 699 if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 700 device_printf(dev, 701 "cannot map MII registers 0x%x:0x%x\n", 702 miibase, IXP425_REG_SIZE); 703 return ENOMEM; 704 } 705 } else 706 sc->sc_miih = sc->sc_ioh; 707 708 /* 709 * Load NPE firmware and start it running. 710 */ 711 error = ixpnpe_init(sc->sc_npe); 712 if (error != 0) { 713 device_printf(dev, "cannot init NPE (error %d)\n", error); 714 return error; 715 } 716 717 /* probe for PHY */ 718 if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) { 719 device_printf(dev, "cannot find PHY %d.\n", sc->sc_phy); 720 return ENXIO; 721 } 722 723 error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 724 if (error != 0) 725 return error; 726 error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 727 if (error != 0) 728 return error; 729 730 /* setup statistics block */ 731 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 732 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 733 sizeof(struct npestats), 1, sizeof(struct npestats), 0, 734 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 735 if (error != 0) { 736 device_printf(sc->sc_dev, "unable to create stats tag, " 737 "error %u\n", error); 738 return error; 739 } 740 if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 741 BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 742 device_printf(sc->sc_dev, 743 "unable to allocate memory for stats block, error %u\n", 744 error); 745 return error; 746 } 747 if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 748 sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 749 device_printf(sc->sc_dev, 750 "unable to load memory for stats block, error %u\n", 751 error); 752 return error; 753 } 754 sc->sc_stats_phys = sc->buf_phys; 755 756 /* 757 * Setup h/w rx/tx queues. There are four q's: 758 * rx inbound q of rx'd frames 759 * rx_free pool of ixpbuf's for receiving frames 760 * tx outbound q of frames to send 761 * tx_done q of tx frames that have been processed 762 * 763 * The NPE handles the actual tx/rx process and the q manager 764 * handles the queues. The driver just writes entries to the 765 * q manager mailbox's and gets callbacks when there are rx'd 766 * frames to process or tx'd frames to reap. These callbacks 767 * are controlled by the q configurations; e.g. we get a 768 * callback when tx_done has 2 or more frames to process and 769 * when the rx q has at least one frame. These setings can 770 * changed at the time the q is configured. 771 */ 772 sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 773 ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 774 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_rxdone, sc); 775 sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 776 ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 777 /* 778 * Setup the NPE to direct all traffic to rx_qid. 779 * When QoS is enabled in the firmware there are 780 * 8 traffic classes; otherwise just 4. 781 */ 782 for (i = 0; i < 8; i++) 783 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 784 785 /* disable firewall mode just in case (should be off) */ 786 npe_setfirewallmode(sc, 0); 787 788 sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 789 sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 790 ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 791 if (tx_doneqid == -1) { 792 ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 793 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 794 tx_doneqid = sc->tx_doneqid; 795 } 796 797 KASSERT(npes[sc->sc_npeid] == NULL, 798 ("npe %u already setup", sc->sc_npeid)); 799 npes[sc->sc_npeid] = sc; 800 801 return 0; 802} 803 804static void 805npe_deactivate(device_t dev) 806{ 807 struct npe_softc *sc = device_get_softc(dev); 808 809 npes[sc->sc_npeid] = NULL; 810 811 /* XXX disable q's */ 812 if (sc->sc_npe != NULL) { 813 ixpnpe_stop(sc->sc_npe); 814 ixpnpe_detach(sc->sc_npe); 815 } 816 if (sc->sc_stats != NULL) { 817 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 818 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 819 sc->sc_stats_map); 820 } 821 if (sc->sc_stats_tag != NULL) 822 bus_dma_tag_destroy(sc->sc_stats_tag); 823 npe_dma_destroy(sc, &sc->txdma); 824 npe_dma_destroy(sc, &sc->rxdma); 825 bus_generic_detach(sc->sc_dev); 826 if (sc->sc_mii != NULL) 827 device_delete_child(sc->sc_dev, sc->sc_mii); 828} 829 830/* 831 * Change media according to request. 832 */ 833static int 834npe_ifmedia_update(struct ifnet *ifp) 835{ 836 struct npe_softc *sc = ifp->if_softc; 837 struct mii_data *mii; 838 839 mii = device_get_softc(sc->sc_mii); 840 NPE_LOCK(sc); 841 mii_mediachg(mii); 842 /* XXX push state ourself? */ 843 NPE_UNLOCK(sc); 844 return (0); 845} 846 847/* 848 * Notify the world which media we're using. 849 */ 850static void 851npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 852{ 853 struct npe_softc *sc = ifp->if_softc; 854 struct mii_data *mii; 855 856 mii = device_get_softc(sc->sc_mii); 857 NPE_LOCK(sc); 858 mii_pollstat(mii); 859 ifmr->ifm_active = mii->mii_media_active; 860 ifmr->ifm_status = mii->mii_media_status; 861 NPE_UNLOCK(sc); 862} 863 864static void 865npe_addstats(struct npe_softc *sc) 866{ 867#define MIBADD(x) sc->mibdata.x += be32toh(ns->x) 868 struct ifnet *ifp = sc->sc_ifp; 869 struct npestats *ns = sc->sc_stats; 870 871 MIBADD(dot3StatsAlignmentErrors); 872 MIBADD(dot3StatsFCSErrors); 873 MIBADD(dot3StatsSingleCollisionFrames); 874 MIBADD(dot3StatsMultipleCollisionFrames); 875 MIBADD(dot3StatsDeferredTransmissions); 876 MIBADD(dot3StatsLateCollisions); 877 MIBADD(dot3StatsExcessiveCollisions); 878 MIBADD(dot3StatsInternalMacTransmitErrors); 879 MIBADD(dot3StatsCarrierSenseErrors); 880 sc->mibdata.dot3StatsFrameTooLongs += 881 be32toh(ns->RxLargeFramesDiscards) 882 + be32toh(ns->TxLargeFrameDiscards); 883 MIBADD(dot3StatsInternalMacReceiveErrors); 884 sc->mibdata.dot3StatsMissedFrames += 885 be32toh(ns->RxOverrunDiscards) 886 + be32toh(ns->RxUnderflowEntryDiscards); 887 888 ifp->if_oerrors += 889 be32toh(ns->dot3StatsInternalMacTransmitErrors) 890 + be32toh(ns->dot3StatsCarrierSenseErrors) 891 + be32toh(ns->TxVLANIdFilterDiscards) 892 ; 893 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 894 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 895 + be32toh(ns->RxOverrunDiscards) 896 + be32toh(ns->RxUnderflowEntryDiscards) 897 ; 898 ifp->if_collisions += 899 be32toh(ns->dot3StatsSingleCollisionFrames) 900 + be32toh(ns->dot3StatsMultipleCollisionFrames) 901 ; 902#undef MIBADD 903} 904 905static void 906npe_tick(void *xsc) 907{ 908#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 909 struct npe_softc *sc = xsc; 910 struct mii_data *mii = device_get_softc(sc->sc_mii); 911 uint32_t msg[2]; 912 913 NPE_ASSERT_LOCKED(sc); 914 915 /* 916 * NB: to avoid sleeping with the softc lock held we 917 * split the NPE msg processing into two parts. The 918 * request for statistics is sent w/o waiting for a 919 * reply and then on the next tick we retrieve the 920 * results. This works because npe_tick is the only 921 * code that talks via the mailbox's (except at setup). 922 * This likely can be handled better. 923 */ 924 if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 925 bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 926 BUS_DMASYNC_POSTREAD); 927 npe_addstats(sc); 928 } 929 npe_updatestats(sc); 930 mii_tick(mii); 931 932 npewatchdog(sc); 933 934 /* schedule next poll */ 935 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 936#undef ACK 937} 938 939static void 940npe_setmac(struct npe_softc *sc, u_char *eaddr) 941{ 942 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 943 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 944 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 945 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 946 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 947 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 948} 949 950static void 951npe_getmac(struct npe_softc *sc, u_char *eaddr) 952{ 953 /* NB: the unicast address appears to be loaded from EEPROM on reset */ 954 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 955 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 956 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 957 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 958 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 959 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 960} 961 962struct txdone { 963 struct npebuf *head; 964 struct npebuf **tail; 965 int count; 966}; 967 968static __inline void 969npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 970{ 971 struct ifnet *ifp = sc->sc_ifp; 972 973 NPE_LOCK(sc); 974 *td->tail = sc->tx_free; 975 sc->tx_free = td->head; 976 /* 977 * We're no longer busy, so clear the busy flag and call the 978 * start routine to xmit more packets. 979 */ 980 ifp->if_opackets += td->count; 981 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 982 sc->npe_watchdog_timer = 0; 983 npestart_locked(ifp); 984 NPE_UNLOCK(sc); 985} 986 987/* 988 * Q manager callback on tx done queue. Reap mbufs 989 * and return tx buffers to the free list. Finally 990 * restart output. Note the microcode has only one 991 * txdone q wired into it so we must use the NPE ID 992 * returned with each npehwbuf to decide where to 993 * send buffers. 994 */ 995static void 996npe_txdone(int qid, void *arg) 997{ 998#define P2V(a, dma) \ 999 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1000 struct npe_softc *sc0 = arg; 1001 struct npe_softc *sc; 1002 struct npebuf *npe; 1003 struct txdone *td, q[NPE_MAX]; 1004 uint32_t entry; 1005 1006 /* XXX no NPE-A support */ 1007 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1008 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1009 /* XXX max # at a time? */ 1010 while (ixpqmgr_qread(qid, &entry) == 0) { 1011 DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1012 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1013 1014 sc = npes[NPE_QM_Q_NPE(entry)]; 1015 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1016 m_freem(npe->ix_m); 1017 npe->ix_m = NULL; 1018 1019 td = &q[NPE_QM_Q_NPE(entry)]; 1020 *td->tail = npe; 1021 td->tail = &npe->ix_next; 1022 td->count++; 1023 } 1024 1025 if (q[NPE_B].count) 1026 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1027 if (q[NPE_C].count) 1028 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1029#undef P2V 1030} 1031 1032static int 1033npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1034{ 1035 bus_dma_segment_t segs[1]; 1036 struct npedma *dma = &sc->rxdma; 1037 struct npehwbuf *hw; 1038 int error, nseg; 1039 1040 if (m == NULL) { 1041 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1042 if (m == NULL) 1043 return ENOBUFS; 1044 } 1045 KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1046 ("ext_size %d", m->m_ext.ext_size)); 1047 m->m_pkthdr.len = m->m_len = 1536; 1048 /* backload payload and align ip hdr */ 1049 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1050 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1051 segs, &nseg, 0); 1052 if (error != 0) { 1053 m_freem(m); 1054 return error; 1055 } 1056 hw = npe->ix_hw; 1057 hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1058 /* NB: NPE requires length be a multiple of 64 */ 1059 /* NB: buffer length is shifted in word */ 1060 hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1061 hw->ix_ne[0].next = 0; 1062 npe->ix_m = m; 1063 /* Flush the memory in the mbuf */ 1064 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1065 return 0; 1066} 1067 1068/* 1069 * RX q processing for a specific NPE. Claim entries 1070 * from the hardware queue and pass the frames up the 1071 * stack. Pass the rx buffers to the free list. 1072 */ 1073static void 1074npe_rxdone(int qid, void *arg) 1075{ 1076#define P2V(a, dma) \ 1077 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1078 struct npe_softc *sc = arg; 1079 struct npedma *dma = &sc->rxdma; 1080 uint32_t entry; 1081 1082 while (ixpqmgr_qread(qid, &entry) == 0) { 1083 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1084 struct mbuf *m; 1085 1086 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1087 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1088 /* 1089 * Allocate a new mbuf to replenish the rx buffer. 1090 * If doing so fails we drop the rx'd frame so we 1091 * can reuse the previous mbuf. When we're able to 1092 * allocate a new mbuf dispatch the mbuf w/ rx'd 1093 * data up the stack and replace it with the newly 1094 * allocated one. 1095 */ 1096 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1097 if (m != NULL) { 1098 struct mbuf *mrx = npe->ix_m; 1099 struct npehwbuf *hw = npe->ix_hw; 1100 struct ifnet *ifp = sc->sc_ifp; 1101 1102 /* Flush mbuf memory for rx'd data */ 1103 bus_dmamap_sync(dma->mtag, npe->ix_map, 1104 BUS_DMASYNC_POSTREAD); 1105 1106 /* XXX flush hw buffer; works now 'cuz coherent */ 1107 /* set m_len etc. per rx frame size */ 1108 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1109 mrx->m_pkthdr.len = mrx->m_len; 1110 mrx->m_pkthdr.rcvif = ifp; 1111 mrx->m_flags |= M_HASFCS; 1112 1113 ifp->if_ipackets++; 1114 ifp->if_input(ifp, mrx); 1115 } else { 1116 /* discard frame and re-use mbuf */ 1117 m = npe->ix_m; 1118 } 1119 if (npe_rxbuf_init(sc, npe, m) == 0) { 1120 /* return npe buf to rx free list */ 1121 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1122 } else { 1123 /* XXX should not happen */ 1124 } 1125 } 1126#undef P2V 1127} 1128 1129#ifdef DEVICE_POLLING 1130static void 1131npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1132{ 1133 struct npe_softc *sc = ifp->if_softc; 1134 1135 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1136 npe_rxdone(sc->rx_qid, sc); 1137 npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1138 } 1139} 1140#endif /* DEVICE_POLLING */ 1141 1142static void 1143npe_startxmit(struct npe_softc *sc) 1144{ 1145 struct npedma *dma = &sc->txdma; 1146 int i; 1147 1148 NPE_ASSERT_LOCKED(sc); 1149 sc->tx_free = NULL; 1150 for (i = 0; i < dma->nbuf; i++) { 1151 struct npebuf *npe = &dma->buf[i]; 1152 if (npe->ix_m != NULL) { 1153 /* NB: should not happen */ 1154 device_printf(sc->sc_dev, 1155 "%s: free mbuf at entry %u\n", __func__, i); 1156 m_freem(npe->ix_m); 1157 } 1158 npe->ix_m = NULL; 1159 npe->ix_next = sc->tx_free; 1160 sc->tx_free = npe; 1161 } 1162} 1163 1164static void 1165npe_startrecv(struct npe_softc *sc) 1166{ 1167 struct npedma *dma = &sc->rxdma; 1168 struct npebuf *npe; 1169 int i; 1170 1171 NPE_ASSERT_LOCKED(sc); 1172 for (i = 0; i < dma->nbuf; i++) { 1173 npe = &dma->buf[i]; 1174 npe_rxbuf_init(sc, npe, npe->ix_m); 1175 /* set npe buf on rx free list */ 1176 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1177 } 1178} 1179 1180/* 1181 * Reset and initialize the chip 1182 */ 1183static void 1184npeinit_locked(void *xsc) 1185{ 1186 struct npe_softc *sc = xsc; 1187 struct ifnet *ifp = sc->sc_ifp; 1188 1189 NPE_ASSERT_LOCKED(sc); 1190if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1191 1192 /* 1193 * Reset MAC core. 1194 */ 1195 npe_mac_reset(sc); 1196 1197 /* disable transmitter and reciver in the MAC */ 1198 WR4(sc, NPE_MAC_RX_CNTRL1, 1199 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1200 WR4(sc, NPE_MAC_TX_CNTRL1, 1201 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1202 1203 /* 1204 * Set the MAC core registers. 1205 */ 1206 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1207 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1208 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1209 /* thresholds determined by NPE firmware FS */ 1210 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1211 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1212 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1213 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1214 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1215 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1216 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1217 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1218 1219 WR4(sc, NPE_MAC_TX_CNTRL1, 1220 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1221 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1222 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1223 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1224 /* XXX pad strip? */ 1225 WR4(sc, NPE_MAC_RX_CNTRL1, 1226 NPE_RX_CNTRL1_CRC_EN /* include CRC/FCS */ 1227 | NPE_RX_CNTRL1_PAUSE_EN); /* ena pause frame handling */ 1228 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1229 1230 npe_setmac(sc, IF_LLADDR(ifp)); 1231 npe_setmcast(sc); 1232 1233 npe_startxmit(sc); 1234 npe_startrecv(sc); 1235 1236 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1237 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1238 sc->npe_watchdog_timer = 0; /* just in case */ 1239 1240 /* enable transmitter and reciver in the MAC */ 1241 WR4(sc, NPE_MAC_RX_CNTRL1, 1242 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1243 WR4(sc, NPE_MAC_TX_CNTRL1, 1244 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1245 1246 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1247} 1248 1249static void 1250npeinit(void *xsc) 1251{ 1252 struct npe_softc *sc = xsc; 1253 NPE_LOCK(sc); 1254 npeinit_locked(sc); 1255 NPE_UNLOCK(sc); 1256} 1257 1258/* 1259 * Dequeue packets and place on the h/w transmit queue. 1260 */ 1261static void 1262npestart_locked(struct ifnet *ifp) 1263{ 1264 struct npe_softc *sc = ifp->if_softc; 1265 struct npebuf *npe; 1266 struct npehwbuf *hw; 1267 struct mbuf *m, *n; 1268 struct npedma *dma = &sc->txdma; 1269 bus_dma_segment_t segs[NPE_MAXSEG]; 1270 int nseg, len, error, i; 1271 uint32_t next; 1272 1273 NPE_ASSERT_LOCKED(sc); 1274 /* XXX can this happen? */ 1275 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1276 return; 1277 1278 while (sc->tx_free != NULL) { 1279 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1280 if (m == NULL) { 1281 /* XXX? */ 1282 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1283 return; 1284 } 1285 npe = sc->tx_free; 1286 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1287 m, segs, &nseg, 0); 1288 if (error == EFBIG) { 1289 n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG); 1290 if (n == NULL) { 1291 if_printf(ifp, "%s: too many fragments %u\n", 1292 __func__, nseg); 1293 m_freem(m); 1294 return; /* XXX? */ 1295 } 1296 m = n; 1297 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1298 m, segs, &nseg, 0); 1299 } 1300 if (error != 0 || nseg == 0) { 1301 if_printf(ifp, "%s: error %u nseg %u\n", 1302 __func__, error, nseg); 1303 m_freem(m); 1304 return; /* XXX? */ 1305 } 1306 sc->tx_free = npe->ix_next; 1307 1308 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1309 1310 /* 1311 * Tap off here if there is a bpf listener. 1312 */ 1313 BPF_MTAP(ifp, m); 1314 1315 npe->ix_m = m; 1316 hw = npe->ix_hw; 1317 len = m->m_pkthdr.len; 1318 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1319 for (i = 0; i < nseg; i++) { 1320 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1321 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1322 hw->ix_ne[i].next = htobe32(next); 1323 1324 len = 0; /* zero for segments > 1 */ 1325 next += sizeof(hw->ix_ne[0]); 1326 } 1327 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1328 /* XXX flush descriptor instead of using uncached memory */ 1329 1330 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1331 __func__, sc->tx_qid, npe->ix_neaddr, 1332 hw->ix_ne[0].data, hw->ix_ne[0].len); 1333 /* stick it on the tx q */ 1334 /* XXX add vlan priority */ 1335 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1336 1337 sc->npe_watchdog_timer = 5; 1338 } 1339 if (sc->tx_free == NULL) 1340 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1341} 1342 1343void 1344npestart(struct ifnet *ifp) 1345{ 1346 struct npe_softc *sc = ifp->if_softc; 1347 NPE_LOCK(sc); 1348 npestart_locked(ifp); 1349 NPE_UNLOCK(sc); 1350} 1351 1352static void 1353npe_stopxmit(struct npe_softc *sc) 1354{ 1355 struct npedma *dma = &sc->txdma; 1356 int i; 1357 1358 NPE_ASSERT_LOCKED(sc); 1359 1360 /* XXX qmgr */ 1361 for (i = 0; i < dma->nbuf; i++) { 1362 struct npebuf *npe = &dma->buf[i]; 1363 1364 if (npe->ix_m != NULL) { 1365 bus_dmamap_unload(dma->mtag, npe->ix_map); 1366 m_freem(npe->ix_m); 1367 npe->ix_m = NULL; 1368 } 1369 } 1370} 1371 1372static void 1373npe_stoprecv(struct npe_softc *sc) 1374{ 1375 struct npedma *dma = &sc->rxdma; 1376 int i; 1377 1378 NPE_ASSERT_LOCKED(sc); 1379 1380 /* XXX qmgr */ 1381 for (i = 0; i < dma->nbuf; i++) { 1382 struct npebuf *npe = &dma->buf[i]; 1383 1384 if (npe->ix_m != NULL) { 1385 bus_dmamap_unload(dma->mtag, npe->ix_map); 1386 m_freem(npe->ix_m); 1387 npe->ix_m = NULL; 1388 } 1389 } 1390} 1391 1392/* 1393 * Turn off interrupts, and stop the nic. 1394 */ 1395void 1396npestop(struct npe_softc *sc) 1397{ 1398 struct ifnet *ifp = sc->sc_ifp; 1399 1400 /* disable transmitter and reciver in the MAC */ 1401 WR4(sc, NPE_MAC_RX_CNTRL1, 1402 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1403 WR4(sc, NPE_MAC_TX_CNTRL1, 1404 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1405 1406 sc->npe_watchdog_timer = 0; 1407 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1408 1409 callout_stop(&sc->tick_ch); 1410 1411 npe_stopxmit(sc); 1412 npe_stoprecv(sc); 1413 /* XXX go into loopback & drain q's? */ 1414 /* XXX but beware of disabling tx above */ 1415 1416 /* 1417 * The MAC core rx/tx disable may leave the MAC hardware in an 1418 * unpredictable state. A hw reset is executed before resetting 1419 * all the MAC parameters to a known value. 1420 */ 1421 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1422 DELAY(NPE_MAC_RESET_DELAY); 1423 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1424 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1425} 1426 1427void 1428npewatchdog(struct npe_softc *sc) 1429{ 1430 NPE_ASSERT_LOCKED(sc); 1431 1432 if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1433 return; 1434 1435 device_printf(sc->sc_dev, "watchdog timeout\n"); 1436 sc->sc_ifp->if_oerrors++; 1437 1438 npeinit_locked(sc); 1439} 1440 1441static int 1442npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1443{ 1444 struct npe_softc *sc = ifp->if_softc; 1445 struct mii_data *mii; 1446 struct ifreq *ifr = (struct ifreq *)data; 1447 int error = 0; 1448#ifdef DEVICE_POLLING 1449 int mask; 1450#endif 1451 1452 switch (cmd) { 1453 case SIOCSIFFLAGS: 1454 NPE_LOCK(sc); 1455 if ((ifp->if_flags & IFF_UP) == 0 && 1456 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1457 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1458 npestop(sc); 1459 } else { 1460 /* reinitialize card on any parameter change */ 1461 npeinit_locked(sc); 1462 } 1463 NPE_UNLOCK(sc); 1464 break; 1465 1466 case SIOCADDMULTI: 1467 case SIOCDELMULTI: 1468 /* update multicast filter list. */ 1469 NPE_LOCK(sc); 1470 npe_setmcast(sc); 1471 NPE_UNLOCK(sc); 1472 error = 0; 1473 break; 1474 1475 case SIOCSIFMEDIA: 1476 case SIOCGIFMEDIA: 1477 mii = device_get_softc(sc->sc_mii); 1478 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1479 break; 1480 1481#ifdef DEVICE_POLLING 1482 case SIOCSIFCAP: 1483 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1484 if (mask & IFCAP_POLLING) { 1485 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1486 error = ether_poll_register(npe_poll, ifp); 1487 if (error) 1488 return error; 1489 NPE_LOCK(sc); 1490 /* disable callbacks XXX txdone is shared */ 1491 ixpqmgr_notify_disable(sc->rx_qid); 1492 ixpqmgr_notify_disable(sc->tx_doneqid); 1493 ifp->if_capenable |= IFCAP_POLLING; 1494 NPE_UNLOCK(sc); 1495 } else { 1496 error = ether_poll_deregister(ifp); 1497 /* NB: always enable qmgr callbacks */ 1498 NPE_LOCK(sc); 1499 /* enable qmgr callbacks */ 1500 ixpqmgr_notify_enable(sc->rx_qid, 1501 IX_QMGR_Q_SOURCE_ID_NOT_E); 1502 ixpqmgr_notify_enable(sc->tx_doneqid, 1503 IX_QMGR_Q_SOURCE_ID_NOT_E); 1504 ifp->if_capenable &= ~IFCAP_POLLING; 1505 NPE_UNLOCK(sc); 1506 } 1507 } 1508 break; 1509#endif 1510 default: 1511 error = ether_ioctl(ifp, cmd, data); 1512 break; 1513 } 1514 return error; 1515} 1516 1517/* 1518 * Setup a traffic class -> rx queue mapping. 1519 */ 1520static int 1521npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1522{ 1523 uint32_t msg[2]; 1524 1525 msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1526 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1527 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1528} 1529 1530static int 1531npe_setfirewallmode(struct npe_softc *sc, int onoff) 1532{ 1533 uint32_t msg[2]; 1534 1535 /* XXX honor onoff */ 1536 msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1537 msg[1] = 0; 1538 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1539} 1540 1541/* 1542 * Update and reset the statistics in the NPE. 1543 */ 1544static int 1545npe_updatestats(struct npe_softc *sc) 1546{ 1547 uint32_t msg[2]; 1548 1549 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1550 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1551 return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1552} 1553 1554#if 0 1555/* 1556 * Get the current statistics block. 1557 */ 1558static int 1559npe_getstats(struct npe_softc *sc) 1560{ 1561 uint32_t msg[2]; 1562 1563 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1564 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1565 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1566} 1567 1568/* 1569 * Query the image id of the loaded firmware. 1570 */ 1571static uint32_t 1572npe_getimageid(struct npe_softc *sc) 1573{ 1574 uint32_t msg[2]; 1575 1576 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1577 msg[1] = 0; 1578 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1579} 1580 1581/* 1582 * Enable/disable loopback. 1583 */ 1584static int 1585npe_setloopback(struct npe_softc *sc, int ena) 1586{ 1587 uint32_t msg[2]; 1588 1589 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1590 msg[1] = 0; 1591 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1592} 1593#endif 1594 1595static void 1596npe_child_detached(device_t dev, device_t child) 1597{ 1598 struct npe_softc *sc; 1599 1600 sc = device_get_softc(dev); 1601 if (child == sc->sc_mii) 1602 sc->sc_mii = NULL; 1603} 1604 1605/* 1606 * MII bus support routines. 1607 */ 1608#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1609#define MII_WR4(sc, reg, v) \ 1610 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1611 1612static uint32_t 1613npe_mii_mdio_read(struct npe_softc *sc, int reg) 1614{ 1615 uint32_t v; 1616 1617 /* NB: registers are known to be sequential */ 1618 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1619 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1620 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1621 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1622 return v; 1623} 1624 1625static void 1626npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1627{ 1628 /* NB: registers are known to be sequential */ 1629 MII_WR4(sc, reg+0, cmd & 0xff); 1630 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1631 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1632 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1633} 1634 1635static int 1636npe_mii_mdio_wait(struct npe_softc *sc) 1637{ 1638 uint32_t v; 1639 int i; 1640 1641 /* NB: typically this takes 25-30 trips */ 1642 for (i = 0; i < 1000; i++) { 1643 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1644 if ((v & NPE_MII_GO) == 0) 1645 return 1; 1646 DELAY(1); 1647 } 1648 device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1649 __func__, v); 1650 return 0; /* NB: timeout */ 1651} 1652 1653static int 1654npe_miibus_readreg(device_t dev, int phy, int reg) 1655{ 1656 struct npe_softc *sc = device_get_softc(dev); 1657 uint32_t v; 1658 1659 if (phy != sc->sc_phy) /* XXX no auto-detect */ 1660 return 0xffff; 1661 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1662 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1663 if (npe_mii_mdio_wait(sc)) 1664 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1665 else 1666 v = 0xffff | NPE_MII_READ_FAIL; 1667 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1668} 1669 1670static void 1671npe_miibus_writereg(device_t dev, int phy, int reg, int data) 1672{ 1673 struct npe_softc *sc = device_get_softc(dev); 1674 uint32_t v; 1675 1676 if (phy != sc->sc_phy) /* XXX */ 1677 return; 1678 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1679 | data | NPE_MII_WRITE 1680 | NPE_MII_GO; 1681 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1682 /* XXX complain about timeout */ 1683 (void) npe_mii_mdio_wait(sc); 1684} 1685 1686static void 1687npe_miibus_statchg(device_t dev) 1688{ 1689 struct npe_softc *sc = device_get_softc(dev); 1690 struct mii_data *mii = device_get_softc(sc->sc_mii); 1691 uint32_t tx1, rx1; 1692 1693 /* sync MAC duplex state */ 1694 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1695 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1696 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1697 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1698 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1699 } else { 1700 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1701 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1702 } 1703 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1704 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1705} 1706 1707static device_method_t npe_methods[] = { 1708 /* Device interface */ 1709 DEVMETHOD(device_probe, npe_probe), 1710 DEVMETHOD(device_attach, npe_attach), 1711 DEVMETHOD(device_detach, npe_detach), 1712 1713 /* Bus interface */ 1714 DEVMETHOD(bus_child_detached, npe_child_detached), 1715 1716 /* MII interface */ 1717 DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1718 DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1719 DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1720 1721 { 0, 0 } 1722}; 1723 1724static driver_t npe_driver = { 1725 "npe", 1726 npe_methods, 1727 sizeof(struct npe_softc), 1728}; 1729 1730DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1731DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1732MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1733MODULE_DEPEND(npe, miibus, 1, 1, 1); 1734MODULE_DEPEND(npe, ether, 1, 1, 1); 1735