1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3239281Sgonzo * All rights reserved. 4239281Sgonzo * 5239281Sgonzo * Redistribution and use in source and binary forms, with or without 6239281Sgonzo * modification, are permitted provided that the following conditions 7239281Sgonzo * are met: 8239281Sgonzo * 1. Redistributions of source code must retain the above copyright 9239281Sgonzo * notice, this list of conditions and the following disclaimer. 10239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11239281Sgonzo * notice, this list of conditions and the following disclaimer in the 12239281Sgonzo * documentation and/or other materials provided with the distribution. 13239281Sgonzo * 14239281Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24239281Sgonzo * SUCH DAMAGE. 25239281Sgonzo * 26239281Sgonzo * $FreeBSD$ 27239281Sgonzo */ 28239281Sgonzo 29239281Sgonzo#ifndef _IF_CPSWVAR_H 30239281Sgonzo#define _IF_CPSWVAR_H 31239281Sgonzo 32239281Sgonzo#define CPSW_INTR_COUNT 4 33239281Sgonzo 34239281Sgonzo/* MII BUS */ 35239281Sgonzo#define CPSW_MIIBUS_RETRIES 5 36239281Sgonzo#define CPSW_MIIBUS_DELAY 1000 37239281Sgonzo 38239281Sgonzo#define CPSW_MAX_ALE_ENTRIES 1024 39239281Sgonzo 40246276Skientzle#define CPSW_SYSCTL_COUNT 34 41246276Skientzle 42244939Skientzlestruct cpsw_slot { 43246276Skientzle uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */ 44244939Skientzle bus_dmamap_t dmamap; 45244939Skientzle struct mbuf *mbuf; 46244939Skientzle STAILQ_ENTRY(cpsw_slot) next; 47244939Skientzle}; 48246276SkientzleSTAILQ_HEAD(cpsw_slots, cpsw_slot); 49244939Skientzle 50246276Skientzlestruct cpsw_queue { 51246276Skientzle struct mtx lock; 52246276Skientzle int running; 53246276Skientzle struct cpsw_slots active; 54246276Skientzle struct cpsw_slots avail; 55246276Skientzle uint32_t queue_adds; /* total bufs added */ 56246276Skientzle uint32_t queue_removes; /* total bufs removed */ 57246276Skientzle uint32_t queue_removes_at_last_tick; /* Used by watchdog */ 58246276Skientzle int queue_slots; 59246276Skientzle int active_queue_len; 60246276Skientzle int max_active_queue_len; 61246276Skientzle int avail_queue_len; 62246276Skientzle int max_avail_queue_len; 63246276Skientzle int longest_chain; /* Largest # segments in a single packet. */ 64246276Skientzle int hdp_offset; 65246276Skientzle}; 66246276Skientzle 67239281Sgonzostruct cpsw_softc { 68239281Sgonzo struct ifnet *ifp; 69239281Sgonzo phandle_t node; 70239281Sgonzo device_t dev; 71246276Skientzle struct bintime attach_uptime; /* system uptime when attach happened. */ 72246276Skientzle struct bintime init_uptime; /* system uptime when init happened. */ 73246276Skientzle 74246276Skientzle /* TODO: We should set up a child structure for each port; 75246276Skientzle store mac, phy information, etc, in that structure. */ 76239281Sgonzo uint8_t mac_addr[ETHER_ADDR_LEN]; 77246276Skientzle 78239281Sgonzo device_t miibus; 79239281Sgonzo struct mii_data *mii; 80246276Skientzle /* We expect 1 memory resource and 4 interrupts from the device tree. */ 81246276Skientzle struct resource *res[1 + CPSW_INTR_COUNT]; 82239281Sgonzo 83246276Skientzle /* Interrupts get recorded here as we initialize them. */ 84246276Skientzle /* Interrupt teardown just walks this list. */ 85246276Skientzle struct { 86246276Skientzle struct resource *res; 87246276Skientzle void *ih_cookie; 88246276Skientzle const char *description; 89246276Skientzle } interrupts[CPSW_INTR_COUNT]; 90246276Skientzle int interrupt_count; 91246276Skientzle 92239281Sgonzo uint32_t cpsw_if_flags; 93239281Sgonzo int cpsw_media_status; 94239281Sgonzo 95246276Skientzle struct { 96246276Skientzle int resets; 97246276Skientzle int timer; 98246276Skientzle struct callout callout; 99246276Skientzle } watchdog; 100239281Sgonzo 101239281Sgonzo bus_dma_tag_t mbuf_dtag; 102239281Sgonzo 103246276Skientzle /* An mbuf full of nulls for TX padding. */ 104246276Skientzle bus_dmamap_t null_mbuf_dmamap; 105246276Skientzle struct mbuf *null_mbuf; 106246276Skientzle bus_addr_t null_mbuf_paddr; 107244939Skientzle 108246276Skientzle /* RX and TX buffer tracking */ 109246276Skientzle struct cpsw_queue rx, tx; 110244939Skientzle 111246276Skientzle /* 64-bit versions of 32-bit hardware statistics counters */ 112246276Skientzle uint64_t shadow_stats[CPSW_SYSCTL_COUNT]; 113239281Sgonzo 114246276Skientzle /* CPPI STATERAM has 512 slots for building TX/RX queues. */ 115246276Skientzle /* TODO: Size here supposedly varies with different versions 116246276Skientzle of the controller. Check DaVinci specs and find a good 117246276Skientzle way to adjust this. One option is to have a separate 118246276Skientzle Device Tree parameter for number slots; another option 119246276Skientzle is to calculate it from the memory size in the device tree. */ 120246276Skientzle struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)]; 121246276Skientzle struct cpsw_slots avail; 122239281Sgonzo}; 123239281Sgonzo 124239281Sgonzo#endif /*_IF_CPSWVAR_H */ 125