1183840Sraj/*- 2239277Sgonzo * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD$ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37183840Sraj#if defined(SOC_MV_DISCOVERY) 38183840Sraj#define IRQ_CAUSE_ERROR 0x0 39183840Sraj#define IRQ_CAUSE 0x4 40183840Sraj#define IRQ_CAUSE_HI 0x8 41183840Sraj#define IRQ_MASK_ERROR 0xC 42183840Sraj#define IRQ_MASK 0x10 43183840Sraj#define IRQ_MASK_HI 0x14 44183840Sraj#define IRQ_CAUSE_SELECT 0x18 45183840Sraj#define FIQ_MASK_ERROR 0x1C 46183840Sraj#define FIQ_MASK 0x20 47183840Sraj#define FIQ_MASK_HI 0x24 48183840Sraj#define FIQ_CAUSE_SELECT 0x28 49239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 50239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0x30 51239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x34 52183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 53239277Sgonzo#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 54183840Sraj#define IRQ_CAUSE 0x0 55183840Sraj#define IRQ_MASK 0x4 56183840Sraj#define FIQ_MASK 0x8 57239277Sgonzo#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 58239277Sgonzo#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 59239277Sgonzo#define IRQ_MASK_HI (-1) /* interrupt controller code */ 60239277Sgonzo#define FIQ_MASK_HI (-1) 61239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) (-1) 62239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 63239277Sgonzo#define IRQ_CAUSE_ERROR (-1) 64239277Sgonzo#define IRQ_MASK_ERROR (-1) 65239277Sgonzo#elif defined (SOC_MV_ARMADAXP) 66239277Sgonzo#define IRQ_CAUSE 0x18 67239277Sgonzo#define IRQ_MASK 0x30 68239277Sgonzo#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 69239277Sgonzo#define IRQ_CAUSE 0x0 70239277Sgonzo#define IRQ_MASK 0x4 71239277Sgonzo#define FIQ_MASK 0x8 72239277Sgonzo#define ENDPOINT_IRQ_MASK(n) 0xC 73183840Sraj#define IRQ_CAUSE_HI 0x10 74183840Sraj#define IRQ_MASK_HI 0x14 75183840Sraj#define FIQ_MASK_HI 0x18 76239277Sgonzo#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 77239277Sgonzo#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 78183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 79183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 80183840Sraj#endif 81183840Sraj 82239277Sgonzo#if defined(SOC_MV_FREY) 83239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x118 84239277Sgonzo#define IRQ_TIMER0 0x00000002 85239277Sgonzo#define IRQ_TIMER1 0x00000004 86239277Sgonzo#define IRQ_TIMER_WD 0x00000008 87239277Sgonzo 88239277Sgonzo#define BRIDGE_IRQ_MASK 0x11c 89239277Sgonzo#define IRQ_TIMER0_MASK 0x00000002 90239277Sgonzo#define IRQ_TIMER1_MASK 0x00000004 91239277Sgonzo#define IRQ_TIMER_WD_MASK 0x00000008 92239277Sgonzo#elif defined(SOC_MV_ARMADAXP) 93239277Sgonzo#define BRIDGE_IRQ_CAUSE 0x68 94239277Sgonzo#define IRQ_TIMER0 0x00000001 95239277Sgonzo#define IRQ_TIMER1 0x00000002 96239277Sgonzo#define IRQ_TIMER_WD 0x00000004 97239277Sgonzo#else 98183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 99183840Sraj#define IRQ_CPU_SELF 0x00000001 100183840Sraj#define IRQ_TIMER0 0x00000002 101183840Sraj#define IRQ_TIMER1 0x00000004 102183840Sraj#define IRQ_TIMER_WD 0x00000008 103183840Sraj 104183840Sraj#define BRIDGE_IRQ_MASK 0x14 105183840Sraj#define IRQ_CPU_MASK 0x00000001 106183840Sraj#define IRQ_TIMER0_MASK 0x00000002 107183840Sraj#define IRQ_TIMER1_MASK 0x00000004 108183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 109239277Sgonzo#endif 110183840Sraj 111239277Sgonzo#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 112239277Sgonzo#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 113239277Sgonzo#define IRQ_TIMER0_CLR IRQ_TIMER0 114239277Sgonzo#define IRQ_TIMER1_CLR IRQ_TIMER1 115239277Sgonzo#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 116239277Sgonzo#else 117239277Sgonzo#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 118239277Sgonzo#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119239277Sgonzo#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120239277Sgonzo#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121239277Sgonzo#endif 122239277Sgonzo 123183840Sraj/* 124183840Sraj * System reset 125183840Sraj */ 126240488Sgber#if defined(SOC_MV_ARMADAXP) 127240488Sgber#define RSTOUTn_MASK 0x60 128240488Sgber#define SYSTEM_SOFT_RESET 0x64 129240488Sgber#define WD_RSTOUTn_MASK 0x4 130240488Sgber#define WD_GLOBAL_MASK 0x00000100 131240488Sgber#define WD_CPU0_MASK 0x00000001 132240488Sgber#define SOFT_RST_OUT_EN 0x00000001 133240488Sgber#define SYS_SOFT_RST 0x00000001 134240488Sgber#else 135183840Sraj#define RSTOUTn_MASK 0x8 136183840Sraj#define WD_RST_OUT_EN 0x00000002 137183840Sraj#define SOFT_RST_OUT_EN 0x00000004 138183840Sraj#define SYSTEM_SOFT_RESET 0xc 139183840Sraj#define SYS_SOFT_RST 0x00000001 140240488Sgber#endif 141183840Sraj 142183840Sraj/* 143183840Sraj * Power Control 144183840Sraj */ 145266277Sian#if defined(SOC_MV_KIRKWOOD) 146266277Sian#define CPU_PM_CTRL 0x18 147266277Sian#else 148183840Sraj#define CPU_PM_CTRL 0x1C 149266277Sian#endif 150183840Sraj#define CPU_PM_CTRL_NONE 0 151196532Sraj#define CPU_PM_CTRL_ALL ~0x0 152183840Sraj 153183840Sraj#if defined(SOC_MV_KIRKWOOD) 154183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 155183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 156183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 157183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 158183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 159183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 160183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 161183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 162183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 163183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 164183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 165183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 166183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 167183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 168196532Sraj#define CPU_PM_CTRL_GE1 (1 << 19) 169196532Sraj#define CPU_PM_CTRL_TDM (1 << 20) 170196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 171196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 172196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 173209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 174209131Sraj (1 - (u))) 175209131Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 176183840Sraj#elif defined(SOC_MV_DISCOVERY) 177183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 178183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 179183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 180183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 181183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 182183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 183183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 184183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 185183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 186183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 187183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 188183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 189183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 190183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 191183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 192183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 193183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 194183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 195183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 196183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 197183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 198196532Sraj#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 199196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 200209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 201209131Sraj (1 - (u))) 202196532Sraj#else 203196532Sraj#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 204196532Sraj#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 205196532Sraj#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 206196532Sraj#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 207196532Sraj#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 208209131Sraj#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 209183840Sraj#endif 210183840Sraj 211183840Sraj/* 212183840Sraj * Timers 213183840Sraj */ 214239277Sgonzo#define CPU_TIMERS_BASE 0x300 215183840Sraj#define CPU_TIMER_CONTROL 0x0 216183840Sraj#define CPU_TIMER0_EN 0x00000001 217183840Sraj#define CPU_TIMER0_AUTO 0x00000002 218183840Sraj#define CPU_TIMER1_EN 0x00000004 219183840Sraj#define CPU_TIMER1_AUTO 0x00000008 220183840Sraj#define CPU_TIMER_WD_EN 0x00000010 221183840Sraj#define CPU_TIMER_WD_AUTO 0x00000020 222251371Sgber/* 25MHz mode is Armada XP - specific */ 223251371Sgber#define CPU_TIMER_WD_25MHZ_EN 0x00000400 224251371Sgber#define CPU_TIMER0_25MHZ_EN 0x00000800 225251371Sgber#define CPU_TIMER1_25MHZ_EN 0x00001000 226183840Sraj#define CPU_TIMER0_REL 0x10 227183840Sraj#define CPU_TIMER0 0x14 228183840Sraj 229183840Sraj/* 230194845Sraj * SATA 231194845Sraj */ 232194845Sraj#define SATA_CHAN_NUM 2 233194845Sraj 234194845Sraj#define EDMA_REGISTERS_OFFSET 0x2000 235194845Sraj#define EDMA_REGISTERS_SIZE 0x2000 236194845Sraj#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 237194845Sraj ((ch) * EDMA_REGISTERS_SIZE)) 238194845Sraj 239194845Sraj/* SATAHC registers */ 240194845Sraj#define SATA_CR 0x000 /* Configuration Reg. */ 241194845Sraj#define SATA_CR_NODMABS (1 << 8) 242194845Sraj#define SATA_CR_NOEDMABS (1 << 9) 243194845Sraj#define SATA_CR_NOPRDPBS (1 << 10) 244194845Sraj#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 245194845Sraj 246239277Sgonzo/* Interrupt Coalescing Threshold Reg. */ 247239277Sgonzo#define SATA_ICTR 0x00C 248239277Sgonzo#define SATA_ICTR_MAX ((1 << 8) - 1) 249239277Sgonzo 250239277Sgonzo/* Interrupt Time Threshold Reg. */ 251239277Sgonzo#define SATA_ITTR 0x010 252239277Sgonzo#define SATA_ITTR_MAX ((1 << 24) - 1) 253239277Sgonzo 254239277Sgonzo#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 255194845Sraj#define SATA_ICR_DMADONE(ch) (1 << (ch)) 256194845Sraj#define SATA_ICR_COAL (1 << 4) 257194845Sraj#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 258194845Sraj 259194845Sraj#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 260194845Sraj#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 261194845Sraj#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 262194845Sraj#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 263194845Sraj#define SATA_MICR_COAL (1 << 8) 264194845Sraj 265194845Sraj#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 266194845Sraj 267194845Sraj/* Shadow registers */ 268194845Sraj#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 269194845Sraj#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 270194845Sraj 271194845Sraj/* SATA registers */ 272194845Sraj#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 273194845Sraj#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 274194845Sraj#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 275194845Sraj#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 276194845Sraj 277194845Sraj/* EDMA registers */ 278194845Sraj#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 279194845Sraj#define SATA_EDMA_CFG_QL128 (1 << 19) 280194845Sraj#define SATA_EDMA_CFG_HQCACHE (1 << 22) 281194845Sraj 282194845Sraj#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 283194845Sraj 284194845Sraj#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 285194845Sraj#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 286194845Sraj#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 287194845Sraj#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 288194845Sraj#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 289194845Sraj#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 290194845Sraj#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 291194845Sraj 292194845Sraj#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 293194845Sraj#define SATA_EDMA_CMD_ENABLE (1 << 0) 294194845Sraj#define SATA_EDMA_CMD_DISABLE (1 << 1) 295194845Sraj#define SATA_EDMA_CMD_RESET (1 << 2) 296194845Sraj 297194845Sraj#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 298194845Sraj#define SATA_EDMA_STATUS_IDLE (1 << 7) 299194845Sraj 300194845Sraj/* Offset to extract input slot from REQIPR register */ 301194845Sraj#define SATA_EDMA_REQIS_OFS 5 302194845Sraj 303194845Sraj/* Offset to extract input slot from RESOPR register */ 304194845Sraj#define SATA_EDMA_RESOS_OFS 3 305194845Sraj 306194845Sraj/* 307183840Sraj * GPIO 308183840Sraj */ 309183840Sraj#define GPIO_DATA_OUT 0x00 310183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 311183840Sraj#define GPIO_BLINK_EN 0x08 312183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 313183840Sraj#define GPIO_DATA_IN 0x10 314183840Sraj#define GPIO_INT_CAUSE 0x14 315183840Sraj#define GPIO_INT_EDGE_MASK 0x18 316183840Sraj#define GPIO_INT_LEV_MASK 0x1c 317183840Sraj 318183840Sraj#define GPIO_HI_DATA_OUT 0x40 319183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 320183840Sraj#define GPIO_HI_BLINK_EN 0x48 321183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 322183840Sraj#define GPIO_HI_DATA_IN 0x50 323183840Sraj#define GPIO_HI_INT_CAUSE 0x54 324183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 325183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 326183840Sraj 327183840Sraj#define GPIO(n) (1 << (n)) 328183840Sraj#define MV_GPIO_MAX_NPINS 64 329183840Sraj 330209131Sraj#define MV_GPIO_IN_NONE 0x0 331209131Sraj#define MV_GPIO_IN_POL_LOW (1 << 16) 332209131Sraj#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 333209131Sraj#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 334209131Sraj#define MV_GPIO_OUT_NONE 0x0 335209131Sraj#define MV_GPIO_OUT_BLINK 0x1 336209131Sraj#define MV_GPIO_OUT_OPEN_DRAIN 0x2 337209131Sraj#define MV_GPIO_OUT_OPEN_SRC 0x4 338183840Sraj 339183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 340183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 341183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 342183840Sraj 343239277Sgonzo#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 344183840Sraj#define SAMPLE_AT_RESET 0x10 345186899Sraj#elif defined(SOC_MV_KIRKWOOD) 346183840Sraj#define SAMPLE_AT_RESET 0x30 347243580Smarcel#elif defined(SOC_MV_FREY) 348243580Smarcel#define SAMPLE_AT_RESET 0x100 349243580Smarcel#endif 350243580Smarcel#if defined(SOC_MV_DISCOVERY) 351186899Sraj#define SAMPLE_AT_RESET_LO 0x30 352186899Sraj#define SAMPLE_AT_RESET_HI 0x34 353239277Sgonzo#elif defined(SOC_MV_DOVE) 354239277Sgonzo#define SAMPLE_AT_RESET_LO 0x14 355239277Sgonzo#define SAMPLE_AT_RESET_HI 0x18 356240488Sgber#elif defined(SOC_MV_ARMADAXP) 357240488Sgber#define SAMPLE_AT_RESET_LO 0x30 358240488Sgber#define SAMPLE_AT_RESET_HI 0x34 359183840Sraj#endif 360183840Sraj 361183840Sraj/* 362183840Sraj * Clocks 363183840Sraj */ 364186899Sraj#if defined(SOC_MV_ORION) 365186899Sraj#define TCLK_MASK 0x00000300 366186899Sraj#define TCLK_SHIFT 0x08 367186899Sraj#elif defined(SOC_MV_DISCOVERY) 368186899Sraj#define TCLK_MASK 0x00000180 369186899Sraj#define TCLK_SHIFT 0x07 370239277Sgonzo#elif defined(SOC_MV_LOKIPLUS) 371239277Sgonzo#define TCLK_MASK 0x0000F000 372239277Sgonzo#define TCLK_SHIFT 0x0C 373183840Sraj#endif 374183840Sraj 375183840Sraj#define TCLK_100MHZ 100000000 376183840Sraj#define TCLK_125MHZ 125000000 377183840Sraj#define TCLK_133MHZ 133333333 378183840Sraj#define TCLK_150MHZ 150000000 379183840Sraj#define TCLK_166MHZ 166666667 380183840Sraj#define TCLK_200MHZ 200000000 381239277Sgonzo#define TCLK_250MHZ 250000000 382239277Sgonzo#define TCLK_300MHZ 300000000 383239277Sgonzo#define TCLK_667MHZ 667000000 384183840Sraj 385183840Sraj/* 386239277Sgonzo * CPU Cache Configuration 387239277Sgonzo */ 388239277Sgonzo 389239277Sgonzo#define CPU_CONFIG 0x00000000 390239277Sgonzo#define CPU_CONFIG_IC_PREF 0x00010000 391239277Sgonzo#define CPU_CONFIG_DC_PREF 0x00020000 392239277Sgonzo#define CPU_CONTROL 0x00000004 393239277Sgonzo#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 394239277Sgonzo#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 395239277Sgonzo#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 396239277Sgonzo#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 397239277Sgonzo 398239277Sgonzo/* 399239277Sgonzo * PCI Express port control (CPU Control registers) 400239277Sgonzo */ 401239277Sgonzo#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 402239277Sgonzo 403239277Sgonzo/* 404239277Sgonzo * Vendor ID 405239277Sgonzo */ 406239277Sgonzo#define PCI_VENDORID_MRVL 0x11AB 407239277Sgonzo#define PCI_VENDORID_MRVL2 0x1B4B 408239277Sgonzo 409239277Sgonzo/* 410183840Sraj * Chip ID 411183840Sraj */ 412191140Sraj#define MV_DEV_88F5181 0x5181 413191140Sraj#define MV_DEV_88F5182 0x5182 414191140Sraj#define MV_DEV_88F5281 0x5281 415191140Sraj#define MV_DEV_88F6281 0x6281 416239370Shrs#define MV_DEV_88F6282 0x6282 417239277Sgonzo#define MV_DEV_88F6781 0x6781 418191140Sraj#define MV_DEV_MV78100_Z0 0x6381 419191140Sraj#define MV_DEV_MV78100 0x7810 420239277Sgonzo#define MV_DEV_MV78130 0x7813 421239277Sgonzo#define MV_DEV_MV78160 0x7816 422239277Sgonzo#define MV_DEV_MV78230 0x7823 423239277Sgonzo#define MV_DEV_MV78260 0x7826 424239277Sgonzo#define MV_DEV_MV78460 0x7846 425239277Sgonzo#define MV_DEV_88RC8180 0x8180 426239277Sgonzo#define MV_DEV_88RC9480 0x9480 427239277Sgonzo#define MV_DEV_88RC9580 0x9580 428183840Sraj 429239277Sgonzo#define MV_DEV_FAMILY_MASK 0xff00 430239277Sgonzo#define MV_DEV_DISCOVERY 0x7800 431239277Sgonzo 432239277Sgonzo/* 433239277Sgonzo * Doorbell register control 434239277Sgonzo */ 435239277Sgonzo#define MV_DRBL_PCIE_TO_CPU 0 436239277Sgonzo#define MV_DRBL_CPU_TO_PCIE 1 437239277Sgonzo 438239277Sgonzo#if defined(SOC_MV_FREY) 439239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 440239277Sgonzo#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 441239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 442239277Sgonzo#else 443239277Sgonzo#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 444239277Sgonzo#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 445239277Sgonzo#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 446239277Sgonzo#endif 447183840Sraj#endif /* _MVREG_H_ */ 448