vf_dcu4.c revision 261413
1261413Sbr/*- 2261413Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3261413Sbr * All rights reserved. 4261413Sbr * 5261413Sbr * Redistribution and use in source and binary forms, with or without 6261413Sbr * modification, are permitted provided that the following conditions 7261413Sbr * are met: 8261413Sbr * 1. Redistributions of source code must retain the above copyright 9261413Sbr * notice, this list of conditions and the following disclaimer. 10261413Sbr * 2. Redistributions in binary form must reproduce the above copyright 11261413Sbr * notice, this list of conditions and the following disclaimer in the 12261413Sbr * documentation and/or other materials provided with the distribution. 13261413Sbr * 14261413Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15261413Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16261413Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17261413Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18261413Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19261413Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20261413Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21261413Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22261413Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23261413Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24261413Sbr * SUCH DAMAGE. 25261413Sbr */ 26261413Sbr 27261413Sbr/* 28261413Sbr * Vybrid Family Display Control Unit (DCU4) 29261413Sbr * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 30261413Sbr */ 31261413Sbr 32261413Sbr#include <sys/cdefs.h> 33261413Sbr__FBSDID("$FreeBSD: head/sys/arm/freescale/vybrid/vf_dcu4.c 261413 2014-02-02 20:25:27Z br $"); 34261413Sbr 35261413Sbr#include <sys/param.h> 36261413Sbr#include <sys/systm.h> 37261413Sbr#include <sys/bus.h> 38261413Sbr#include <sys/kernel.h> 39261413Sbr#include <sys/module.h> 40261413Sbr#include <sys/malloc.h> 41261413Sbr#include <sys/rman.h> 42261413Sbr#include <sys/timeet.h> 43261413Sbr#include <sys/timetc.h> 44261413Sbr#include <sys/watchdog.h> 45261413Sbr#include <sys/fbio.h> 46261413Sbr#include <sys/consio.h> 47261413Sbr#include <sys/eventhandler.h> 48261413Sbr 49261413Sbr#include <dev/fdt/fdt_common.h> 50261413Sbr#include <dev/ofw/openfirm.h> 51261413Sbr#include <dev/ofw/ofw_bus.h> 52261413Sbr#include <dev/ofw/ofw_bus_subr.h> 53261413Sbr 54261413Sbr#include <dev/vt/vt.h> 55261413Sbr#include <dev/vt/colors/vt_termcolors.h> 56261413Sbr 57261413Sbr#include <machine/bus.h> 58261413Sbr#include <machine/fdt.h> 59261413Sbr#include <machine/cpu.h> 60261413Sbr#include <machine/intr.h> 61261413Sbr 62261413Sbr#include "fb_if.h" 63261413Sbr 64261413Sbr#include <arm/freescale/vybrid/vf_common.h> 65261413Sbr 66261413Sbr#define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 67261413Sbr#define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 68261413Sbr#define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 69261413Sbr#define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 70261413Sbr#define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 71261413Sbr#define DCU_MODE_M 0x3 72261413Sbr#define DCU_MODE_S 0 73261413Sbr#define DCU_MODE_NORMAL 0x1 74261413Sbr#define DCU_MODE_TEST 0x2 75261413Sbr#define DCU_MODE_COLBAR 0x3 76261413Sbr#define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 77261413Sbr#define DCU_BGND 0x014 /* Background */ 78261413Sbr#define DCU_DISP_SIZE 0x018 /* Display Size */ 79261413Sbr#define DELTA_M 0x7ff 80261413Sbr#define DELTA_Y_S 16 81261413Sbr#define DELTA_X_S 0 82261413Sbr#define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 83261413Sbr#define BP_H_SHIFT 22 84261413Sbr#define PW_H_SHIFT 11 85261413Sbr#define FP_H_SHIFT 0 86261413Sbr#define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 87261413Sbr#define BP_V_SHIFT 22 88261413Sbr#define PW_V_SHIFT 11 89261413Sbr#define FP_V_SHIFT 0 90261413Sbr#define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 91261413Sbr#define INV_HS (1 << 0) 92261413Sbr#define INV_VS (1 << 1) 93261413Sbr#define DCU_THRESHOLD 0x028 /* Threshold */ 94261413Sbr#define LS_BF_VS_SHIFT 16 95261413Sbr#define OUT_BUF_HIGH_SHIFT 8 96261413Sbr#define OUT_BUF_LOW_SHIFT 0 97261413Sbr#define DCU_INT_STATUS 0x02C /* Interrupt Status */ 98261413Sbr#define DCU_INT_MASK 0x030 /* Interrupt Mask */ 99261413Sbr#define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 100261413Sbr#define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 101261413Sbr#define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 102261413Sbr#define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 103261413Sbr#define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 104261413Sbr#define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 105261413Sbr#define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 106261413Sbr#define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 107261413Sbr#define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 108261413Sbr#define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 109261413Sbr#define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 110261413Sbr#define DCU_CRC_VAL 0x060 /* CRC Value */ 111261413Sbr#define DCU_PDI_STATUS 0x064 /* PDI Status */ 112261413Sbr#define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 113261413Sbr#define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 114261413Sbr#define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 115261413Sbr#define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 116261413Sbr#define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 117261413Sbr#define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 118261413Sbr#define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 119261413Sbr#define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 120261413Sbr#define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 121261413Sbr#define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 122261413Sbr#define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 123261413Sbr#define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 124261413Sbr#define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 125261413Sbr#define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 126261413Sbr#define DCU_CRC_POS 0x0B0 /* CRC Position */ 127261413Sbr#define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 128261413Sbr#define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 129261413Sbr#define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 130261413Sbr#define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 131261413Sbr#define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 132261413Sbr#define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 133261413Sbr#define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 134261413Sbr#define READREG (1 << 30) 135261413Sbr#define MODE (1 << 31) 136261413Sbr#define DCU_UNDERRUN 0x0D0 /* Underrun */ 137261413Sbr#define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 138261413Sbr#define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 139261413Sbr#define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 140261413Sbr#define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 141261413Sbr#define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 142261413Sbr#define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 143261413Sbr#define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 144261413Sbr#define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 145261413Sbr 146261413Sbr/* Control Descriptor */ 147261413Sbr#define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 148261413Sbr#define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 149261413Sbr#define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 150261413Sbr#define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 151261413Sbr#define TRANS_SHIFT 20 152261413Sbr#define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 153261413Sbr#define BPP_MASK 0xf /* Bit per pixel Mask */ 154261413Sbr#define BPP_SHIFT 16 /* Bit per pixel Shift */ 155261413Sbr#define BPP24 0x5 156261413Sbr#define EN_LAYER (1 << 31) /* Enable the layer */ 157261413Sbr#define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 158261413Sbr#define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 159261413Sbr#define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 160261413Sbr#define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 161261413Sbr#define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 162261413Sbr 163261413Sbr#define DISPLAY_WIDTH 480 164261413Sbr#define DISPLAY_HEIGHT 272 165261413Sbr 166261413Sbrstruct dcu_softc { 167261413Sbr struct resource *res[2]; 168261413Sbr bus_space_tag_t bst; 169261413Sbr bus_space_handle_t bsh; 170261413Sbr void *ih; 171261413Sbr device_t dev; 172261413Sbr device_t sc_fbd; /* fbd child */ 173261413Sbr struct fb_info sc_info; 174261413Sbr}; 175261413Sbr 176261413Sbrstatic struct resource_spec dcu_spec[] = { 177261413Sbr { SYS_RES_MEMORY, 0, RF_ACTIVE }, 178261413Sbr { SYS_RES_IRQ, 0, RF_ACTIVE }, 179261413Sbr { -1, 0 } 180261413Sbr}; 181261413Sbr 182261413Sbrstatic int 183261413Sbrdcu_probe(device_t dev) 184261413Sbr{ 185261413Sbr 186261413Sbr if (!ofw_bus_status_okay(dev)) 187261413Sbr return (ENXIO); 188261413Sbr 189261413Sbr if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 190261413Sbr return (ENXIO); 191261413Sbr 192261413Sbr device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 193261413Sbr return (BUS_PROBE_DEFAULT); 194261413Sbr} 195261413Sbr 196261413Sbrstatic void 197261413Sbrdcu_intr(void *arg) 198261413Sbr{ 199261413Sbr struct dcu_softc *sc; 200261413Sbr int reg; 201261413Sbr 202261413Sbr sc = arg; 203261413Sbr 204261413Sbr /* Ack interrupts */ 205261413Sbr reg = READ4(sc, DCU_INT_STATUS); 206261413Sbr WRITE4(sc, DCU_INT_STATUS, reg); 207261413Sbr 208261413Sbr /* TODO interrupt handler */ 209261413Sbr} 210261413Sbr 211261413Sbrstatic int 212261413Sbrdcu_init(struct dcu_softc *sc) 213261413Sbr{ 214261413Sbr int reg; 215261413Sbr 216261413Sbr /* Configure DCU */ 217261413Sbr reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 218261413Sbr reg |= (sc->sc_info.fb_width / 16); 219261413Sbr WRITE4(sc, DCU_DISP_SIZE, reg); 220261413Sbr 221261413Sbr /* TODO: export panel info to FDT */ 222261413Sbr 223261413Sbr reg = (2 << BP_H_SHIFT); 224261413Sbr reg |= (41 << PW_H_SHIFT); 225261413Sbr reg |= (2 << FP_H_SHIFT); 226261413Sbr WRITE4(sc, DCU_HSYN_PARA, reg); 227261413Sbr 228261413Sbr reg = (2 << BP_V_SHIFT); 229261413Sbr reg |= (10 << PW_V_SHIFT); 230261413Sbr reg |= (2 << FP_V_SHIFT); 231261413Sbr WRITE4(sc, DCU_VSYN_PARA, reg); 232261413Sbr 233261413Sbr WRITE4(sc, DCU_BGND, 0); 234261413Sbr WRITE4(sc, DCU_DIV_RATIO, 30); 235261413Sbr 236261413Sbr reg = (INV_VS | INV_HS); 237261413Sbr WRITE4(sc, DCU_SYNPOL, reg); 238261413Sbr 239261413Sbr reg = (0x3 << LS_BF_VS_SHIFT); 240261413Sbr reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 241261413Sbr reg |= (0 << OUT_BUF_LOW_SHIFT); 242261413Sbr WRITE4(sc, DCU_THRESHOLD, reg); 243261413Sbr 244261413Sbr /* Mask all the interrupts */ 245261413Sbr WRITE4(sc, DCU_INT_MASK, 0xffffffff); 246261413Sbr 247261413Sbr /* Setup first layer */ 248261413Sbr reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 249261413Sbr WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 250261413Sbr WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 251261413Sbr WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 252261413Sbr reg = (BPP24 << BPP_SHIFT); 253261413Sbr reg |= EN_LAYER; 254261413Sbr reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 255261413Sbr WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 256261413Sbr WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 257261413Sbr WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 258261413Sbr WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 259261413Sbr WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 260261413Sbr WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 261261413Sbr 262261413Sbr /* Enable DCU in normal mode */ 263261413Sbr reg = READ4(sc, DCU_DCU_MODE); 264261413Sbr reg &= ~(DCU_MODE_M << DCU_MODE_S); 265261413Sbr reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 266261413Sbr reg |= (RASTER_EN); 267261413Sbr WRITE4(sc, DCU_DCU_MODE, reg); 268261413Sbr WRITE4(sc, DCU_UPDATE_MODE, READREG); 269261413Sbr 270261413Sbr return (0); 271261413Sbr} 272261413Sbr 273261413Sbrstatic int 274261413Sbrdcu_attach(device_t dev) 275261413Sbr{ 276261413Sbr struct dcu_softc *sc; 277261413Sbr int err; 278261413Sbr 279261413Sbr sc = device_get_softc(dev); 280261413Sbr 281261413Sbr if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 282261413Sbr device_printf(dev, "could not allocate resources\n"); 283261413Sbr return (ENXIO); 284261413Sbr } 285261413Sbr 286261413Sbr /* Memory interface */ 287261413Sbr sc->bst = rman_get_bustag(sc->res[0]); 288261413Sbr sc->bsh = rman_get_bushandle(sc->res[0]); 289261413Sbr 290261413Sbr /* Setup interrupt handler */ 291261413Sbr err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 292261413Sbr NULL, dcu_intr, sc, &sc->ih); 293261413Sbr if (err) { 294261413Sbr device_printf(dev, "Unable to alloc interrupt resource.\n"); 295261413Sbr return (ENXIO); 296261413Sbr } 297261413Sbr 298261413Sbr /* Bypass timing control (used for raw lcd panels) */ 299261413Sbr tcon_bypass(); 300261413Sbr 301261413Sbr sc->sc_info.fb_width = DISPLAY_WIDTH; 302261413Sbr sc->sc_info.fb_height = DISPLAY_HEIGHT; 303261413Sbr sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 304261413Sbr sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 305261413Sbr sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 306261413Sbr sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 307261413Sbr M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 308261413Sbr sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 309261413Sbr 310261413Sbr#if 0 311261413Sbr printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 312261413Sbr sc->sc_info.fb_stride); 313261413Sbr printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 314261413Sbr#endif 315261413Sbr 316261413Sbr memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 317261413Sbr 318261413Sbr dcu_init(sc); 319261413Sbr 320261413Sbr sc->sc_info.fb_name = device_get_nameunit(dev); 321261413Sbr 322261413Sbr /* Ask newbus to attach framebuffer device to me. */ 323261413Sbr sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 324261413Sbr if (sc->sc_fbd == NULL) 325261413Sbr device_printf(dev, "Can't attach fbd device\n"); 326261413Sbr 327261413Sbr if (device_probe_and_attach(sc->sc_fbd) != 0) { 328261413Sbr device_printf(sc->dev, "Failed to attach fbd device\n"); 329261413Sbr } 330261413Sbr 331261413Sbr return (0); 332261413Sbr} 333261413Sbr 334261413Sbrstatic struct fb_info * 335261413Sbrdcu4_fb_getinfo(device_t dev) 336261413Sbr{ 337261413Sbr struct dcu_softc *sc = device_get_softc(dev); 338261413Sbr 339261413Sbr return (&sc->sc_info); 340261413Sbr} 341261413Sbr 342261413Sbrstatic device_method_t dcu_methods[] = { 343261413Sbr DEVMETHOD(device_probe, dcu_probe), 344261413Sbr DEVMETHOD(device_attach, dcu_attach), 345261413Sbr 346261413Sbr /* Framebuffer service methods */ 347261413Sbr DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 348261413Sbr { 0, 0 } 349261413Sbr}; 350261413Sbr 351261413Sbrstatic driver_t dcu_driver = { 352261413Sbr "fb", 353261413Sbr dcu_methods, 354261413Sbr sizeof(struct dcu_softc), 355261413Sbr}; 356261413Sbr 357261413Sbrstatic devclass_t dcu_devclass; 358261413Sbr 359261413SbrDRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0); 360