1261413Sbr/*- 2261413Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3261413Sbr * All rights reserved. 4261413Sbr * 5261413Sbr * Redistribution and use in source and binary forms, with or without 6261413Sbr * modification, are permitted provided that the following conditions 7261413Sbr * are met: 8261413Sbr * 1. Redistributions of source code must retain the above copyright 9261413Sbr * notice, this list of conditions and the following disclaimer. 10261413Sbr * 2. Redistributions in binary form must reproduce the above copyright 11261413Sbr * notice, this list of conditions and the following disclaimer in the 12261413Sbr * documentation and/or other materials provided with the distribution. 13261413Sbr * 14261413Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15261413Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16261413Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17261413Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18261413Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19261413Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20261413Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21261413Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22261413Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23261413Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24261413Sbr * SUCH DAMAGE. 25261413Sbr */ 26261413Sbr 27261413Sbr/* 28261413Sbr * Vybrid Family Display Control Unit (DCU4) 29261413Sbr * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 30261413Sbr */ 31261413Sbr 32261413Sbr#include <sys/cdefs.h> 33261413Sbr__FBSDID("$FreeBSD$"); 34261413Sbr 35261413Sbr#include <sys/param.h> 36261413Sbr#include <sys/systm.h> 37261413Sbr#include <sys/bus.h> 38261413Sbr#include <sys/kernel.h> 39261413Sbr#include <sys/module.h> 40261413Sbr#include <sys/malloc.h> 41261413Sbr#include <sys/rman.h> 42261413Sbr#include <sys/timeet.h> 43261413Sbr#include <sys/timetc.h> 44261413Sbr#include <sys/watchdog.h> 45261413Sbr#include <sys/fbio.h> 46261413Sbr#include <sys/consio.h> 47261413Sbr#include <sys/eventhandler.h> 48266274Sian#include <sys/gpio.h> 49261413Sbr 50261413Sbr#include <dev/fdt/fdt_common.h> 51261413Sbr#include <dev/ofw/openfirm.h> 52261413Sbr#include <dev/ofw/ofw_bus.h> 53261413Sbr#include <dev/ofw/ofw_bus_subr.h> 54261413Sbr 55261413Sbr#include <dev/vt/vt.h> 56261413Sbr#include <dev/vt/colors/vt_termcolors.h> 57261413Sbr 58266274Sian#include "gpio_if.h" 59266274Sian 60261413Sbr#include <machine/bus.h> 61261413Sbr#include <machine/fdt.h> 62261413Sbr#include <machine/cpu.h> 63261413Sbr#include <machine/intr.h> 64261413Sbr 65261413Sbr#include "fb_if.h" 66261413Sbr 67261413Sbr#include <arm/freescale/vybrid/vf_common.h> 68261413Sbr 69261413Sbr#define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 70261413Sbr#define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 71261413Sbr#define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 72261413Sbr#define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 73261413Sbr#define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 74261413Sbr#define DCU_MODE_M 0x3 75261413Sbr#define DCU_MODE_S 0 76261413Sbr#define DCU_MODE_NORMAL 0x1 77261413Sbr#define DCU_MODE_TEST 0x2 78261413Sbr#define DCU_MODE_COLBAR 0x3 79261413Sbr#define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 80266274Sian#define PDI_EN (1 << 13) 81266274Sian#define PDI_DE_MODE (1 << 11) 82266274Sian#define PDI_MODE_M 2 83261413Sbr#define DCU_BGND 0x014 /* Background */ 84261413Sbr#define DCU_DISP_SIZE 0x018 /* Display Size */ 85261413Sbr#define DELTA_M 0x7ff 86261413Sbr#define DELTA_Y_S 16 87261413Sbr#define DELTA_X_S 0 88261413Sbr#define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 89261413Sbr#define BP_H_SHIFT 22 90261413Sbr#define PW_H_SHIFT 11 91261413Sbr#define FP_H_SHIFT 0 92261413Sbr#define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 93261413Sbr#define BP_V_SHIFT 22 94261413Sbr#define PW_V_SHIFT 11 95261413Sbr#define FP_V_SHIFT 0 96261413Sbr#define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 97261413Sbr#define INV_HS (1 << 0) 98261413Sbr#define INV_VS (1 << 1) 99266274Sian#define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ 100266274Sian#define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ 101266274Sian#define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ 102261413Sbr#define DCU_THRESHOLD 0x028 /* Threshold */ 103261413Sbr#define LS_BF_VS_SHIFT 16 104261413Sbr#define OUT_BUF_HIGH_SHIFT 8 105261413Sbr#define OUT_BUF_LOW_SHIFT 0 106261413Sbr#define DCU_INT_STATUS 0x02C /* Interrupt Status */ 107261413Sbr#define DCU_INT_MASK 0x030 /* Interrupt Mask */ 108261413Sbr#define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 109261413Sbr#define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 110261413Sbr#define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 111261413Sbr#define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 112261413Sbr#define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 113261413Sbr#define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 114261413Sbr#define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 115261413Sbr#define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 116261413Sbr#define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 117261413Sbr#define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 118261413Sbr#define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 119261413Sbr#define DCU_CRC_VAL 0x060 /* CRC Value */ 120261413Sbr#define DCU_PDI_STATUS 0x064 /* PDI Status */ 121261413Sbr#define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 122261413Sbr#define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 123261413Sbr#define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 124261413Sbr#define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 125261413Sbr#define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 126261413Sbr#define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 127261413Sbr#define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 128261413Sbr#define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 129261413Sbr#define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 130261413Sbr#define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 131261413Sbr#define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 132261413Sbr#define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 133261413Sbr#define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 134261413Sbr#define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 135261413Sbr#define DCU_CRC_POS 0x0B0 /* CRC Position */ 136261413Sbr#define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 137261413Sbr#define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 138261413Sbr#define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 139261413Sbr#define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 140261413Sbr#define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 141261413Sbr#define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 142261413Sbr#define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 143261413Sbr#define READREG (1 << 30) 144261413Sbr#define MODE (1 << 31) 145261413Sbr#define DCU_UNDERRUN 0x0D0 /* Underrun */ 146261413Sbr#define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 147261413Sbr#define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 148261413Sbr#define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 149261413Sbr#define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 150261413Sbr#define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 151261413Sbr#define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 152261413Sbr#define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 153261413Sbr#define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 154261413Sbr 155261413Sbr/* Control Descriptor */ 156261413Sbr#define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 157261413Sbr#define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 158261413Sbr#define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 159261413Sbr#define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 160261413Sbr#define TRANS_SHIFT 20 161261413Sbr#define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 162261413Sbr#define BPP_MASK 0xf /* Bit per pixel Mask */ 163261413Sbr#define BPP_SHIFT 16 /* Bit per pixel Shift */ 164261413Sbr#define BPP24 0x5 165261413Sbr#define EN_LAYER (1 << 31) /* Enable the layer */ 166261413Sbr#define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 167261413Sbr#define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 168261413Sbr#define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 169261413Sbr#define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 170261413Sbr#define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 171261413Sbr 172266274Sian#define NUM_LAYERS 64 173261413Sbr 174266274Sianstruct panel_info { 175266274Sian uint32_t width; 176266274Sian uint32_t height; 177266274Sian uint32_t h_back_porch; 178266274Sian uint32_t h_pulse_width; 179266274Sian uint32_t h_front_porch; 180266274Sian uint32_t v_back_porch; 181266274Sian uint32_t v_pulse_width; 182266274Sian uint32_t v_front_porch; 183266274Sian uint32_t clk_div; 184266274Sian uint32_t backlight_pin; 185266274Sian}; 186266274Sian 187261413Sbrstruct dcu_softc { 188261413Sbr struct resource *res[2]; 189261413Sbr bus_space_tag_t bst; 190261413Sbr bus_space_handle_t bsh; 191261413Sbr void *ih; 192261413Sbr device_t dev; 193261413Sbr device_t sc_fbd; /* fbd child */ 194261413Sbr struct fb_info sc_info; 195266274Sian struct panel_info *panel; 196261413Sbr}; 197261413Sbr 198261413Sbrstatic struct resource_spec dcu_spec[] = { 199261413Sbr { SYS_RES_MEMORY, 0, RF_ACTIVE }, 200261413Sbr { SYS_RES_IRQ, 0, RF_ACTIVE }, 201261413Sbr { -1, 0 } 202261413Sbr}; 203261413Sbr 204261413Sbrstatic int 205261413Sbrdcu_probe(device_t dev) 206261413Sbr{ 207261413Sbr 208261413Sbr if (!ofw_bus_status_okay(dev)) 209261413Sbr return (ENXIO); 210261413Sbr 211261413Sbr if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 212261413Sbr return (ENXIO); 213261413Sbr 214261413Sbr device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 215261413Sbr return (BUS_PROBE_DEFAULT); 216261413Sbr} 217261413Sbr 218261413Sbrstatic void 219261413Sbrdcu_intr(void *arg) 220261413Sbr{ 221261413Sbr struct dcu_softc *sc; 222261413Sbr int reg; 223261413Sbr 224261413Sbr sc = arg; 225261413Sbr 226261413Sbr /* Ack interrupts */ 227261413Sbr reg = READ4(sc, DCU_INT_STATUS); 228261413Sbr WRITE4(sc, DCU_INT_STATUS, reg); 229261413Sbr 230261413Sbr /* TODO interrupt handler */ 231261413Sbr} 232261413Sbr 233261413Sbrstatic int 234266274Sianget_panel_info(struct dcu_softc *sc, struct panel_info *panel) 235266274Sian{ 236266274Sian phandle_t node; 237266274Sian pcell_t dts_value[3]; 238266274Sian int len; 239266274Sian 240266274Sian if ((node = ofw_bus_get_node(sc->dev)) == -1) 241266274Sian return (ENXIO); 242266274Sian 243266274Sian /* panel size */ 244266274Sian if ((len = OF_getproplen(node, "panel-size")) <= 0) 245266274Sian return (ENXIO); 246266274Sian OF_getprop(node, "panel-size", &dts_value, len); 247266274Sian panel->width = fdt32_to_cpu(dts_value[0]); 248266274Sian panel->height = fdt32_to_cpu(dts_value[1]); 249266274Sian 250266274Sian /* hsync */ 251266274Sian if ((len = OF_getproplen(node, "panel-hsync")) <= 0) 252266274Sian return (ENXIO); 253266274Sian OF_getprop(node, "panel-hsync", &dts_value, len); 254266274Sian panel->h_back_porch = fdt32_to_cpu(dts_value[0]); 255266274Sian panel->h_pulse_width = fdt32_to_cpu(dts_value[1]); 256266274Sian panel->h_front_porch = fdt32_to_cpu(dts_value[2]); 257266274Sian 258266274Sian /* vsync */ 259266274Sian if ((len = OF_getproplen(node, "panel-vsync")) <= 0) 260266274Sian return (ENXIO); 261266274Sian OF_getprop(node, "panel-vsync", &dts_value, len); 262266274Sian panel->v_back_porch = fdt32_to_cpu(dts_value[0]); 263266274Sian panel->v_pulse_width = fdt32_to_cpu(dts_value[1]); 264266274Sian panel->v_front_porch = fdt32_to_cpu(dts_value[2]); 265266274Sian 266266274Sian /* clk divider */ 267266274Sian if ((len = OF_getproplen(node, "panel-clk-div")) <= 0) 268266274Sian return (ENXIO); 269266274Sian OF_getprop(node, "panel-clk-div", &dts_value, len); 270266274Sian panel->clk_div = fdt32_to_cpu(dts_value[0]); 271266274Sian 272266274Sian /* backlight pin */ 273266274Sian if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0) 274266274Sian return (ENXIO); 275266274Sian OF_getprop(node, "panel-backlight-pin", &dts_value, len); 276266274Sian panel->backlight_pin = fdt32_to_cpu(dts_value[0]); 277266274Sian 278266274Sian return (0); 279266274Sian} 280266274Sian 281266274Sianstatic int 282261413Sbrdcu_init(struct dcu_softc *sc) 283261413Sbr{ 284266274Sian struct panel_info *panel; 285261413Sbr int reg; 286266274Sian int i; 287261413Sbr 288266274Sian panel = sc->panel; 289266274Sian 290261413Sbr /* Configure DCU */ 291261413Sbr reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 292261413Sbr reg |= (sc->sc_info.fb_width / 16); 293261413Sbr WRITE4(sc, DCU_DISP_SIZE, reg); 294261413Sbr 295266274Sian reg = (panel->h_back_porch << BP_H_SHIFT); 296266274Sian reg |= (panel->h_pulse_width << PW_H_SHIFT); 297266274Sian reg |= (panel->h_front_porch << FP_H_SHIFT); 298261413Sbr WRITE4(sc, DCU_HSYN_PARA, reg); 299261413Sbr 300266274Sian reg = (panel->v_back_porch << BP_V_SHIFT); 301266274Sian reg |= (panel->v_pulse_width << PW_V_SHIFT); 302266274Sian reg |= (panel->v_front_porch << FP_V_SHIFT); 303261413Sbr WRITE4(sc, DCU_VSYN_PARA, reg); 304261413Sbr 305261413Sbr WRITE4(sc, DCU_BGND, 0); 306266274Sian WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); 307261413Sbr 308261413Sbr reg = (INV_VS | INV_HS); 309261413Sbr WRITE4(sc, DCU_SYNPOL, reg); 310261413Sbr 311266274Sian /* TODO: export to panel info */ 312261413Sbr reg = (0x3 << LS_BF_VS_SHIFT); 313261413Sbr reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 314261413Sbr reg |= (0 << OUT_BUF_LOW_SHIFT); 315261413Sbr WRITE4(sc, DCU_THRESHOLD, reg); 316261413Sbr 317261413Sbr /* Mask all the interrupts */ 318261413Sbr WRITE4(sc, DCU_INT_MASK, 0xffffffff); 319261413Sbr 320266274Sian /* Reset all layers */ 321266274Sian for (i = 0; i < NUM_LAYERS; i++) { 322266274Sian WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0); 323266274Sian WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0); 324266274Sian WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0); 325266274Sian WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0); 326266274Sian WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0); 327266274Sian WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0); 328266274Sian WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0); 329266274Sian WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0); 330266274Sian WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0); 331266274Sian } 332266274Sian 333261413Sbr /* Setup first layer */ 334261413Sbr reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 335261413Sbr WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 336261413Sbr WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 337261413Sbr WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 338261413Sbr reg = (BPP24 << BPP_SHIFT); 339261413Sbr reg |= EN_LAYER; 340261413Sbr reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 341261413Sbr WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 342261413Sbr WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 343261413Sbr WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 344261413Sbr WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 345261413Sbr WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 346261413Sbr WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 347261413Sbr 348261413Sbr /* Enable DCU in normal mode */ 349261413Sbr reg = READ4(sc, DCU_DCU_MODE); 350261413Sbr reg &= ~(DCU_MODE_M << DCU_MODE_S); 351261413Sbr reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 352261413Sbr reg |= (RASTER_EN); 353261413Sbr WRITE4(sc, DCU_DCU_MODE, reg); 354261413Sbr WRITE4(sc, DCU_UPDATE_MODE, READREG); 355261413Sbr 356261413Sbr return (0); 357261413Sbr} 358261413Sbr 359261413Sbrstatic int 360261413Sbrdcu_attach(device_t dev) 361261413Sbr{ 362266274Sian struct panel_info panel; 363261413Sbr struct dcu_softc *sc; 364266274Sian device_t gpio_dev; 365261413Sbr int err; 366261413Sbr 367261413Sbr sc = device_get_softc(dev); 368266274Sian sc->dev = dev; 369261413Sbr 370261413Sbr if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 371261413Sbr device_printf(dev, "could not allocate resources\n"); 372261413Sbr return (ENXIO); 373261413Sbr } 374261413Sbr 375261413Sbr /* Memory interface */ 376261413Sbr sc->bst = rman_get_bustag(sc->res[0]); 377261413Sbr sc->bsh = rman_get_bushandle(sc->res[0]); 378261413Sbr 379261413Sbr /* Setup interrupt handler */ 380261413Sbr err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 381261413Sbr NULL, dcu_intr, sc, &sc->ih); 382261413Sbr if (err) { 383261413Sbr device_printf(dev, "Unable to alloc interrupt resource.\n"); 384261413Sbr return (ENXIO); 385261413Sbr } 386261413Sbr 387266274Sian if (get_panel_info(sc, &panel)) { 388266274Sian device_printf(dev, "Can't get panel info\n"); 389266274Sian return (ENXIO); 390266274Sian } 391266274Sian 392266274Sian sc->panel = &panel; 393266274Sian 394261413Sbr /* Bypass timing control (used for raw lcd panels) */ 395261413Sbr tcon_bypass(); 396261413Sbr 397266274Sian /* Get the GPIO device, we need this to give power to USB */ 398266274Sian gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 399266274Sian if (gpio_dev == NULL) { 400266274Sian device_printf(sc->dev, "Error: failed to get the GPIO dev\n"); 401266274Sian return (1); 402266274Sian } 403266274Sian 404266274Sian /* Turn on backlight */ 405266274Sian /* TODO: Use FlexTimer/PWM */ 406266274Sian GPIO_PIN_SETFLAGS(gpio_dev, panel.backlight_pin, GPIO_PIN_OUTPUT); 407266274Sian GPIO_PIN_SET(gpio_dev, panel.backlight_pin, GPIO_PIN_HIGH); 408266274Sian 409266274Sian sc->sc_info.fb_width = panel.width; 410266274Sian sc->sc_info.fb_height = panel.height; 411261413Sbr sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 412261413Sbr sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 413261413Sbr sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 414261413Sbr sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 415261413Sbr M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 416261413Sbr sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 417261413Sbr 418261413Sbr#if 0 419261413Sbr printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 420261413Sbr sc->sc_info.fb_stride); 421261413Sbr printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 422261413Sbr#endif 423261413Sbr 424261413Sbr memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 425261413Sbr 426261413Sbr dcu_init(sc); 427261413Sbr 428261413Sbr sc->sc_info.fb_name = device_get_nameunit(dev); 429261413Sbr 430261413Sbr /* Ask newbus to attach framebuffer device to me. */ 431261413Sbr sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 432261413Sbr if (sc->sc_fbd == NULL) 433261413Sbr device_printf(dev, "Can't attach fbd device\n"); 434261413Sbr 435261413Sbr if (device_probe_and_attach(sc->sc_fbd) != 0) { 436261413Sbr device_printf(sc->dev, "Failed to attach fbd device\n"); 437261413Sbr } 438261413Sbr 439261413Sbr return (0); 440261413Sbr} 441261413Sbr 442261413Sbrstatic struct fb_info * 443261413Sbrdcu4_fb_getinfo(device_t dev) 444261413Sbr{ 445261413Sbr struct dcu_softc *sc = device_get_softc(dev); 446261413Sbr 447261413Sbr return (&sc->sc_info); 448261413Sbr} 449261413Sbr 450261413Sbrstatic device_method_t dcu_methods[] = { 451261413Sbr DEVMETHOD(device_probe, dcu_probe), 452261413Sbr DEVMETHOD(device_attach, dcu_attach), 453261413Sbr 454261413Sbr /* Framebuffer service methods */ 455261413Sbr DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 456261413Sbr { 0, 0 } 457261413Sbr}; 458261413Sbr 459261413Sbrstatic driver_t dcu_driver = { 460261413Sbr "fb", 461261413Sbr dcu_methods, 462261413Sbr sizeof(struct dcu_softc), 463261413Sbr}; 464261413Sbr 465261413Sbrstatic devclass_t dcu_devclass; 466261413Sbr 467261413SbrDRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0); 468