uart_dev_at91usart.c revision 266207
1/*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 Olivier Houchard 4 * Copyright (c) 2012 Ian Lepore 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/arm/at91/uart_dev_at91usart.c 266207 2014-05-16 02:21:51Z ian $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/cons.h> 38#include <sys/tty.h> 39#include <machine/bus.h> 40 41#include <dev/uart/uart.h> 42#include <dev/uart/uart_cpu.h> 43#include <dev/uart/uart_bus.h> 44#include <arm/at91/at91_usartreg.h> 45#include <arm/at91/at91_pdcreg.h> 46#include <arm/at91/at91_piovar.h> 47#include <arm/at91/at91_pioreg.h> 48#include <arm/at91/at91rm92reg.h> 49#include <arm/at91/at91var.h> 50 51#include "uart_if.h" 52 53#define DEFAULT_RCLK at91_master_clock 54#define USART_DEFAULT_FIFO_BYTES 128 55 56#define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \ 57 USART_CSR_DSRIC | USART_CSR_RIIC) 58 59/* 60 * High-level UART interface. 61 */ 62struct at91_usart_rx { 63 bus_addr_t pa; 64 uint8_t *buffer; 65 bus_dmamap_t map; 66}; 67 68struct at91_usart_softc { 69 struct uart_softc base; 70 bus_dma_tag_t tx_tag; 71 bus_dmamap_t tx_map; 72 uint32_t flags; 73#define HAS_TIMEOUT 0x1 74#define USE_RTS0_WORKAROUND 0x2 75 bus_dma_tag_t rx_tag; 76 struct at91_usart_rx ping_pong[2]; 77 struct at91_usart_rx *ping; 78 struct at91_usart_rx *pong; 79}; 80 81#define RD4(bas, reg) \ 82 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 83#define WR4(bas, reg, value) \ 84 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 85 86#define SIGCHG(c, i, s, d) \ 87 do { \ 88 if (c) { \ 89 i |= (i & s) ? s : s | d; \ 90 } else { \ 91 i = (i & s) ? (i & ~s) | d : i; \ 92 } \ 93 } while (0); 94 95#define BAUD2DIVISOR(b) \ 96 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10) 97 98/* 99 * Low-level UART interface. 100 */ 101static int at91_usart_probe(struct uart_bas *bas); 102static void at91_usart_init(struct uart_bas *bas, int, int, int, int); 103static void at91_usart_term(struct uart_bas *bas); 104static void at91_usart_putc(struct uart_bas *bas, int); 105static int at91_usart_rxready(struct uart_bas *bas); 106static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx); 107 108extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 109 110static int 111at91_usart_param(struct uart_bas *bas, int baudrate, int databits, 112 int stopbits, int parity) 113{ 114 uint32_t mr; 115 116 /* 117 * Assume 3-wire RS-232 configuration. 118 * XXX Not sure how uart will present the other modes to us, so 119 * XXX they are unimplemented. maybe ioctl? 120 */ 121 mr = USART_MR_MODE_NORMAL; 122 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ 123 124 /* 125 * Or in the databits requested 126 */ 127 if (databits < 9) 128 mr &= ~USART_MR_MODE9; 129 switch (databits) { 130 case 5: 131 mr |= USART_MR_CHRL_5BITS; 132 break; 133 case 6: 134 mr |= USART_MR_CHRL_6BITS; 135 break; 136 case 7: 137 mr |= USART_MR_CHRL_7BITS; 138 break; 139 case 8: 140 mr |= USART_MR_CHRL_8BITS; 141 break; 142 case 9: 143 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; 144 break; 145 default: 146 return (EINVAL); 147 } 148 149 /* 150 * Or in the parity 151 */ 152 switch (parity) { 153 case UART_PARITY_NONE: 154 mr |= USART_MR_PAR_NONE; 155 break; 156 case UART_PARITY_ODD: 157 mr |= USART_MR_PAR_ODD; 158 break; 159 case UART_PARITY_EVEN: 160 mr |= USART_MR_PAR_EVEN; 161 break; 162 case UART_PARITY_MARK: 163 mr |= USART_MR_PAR_MARK; 164 break; 165 case UART_PARITY_SPACE: 166 mr |= USART_MR_PAR_SPACE; 167 break; 168 default: 169 return (EINVAL); 170 } 171 172 /* 173 * Or in the stop bits. Note: The hardware supports 1.5 stop 174 * bits in async mode, but there's no way to specify that 175 * AFAICT. Instead, rely on the convention documented at 176 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which 177 * states that 1.5 stop bits are used for 5 bit bytes and 178 * 2 stop bits only for longer bytes. 179 */ 180 if (stopbits == 1) 181 mr |= USART_MR_NBSTOP_1; 182 else if (databits > 5) 183 mr |= USART_MR_NBSTOP_2; 184 else 185 mr |= USART_MR_NBSTOP_1_5; 186 187 /* 188 * We want normal plumbing mode too, none of this fancy 189 * loopback or echo mode. 190 */ 191 mr |= USART_MR_CHMODE_NORMAL; 192 193 mr &= ~USART_MR_MSBF; /* lsb first */ 194 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ 195 196 WR4(bas, USART_MR, mr); 197 198 /* 199 * Set the baud rate (only if we know our master clock rate) 200 */ 201 if (DEFAULT_RCLK != 0) 202 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 203 204 /* 205 * Set the receive timeout based on the baud rate. The idea is to 206 * compromise between being responsive on an interactive connection and 207 * giving a bulk data sender a bit of time to queue up a new buffer 208 * without mistaking it for a stopping point in the transmission. For 209 * 19.2kbps and below, use 20 * bit time (2 characters). For faster 210 * connections use 500 microseconds worth of bits. 211 */ 212 if (baudrate <= 19200) 213 WR4(bas, USART_RTOR, 20); 214 else 215 WR4(bas, USART_RTOR, baudrate / 2000); 216 WR4(bas, USART_CR, USART_CR_STTTO); 217 218 /* XXX Need to take possible synchronous mode into account */ 219 return (0); 220} 221 222static struct uart_ops at91_usart_ops = { 223 .probe = at91_usart_probe, 224 .init = at91_usart_init, 225 .term = at91_usart_term, 226 .putc = at91_usart_putc, 227 .rxready = at91_usart_rxready, 228 .getc = at91_usart_getc, 229}; 230 231#ifdef EARLY_PRINTF 232/* 233 * Early printf support. This assumes that we have the SoC "system" devices 234 * mapped into AT91_BASE. To use this before we adjust the boostrap tables, 235 * you'll need to define SOCDEV_VA to be 0xdc000000 and SOCDEV_PA to be 236 * 0xfc000000 in your config file where you define EARLY_PRINTF 237 */ 238volatile uint32_t *at91_dbgu = (volatile uint32_t *)(AT91_BASE + AT91_DBGU0); 239 240static void 241eputc(int c) 242{ 243 244 while (!(at91_dbgu[USART_CSR / 4] & USART_CSR_TXRDY)) 245 continue; 246 at91_dbgu[USART_THR / 4] = c; 247} 248 249early_putc_t * early_putc = eputc; 250#endif 251 252static int 253at91_usart_probe(struct uart_bas *bas) 254{ 255 256 /* We know that this is always here */ 257 return (0); 258} 259 260/* 261 * Initialize this device for use as a console. 262 */ 263static void 264at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 265 int parity) 266{ 267 268#ifdef EARLY_PRINTF 269 if (early_putc != NULL) { 270 printf("Early printf yielding control to the real console.\n"); 271 early_putc = NULL; 272 } 273#endif 274 275 /* 276 * This routine is called multiple times, sometimes right after writing 277 * some output, and the last byte is still shifting out. If that's the 278 * case delay briefly before resetting, but don't loop on TXRDY because 279 * we don't want to hang here forever if the hardware is in a bad state. 280 */ 281 if (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 282 DELAY(10000); 283 284 at91_usart_param(bas, baudrate, databits, stopbits, parity); 285 286 /* Reset the rx and tx buffers and turn on rx and tx */ 287 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 288 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 289 WR4(bas, USART_IDR, 0xffffffff); 290} 291 292/* 293 * Free resources now that we're no longer the console. This appears to 294 * be never called, and I'm unsure quite what to do if I am called. 295 */ 296static void 297at91_usart_term(struct uart_bas *bas) 298{ 299 300 /* XXX */ 301} 302 303/* 304 * Put a character of console output (so we do it here polling rather than 305 * interrupt driven). 306 */ 307static void 308at91_usart_putc(struct uart_bas *bas, int c) 309{ 310 311 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 312 continue; 313 WR4(bas, USART_THR, c); 314} 315 316/* 317 * Check for a character available. 318 */ 319static int 320at91_usart_rxready(struct uart_bas *bas) 321{ 322 323 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0); 324} 325 326/* 327 * Block waiting for a character. 328 */ 329static int 330at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx) 331{ 332 int c; 333 334 uart_lock(hwmtx); 335 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) { 336 uart_unlock(hwmtx); 337 DELAY(4); 338 uart_lock(hwmtx); 339 } 340 c = RD4(bas, USART_RHR) & 0xff; 341 uart_unlock(hwmtx); 342 return (c); 343} 344 345static int at91_usart_bus_probe(struct uart_softc *sc); 346static int at91_usart_bus_attach(struct uart_softc *sc); 347static int at91_usart_bus_flush(struct uart_softc *, int); 348static int at91_usart_bus_getsig(struct uart_softc *); 349static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t); 350static int at91_usart_bus_ipend(struct uart_softc *); 351static int at91_usart_bus_param(struct uart_softc *, int, int, int, int); 352static int at91_usart_bus_receive(struct uart_softc *); 353static int at91_usart_bus_setsig(struct uart_softc *, int); 354static int at91_usart_bus_transmit(struct uart_softc *); 355static void at91_usart_bus_grab(struct uart_softc *); 356static void at91_usart_bus_ungrab(struct uart_softc *); 357 358static kobj_method_t at91_usart_methods[] = { 359 KOBJMETHOD(uart_probe, at91_usart_bus_probe), 360 KOBJMETHOD(uart_attach, at91_usart_bus_attach), 361 KOBJMETHOD(uart_flush, at91_usart_bus_flush), 362 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig), 363 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl), 364 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend), 365 KOBJMETHOD(uart_param, at91_usart_bus_param), 366 KOBJMETHOD(uart_receive, at91_usart_bus_receive), 367 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig), 368 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit), 369 KOBJMETHOD(uart_grab, at91_usart_bus_grab), 370 KOBJMETHOD(uart_ungrab, at91_usart_bus_ungrab), 371 372 KOBJMETHOD_END 373}; 374 375int 376at91_usart_bus_probe(struct uart_softc *sc) 377{ 378 int value; 379 380 value = USART_DEFAULT_FIFO_BYTES; 381 resource_int_value(device_get_name(sc->sc_dev), 382 device_get_unit(sc->sc_dev), "fifo_bytes", &value); 383 value = roundup2(value, arm_dcache_align); 384 sc->sc_txfifosz = value; 385 sc->sc_rxfifosz = value; 386 sc->sc_hwiflow = 0; 387 return (0); 388} 389 390static void 391at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 392{ 393 394 if (error != 0) 395 return; 396 *(bus_addr_t *)arg = segs[0].ds_addr; 397} 398 399static int 400at91_usart_requires_rts0_workaround(struct uart_softc *sc) 401{ 402 int value; 403 int unit; 404 405 unit = device_get_unit(sc->sc_dev); 406 407 /* 408 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the 409 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev 410 * I of the manual). This prevents use of the hardware flow control 411 * feature in the usart itself. It also means that if we are to 412 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21 413 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We 414 * can only safely do so if we've been given permission via a hint, 415 * otherwise we might manipulate a pin that's attached to who-knows-what 416 * and Bad Things could happen. 417 */ 418 if (at91_is_rm92() && unit == 1) { 419 value = 0; 420 resource_int_value(device_get_name(sc->sc_dev), unit, 421 "use_rts0_workaround", &value); 422 if (value != 0) { 423 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21); 424 at91_pio_gpio_output(AT91RM92_PIOA_BASE, 425 AT91C_PIO_PA21, 1); 426 at91_pio_use_periph_a(AT91RM92_PIOA_BASE, 427 AT91C_PIO_PA20, 0); 428 return (1); 429 } 430 } 431 return (0); 432} 433 434static int 435at91_usart_bus_attach(struct uart_softc *sc) 436{ 437 int err; 438 int i; 439 uint32_t cr; 440 struct at91_usart_softc *atsc; 441 442 atsc = (struct at91_usart_softc *)sc; 443 444 if (at91_usart_requires_rts0_workaround(sc)) 445 atsc->flags |= USE_RTS0_WORKAROUND; 446 447 /* 448 * See if we have a TIMEOUT bit. We disable all interrupts as 449 * a side effect. Boot loaders may have enabled them. Since 450 * a TIMEOUT interrupt can't happen without other setup, the 451 * apparent race here can't actually happen. 452 */ 453 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 454 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT); 455 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) 456 atsc->flags |= HAS_TIMEOUT; 457 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 458 459 /* 460 * Allocate transmit DMA tag and map. We allow a transmit buffer 461 * to be any size, but it must map to a single contiguous physical 462 * extent. 463 */ 464 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 465 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 466 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 467 NULL, &atsc->tx_tag); 468 if (err != 0) 469 goto errout; 470 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map); 471 if (err != 0) 472 goto errout; 473 474 if (atsc->flags & HAS_TIMEOUT) { 475 /* 476 * Allocate receive DMA tags, maps, and buffers. 477 * The receive buffers should be aligned to arm_dcache_align, 478 * otherwise partial cache line flushes on every receive 479 * interrupt are pretty much guaranteed. 480 */ 481 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 482 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT, 483 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1, 484 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL, 485 &atsc->rx_tag); 486 if (err != 0) 487 goto errout; 488 for (i = 0; i < 2; i++) { 489 err = bus_dmamem_alloc(atsc->rx_tag, 490 (void **)&atsc->ping_pong[i].buffer, 491 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map); 492 if (err != 0) 493 goto errout; 494 err = bus_dmamap_load(atsc->rx_tag, 495 atsc->ping_pong[i].map, 496 atsc->ping_pong[i].buffer, sc->sc_rxfifosz, 497 at91_getaddr, &atsc->ping_pong[i].pa, 0); 498 if (err != 0) 499 goto errout; 500 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map, 501 BUS_DMASYNC_PREREAD); 502 } 503 atsc->ping = &atsc->ping_pong[0]; 504 atsc->pong = &atsc->ping_pong[1]; 505 } 506 507 /* Turn on rx and tx */ 508 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; 509 WR4(&sc->sc_bas, USART_CR, cr); 510 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 511 512 /* 513 * Setup the PDC to receive data. We use the ping-pong buffers 514 * so that we can more easily bounce between the two and so that 515 * we get an interrupt 1/2 way through the software 'fifo' we have 516 * to avoid overruns. 517 */ 518 if (atsc->flags & HAS_TIMEOUT) { 519 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 520 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 521 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 522 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 523 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 524 525 /* 526 * Set the receive timeout to be 1.5 character times 527 * assuming 8N1. 528 */ 529 WR4(&sc->sc_bas, USART_RTOR, 15); 530 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 531 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | 532 USART_CSR_RXBUFF | USART_CSR_ENDRX); 533 } else { 534 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 535 } 536 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS); 537 538 /* Prime sc->hwsig with the initial hw line states. */ 539 at91_usart_bus_getsig(sc); 540 541errout: 542 return (err); 543} 544 545static int 546at91_usart_bus_transmit(struct uart_softc *sc) 547{ 548 bus_addr_t addr; 549 struct at91_usart_softc *atsc; 550 int err; 551 552 err = 0; 553 atsc = (struct at91_usart_softc *)sc; 554 uart_lock(sc->sc_hwmtx); 555 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf, 556 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) { 557 err = EAGAIN; 558 goto errout; 559 } 560 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE); 561 sc->sc_txbusy = 1; 562 /* 563 * Setup the PDC to transfer the data and interrupt us when it 564 * is done. We've already requested the interrupt. 565 */ 566 WR4(&sc->sc_bas, PDC_TPR, addr); 567 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz); 568 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN); 569 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX); 570errout: 571 uart_unlock(sc->sc_hwmtx); 572 return (err); 573} 574 575static int 576at91_usart_bus_setsig(struct uart_softc *sc, int sig) 577{ 578 uint32_t new, old, cr; 579 struct at91_usart_softc *atsc; 580 581 atsc = (struct at91_usart_softc *)sc; 582 583 do { 584 old = sc->sc_hwsig; 585 new = old; 586 if (sig & SER_DDTR) 587 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 588 if (sig & SER_DRTS) 589 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 590 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 591 592 cr = 0; 593 if (new & SER_DTR) 594 cr |= USART_CR_DTREN; 595 else 596 cr |= USART_CR_DTRDIS; 597 if (new & SER_RTS) 598 cr |= USART_CR_RTSEN; 599 else 600 cr |= USART_CR_RTSDIS; 601 602 uart_lock(sc->sc_hwmtx); 603 WR4(&sc->sc_bas, USART_CR, cr); 604 if (atsc->flags & USE_RTS0_WORKAROUND) { 605 /* Signal is active-low. */ 606 if (new & SER_RTS) 607 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21); 608 else 609 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21); 610 } 611 uart_unlock(sc->sc_hwmtx); 612 613 return (0); 614} 615 616static int 617at91_usart_bus_receive(struct uart_softc *sc) 618{ 619 620 return (0); 621} 622 623static int 624at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits, 625 int stopbits, int parity) 626{ 627 628 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits, 629 parity)); 630} 631 632static __inline void 633at91_rx_put(struct uart_softc *sc, int key) 634{ 635 636#if defined(KDB) 637 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) 638 kdb_alt_break(key, &sc->sc_altbrk); 639#endif 640 uart_rx_put(sc, key); 641} 642 643static int 644at91_usart_bus_ipend(struct uart_softc *sc) 645{ 646 struct at91_usart_softc *atsc; 647 struct at91_usart_rx *p; 648 int i, ipend, len; 649 uint32_t csr; 650 651 ipend = 0; 652 atsc = (struct at91_usart_softc *)sc; 653 uart_lock(sc->sc_hwmtx); 654 csr = RD4(&sc->sc_bas, USART_CSR); 655 656 if (csr & USART_CSR_OVRE) { 657 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA); 658 ipend |= SER_INT_OVERRUN; 659 } 660 661 if (csr & USART_DCE_CHANGE_BITS) 662 ipend |= SER_INT_SIGCHG; 663 664 if (csr & USART_CSR_ENDTX) { 665 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, 666 BUS_DMASYNC_POSTWRITE); 667 bus_dmamap_unload(atsc->tx_tag, atsc->tx_map); 668 } 669 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) { 670 if (sc->sc_txbusy) 671 ipend |= SER_INT_TXIDLE; 672 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY | 673 USART_CSR_ENDTX)); 674 } 675 676 /* 677 * Due to the contraints of the DMA engine present in the 678 * atmel chip, I can't just say I have a rx interrupt pending 679 * and do all the work elsewhere. I need to look at the CSR 680 * bits right now and do things based on them to avoid races. 681 */ 682 if (atsc->flags & HAS_TIMEOUT) { 683 if (csr & USART_CSR_RXBUFF) { 684 /* 685 * We have a buffer overflow. Consume data from ping 686 * and give it back to the hardware before worrying 687 * about pong, to minimze data loss. Insert an overrun 688 * marker after the contents of the pong buffer. 689 */ 690 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 691 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 692 BUS_DMASYNC_POSTREAD); 693 for (i = 0; i < sc->sc_rxfifosz; i++) 694 at91_rx_put(sc, atsc->ping->buffer[i]); 695 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 696 BUS_DMASYNC_PREREAD); 697 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 698 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 699 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 700 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map, 701 BUS_DMASYNC_POSTREAD); 702 for (i = 0; i < sc->sc_rxfifosz; i++) 703 at91_rx_put(sc, atsc->pong->buffer[i]); 704 uart_rx_put(sc, UART_STAT_OVERRUN); 705 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map, 706 BUS_DMASYNC_PREREAD); 707 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 708 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 709 ipend |= SER_INT_RXREADY; 710 } else if (csr & USART_CSR_ENDRX) { 711 /* 712 * Consume data from ping of ping pong buffer, but leave 713 * current pong in place, as it has become the new ping. 714 * We need to copy data and setup the old ping as the 715 * new pong when we're done. 716 */ 717 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 718 BUS_DMASYNC_POSTREAD); 719 for (i = 0; i < sc->sc_rxfifosz; i++) 720 at91_rx_put(sc, atsc->ping->buffer[i]); 721 p = atsc->ping; 722 atsc->ping = atsc->pong; 723 atsc->pong = p; 724 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map, 725 BUS_DMASYNC_PREREAD); 726 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 727 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 728 ipend |= SER_INT_RXREADY; 729 } else if (csr & USART_CSR_TIMEOUT) { 730 /* 731 * On a timeout, one of the following applies: 732 * 1. Two empty buffers. The last received byte exactly 733 * filled a buffer, causing an ENDTX that got 734 * processed earlier; no new bytes have arrived. 735 * 2. Ping buffer contains some data and pong is empty. 736 * This should be the most common timeout condition. 737 * 3. Ping buffer is full and pong is now being filled. 738 * This is exceedingly rare; it can happen only if 739 * the ping buffer is almost full when a timeout is 740 * signaled, and then dataflow resumes and the ping 741 * buffer filled up between the time we read the 742 * status register above and the point where the 743 * RXTDIS takes effect here. Yes, it can happen. 744 * Because dataflow can resume at any time following a 745 * timeout (it may have already resumed before we get 746 * here), it's important to minimize the time the PDC is 747 * disabled -- just long enough to take the ping buffer 748 * out of service (so we can consume it) and install the 749 * pong buffer as the active one. Note that in case 3 750 * the hardware has already done the ping-pong swap. 751 */ 752 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 753 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) { 754 len = sc->sc_rxfifosz; 755 } else { 756 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); 757 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa); 758 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 759 WR4(&sc->sc_bas, PDC_RNCR, 0); 760 } 761 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 762 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 763 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 764 BUS_DMASYNC_POSTREAD); 765 for (i = 0; i < len; i++) 766 at91_rx_put(sc, atsc->ping->buffer[i]); 767 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 768 BUS_DMASYNC_PREREAD); 769 p = atsc->ping; 770 atsc->ping = atsc->pong; 771 atsc->pong = p; 772 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 773 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 774 ipend |= SER_INT_RXREADY; 775 } 776 } else if (csr & USART_CSR_RXRDY) { 777 /* 778 * We have another charater in a device that doesn't support 779 * timeouts, so we do it one character at a time. 780 */ 781 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); 782 ipend |= SER_INT_RXREADY; 783 } 784 785 if (csr & USART_CSR_RXBRK) { 786 ipend |= SER_INT_BREAK; 787 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA); 788 } 789 uart_unlock(sc->sc_hwmtx); 790 return (ipend); 791} 792 793static int 794at91_usart_bus_flush(struct uart_softc *sc, int what) 795{ 796 797 return (0); 798} 799 800static int 801at91_usart_bus_getsig(struct uart_softc *sc) 802{ 803 uint32_t csr, new, old, sig; 804 805 /* 806 * Note that the atmel channel status register DCE status bits reflect 807 * the electrical state of the lines, not the logical state. Since they 808 * are logically active-low signals, we invert the tests here. 809 */ 810 do { 811 old = sc->sc_hwsig; 812 sig = old; 813 csr = RD4(&sc->sc_bas, USART_CSR); 814 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR); 815 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS); 816 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD); 817 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI); 818 new = sig & ~SER_MASK_DELTA; 819 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 820 821 return (sig); 822} 823 824static int 825at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 826{ 827 828 switch (request) { 829 case UART_IOCTL_BREAK: 830 case UART_IOCTL_IFLOW: 831 case UART_IOCTL_OFLOW: 832 break; 833 case UART_IOCTL_BAUD: 834 /* only if we know our master clock rate */ 835 if (DEFAULT_RCLK != 0) 836 WR4(&sc->sc_bas, USART_BRGR, 837 BAUD2DIVISOR(*(int *)data)); 838 return (0); 839 } 840 return (EINVAL); 841} 842 843 844static void 845at91_usart_bus_grab(struct uart_softc *sc) 846{ 847 848 uart_lock(sc->sc_hwmtx); 849 WR4(&sc->sc_bas, USART_IDR, USART_CSR_RXRDY); 850 uart_unlock(sc->sc_hwmtx); 851} 852 853static void 854at91_usart_bus_ungrab(struct uart_softc *sc) 855{ 856 857 uart_lock(sc->sc_hwmtx); 858 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 859 uart_unlock(sc->sc_hwmtx); 860} 861 862struct uart_class at91_usart_class = { 863 "at91_usart", 864 at91_usart_methods, 865 sizeof(struct at91_usart_softc), 866 .uc_ops = &at91_usart_ops, 867 .uc_range = 8 868}; 869