uart_dev_at91usart.c revision 262698
1/*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 Olivier Houchard 4 * Copyright (c) 2012 Ian Lepore 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/arm/at91/uart_dev_at91usart.c 262698 2014-03-02 23:09:36Z imp $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/cons.h> 38#include <sys/tty.h> 39#include <machine/bus.h> 40 41#include <dev/uart/uart.h> 42#include <dev/uart/uart_cpu.h> 43#include <dev/uart/uart_bus.h> 44#include <arm/at91/at91_usartreg.h> 45#include <arm/at91/at91_pdcreg.h> 46#include <arm/at91/at91_piovar.h> 47#include <arm/at91/at91_pioreg.h> 48#include <arm/at91/at91rm92reg.h> 49#include <arm/at91/at91var.h> 50 51#include "uart_if.h" 52 53#define DEFAULT_RCLK at91_master_clock 54#define USART_DEFAULT_FIFO_BYTES 128 55 56#define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \ 57 USART_CSR_DSRIC | USART_CSR_RIIC) 58 59/* 60 * High-level UART interface. 61 */ 62struct at91_usart_rx { 63 bus_addr_t pa; 64 uint8_t *buffer; 65 bus_dmamap_t map; 66}; 67 68struct at91_usart_softc { 69 struct uart_softc base; 70 bus_dma_tag_t tx_tag; 71 bus_dmamap_t tx_map; 72 uint32_t flags; 73#define HAS_TIMEOUT 0x1 74#define USE_RTS0_WORKAROUND 0x2 75 bus_dma_tag_t rx_tag; 76 struct at91_usart_rx ping_pong[2]; 77 struct at91_usart_rx *ping; 78 struct at91_usart_rx *pong; 79}; 80 81#define RD4(bas, reg) \ 82 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 83#define WR4(bas, reg, value) \ 84 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 85 86#define SIGCHG(c, i, s, d) \ 87 do { \ 88 if (c) { \ 89 i |= (i & s) ? s : s | d; \ 90 } else { \ 91 i = (i & s) ? (i & ~s) | d : i; \ 92 } \ 93 } while (0); 94 95#define BAUD2DIVISOR(b) \ 96 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10) 97 98/* 99 * Low-level UART interface. 100 */ 101static int at91_usart_probe(struct uart_bas *bas); 102static void at91_usart_init(struct uart_bas *bas, int, int, int, int); 103static void at91_usart_term(struct uart_bas *bas); 104static void at91_usart_putc(struct uart_bas *bas, int); 105static int at91_usart_rxready(struct uart_bas *bas); 106static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx); 107 108extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 109 110static int 111at91_usart_param(struct uart_bas *bas, int baudrate, int databits, 112 int stopbits, int parity) 113{ 114 uint32_t mr; 115 116 /* 117 * Assume 3-wire RS-232 configuration. 118 * XXX Not sure how uart will present the other modes to us, so 119 * XXX they are unimplemented. maybe ioctl? 120 */ 121 mr = USART_MR_MODE_NORMAL; 122 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ 123 124 /* 125 * Or in the databits requested 126 */ 127 if (databits < 9) 128 mr &= ~USART_MR_MODE9; 129 switch (databits) { 130 case 5: 131 mr |= USART_MR_CHRL_5BITS; 132 break; 133 case 6: 134 mr |= USART_MR_CHRL_6BITS; 135 break; 136 case 7: 137 mr |= USART_MR_CHRL_7BITS; 138 break; 139 case 8: 140 mr |= USART_MR_CHRL_8BITS; 141 break; 142 case 9: 143 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; 144 break; 145 default: 146 return (EINVAL); 147 } 148 149 /* 150 * Or in the parity 151 */ 152 switch (parity) { 153 case UART_PARITY_NONE: 154 mr |= USART_MR_PAR_NONE; 155 break; 156 case UART_PARITY_ODD: 157 mr |= USART_MR_PAR_ODD; 158 break; 159 case UART_PARITY_EVEN: 160 mr |= USART_MR_PAR_EVEN; 161 break; 162 case UART_PARITY_MARK: 163 mr |= USART_MR_PAR_MARK; 164 break; 165 case UART_PARITY_SPACE: 166 mr |= USART_MR_PAR_SPACE; 167 break; 168 default: 169 return (EINVAL); 170 } 171 172 /* 173 * Or in the stop bits. Note: The hardware supports 1.5 stop 174 * bits in async mode, but there's no way to specify that 175 * AFAICT. Instead, rely on the convention documented at 176 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which 177 * states that 1.5 stop bits are used for 5 bit bytes and 178 * 2 stop bits only for longer bytes. 179 */ 180 if (stopbits == 1) 181 mr |= USART_MR_NBSTOP_1; 182 else if (databits > 5) 183 mr |= USART_MR_NBSTOP_2; 184 else 185 mr |= USART_MR_NBSTOP_1_5; 186 187 /* 188 * We want normal plumbing mode too, none of this fancy 189 * loopback or echo mode. 190 */ 191 mr |= USART_MR_CHMODE_NORMAL; 192 193 mr &= ~USART_MR_MSBF; /* lsb first */ 194 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ 195 196 WR4(bas, USART_MR, mr); 197 198 /* 199 * Set the baud rate (only if we know our master clock rate) 200 */ 201 if (DEFAULT_RCLK != 0) 202 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 203 204 /* 205 * Set the receive timeout based on the baud rate. The idea is to 206 * compromise between being responsive on an interactive connection and 207 * giving a bulk data sender a bit of time to queue up a new buffer 208 * without mistaking it for a stopping point in the transmission. For 209 * 19.2kbps and below, use 20 * bit time (2 characters). For faster 210 * connections use 500 microseconds worth of bits. 211 */ 212 if (baudrate <= 19200) 213 WR4(bas, USART_RTOR, 20); 214 else 215 WR4(bas, USART_RTOR, baudrate / 2000); 216 WR4(bas, USART_CR, USART_CR_STTTO); 217 218 /* XXX Need to take possible synchronous mode into account */ 219 return (0); 220} 221 222static struct uart_ops at91_usart_ops = { 223 .probe = at91_usart_probe, 224 .init = at91_usart_init, 225 .term = at91_usart_term, 226 .putc = at91_usart_putc, 227 .rxready = at91_usart_rxready, 228 .getc = at91_usart_getc, 229}; 230 231static int 232at91_usart_probe(struct uart_bas *bas) 233{ 234 235 /* We know that this is always here */ 236 return (0); 237} 238 239/* 240 * Initialize this device for use as a console. 241 */ 242static void 243at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 244 int parity) 245{ 246 247 at91_usart_param(bas, baudrate, databits, stopbits, parity); 248 249 /* Reset the rx and tx buffers and turn on rx and tx */ 250 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 251 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 252 WR4(bas, USART_IDR, 0xffffffff); 253} 254 255/* 256 * Free resources now that we're no longer the console. This appears to 257 * be never called, and I'm unsure quite what to do if I am called. 258 */ 259static void 260at91_usart_term(struct uart_bas *bas) 261{ 262 263 /* XXX */ 264} 265 266/* 267 * Put a character of console output (so we do it here polling rather than 268 * interrupt driven). 269 */ 270static void 271at91_usart_putc(struct uart_bas *bas, int c) 272{ 273 274 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 275 continue; 276 WR4(bas, USART_THR, c); 277} 278 279/* 280 * Check for a character available. 281 */ 282static int 283at91_usart_rxready(struct uart_bas *bas) 284{ 285 286 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0); 287} 288 289/* 290 * Block waiting for a character. 291 */ 292static int 293at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx) 294{ 295 int c; 296 297 uart_lock(hwmtx); 298 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) { 299 uart_unlock(hwmtx); 300 DELAY(4); 301 uart_lock(hwmtx); 302 } 303 c = RD4(bas, USART_RHR) & 0xff; 304 uart_unlock(hwmtx); 305 return (c); 306} 307 308static int at91_usart_bus_probe(struct uart_softc *sc); 309static int at91_usart_bus_attach(struct uart_softc *sc); 310static int at91_usart_bus_flush(struct uart_softc *, int); 311static int at91_usart_bus_getsig(struct uart_softc *); 312static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t); 313static int at91_usart_bus_ipend(struct uart_softc *); 314static int at91_usart_bus_param(struct uart_softc *, int, int, int, int); 315static int at91_usart_bus_receive(struct uart_softc *); 316static int at91_usart_bus_setsig(struct uart_softc *, int); 317static int at91_usart_bus_transmit(struct uart_softc *); 318static void at91_usart_bus_grab(struct uart_softc *); 319static void at91_usart_bus_ungrab(struct uart_softc *); 320 321static kobj_method_t at91_usart_methods[] = { 322 KOBJMETHOD(uart_probe, at91_usart_bus_probe), 323 KOBJMETHOD(uart_attach, at91_usart_bus_attach), 324 KOBJMETHOD(uart_flush, at91_usart_bus_flush), 325 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig), 326 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl), 327 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend), 328 KOBJMETHOD(uart_param, at91_usart_bus_param), 329 KOBJMETHOD(uart_receive, at91_usart_bus_receive), 330 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig), 331 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit), 332 KOBJMETHOD(uart_grab, at91_usart_bus_grab), 333 KOBJMETHOD(uart_ungrab, at91_usart_bus_ungrab), 334 335 KOBJMETHOD_END 336}; 337 338int 339at91_usart_bus_probe(struct uart_softc *sc) 340{ 341 int value; 342 343 value = USART_DEFAULT_FIFO_BYTES; 344 resource_int_value(device_get_name(sc->sc_dev), 345 device_get_unit(sc->sc_dev), "fifo_bytes", &value); 346 value = roundup2(value, arm_dcache_align); 347 sc->sc_txfifosz = value; 348 sc->sc_rxfifosz = value; 349 sc->sc_hwiflow = 0; 350 return (0); 351} 352 353static void 354at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 355{ 356 357 if (error != 0) 358 return; 359 *(bus_addr_t *)arg = segs[0].ds_addr; 360} 361 362static int 363at91_usart_requires_rts0_workaround(struct uart_softc *sc) 364{ 365 int value; 366 int unit; 367 368 unit = device_get_unit(sc->sc_dev); 369 370 /* 371 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the 372 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev 373 * I of the manual). This prevents use of the hardware flow control 374 * feature in the usart itself. It also means that if we are to 375 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21 376 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We 377 * can only safely do so if we've been given permission via a hint, 378 * otherwise we might manipulate a pin that's attached to who-knows-what 379 * and Bad Things could happen. 380 */ 381 if (at91_is_rm92() && unit == 1) { 382 value = 0; 383 resource_int_value(device_get_name(sc->sc_dev), unit, 384 "use_rts0_workaround", &value); 385 if (value != 0) { 386 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21); 387 at91_pio_gpio_output(AT91RM92_PIOA_BASE, 388 AT91C_PIO_PA21, 1); 389 at91_pio_use_periph_a(AT91RM92_PIOA_BASE, 390 AT91C_PIO_PA20, 0); 391 return (1); 392 } 393 } 394 return (0); 395} 396 397static int 398at91_usart_bus_attach(struct uart_softc *sc) 399{ 400 int err; 401 int i; 402 uint32_t cr; 403 struct at91_usart_softc *atsc; 404 405 atsc = (struct at91_usart_softc *)sc; 406 407 if (at91_usart_requires_rts0_workaround(sc)) 408 atsc->flags |= USE_RTS0_WORKAROUND; 409 410 /* 411 * See if we have a TIMEOUT bit. We disable all interrupts as 412 * a side effect. Boot loaders may have enabled them. Since 413 * a TIMEOUT interrupt can't happen without other setup, the 414 * apparent race here can't actually happen. 415 */ 416 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 417 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT); 418 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) 419 atsc->flags |= HAS_TIMEOUT; 420 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 421 422 /* 423 * Allocate transmit DMA tag and map. We allow a transmit buffer 424 * to be any size, but it must map to a single contiguous physical 425 * extent. 426 */ 427 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 428 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 429 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 430 NULL, &atsc->tx_tag); 431 if (err != 0) 432 goto errout; 433 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map); 434 if (err != 0) 435 goto errout; 436 437 if (atsc->flags & HAS_TIMEOUT) { 438 /* 439 * Allocate receive DMA tags, maps, and buffers. 440 * The receive buffers should be aligned to arm_dcache_align, 441 * otherwise partial cache line flushes on every receive 442 * interrupt are pretty much guaranteed. 443 */ 444 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 445 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT, 446 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1, 447 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL, 448 &atsc->rx_tag); 449 if (err != 0) 450 goto errout; 451 for (i = 0; i < 2; i++) { 452 err = bus_dmamem_alloc(atsc->rx_tag, 453 (void **)&atsc->ping_pong[i].buffer, 454 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map); 455 if (err != 0) 456 goto errout; 457 err = bus_dmamap_load(atsc->rx_tag, 458 atsc->ping_pong[i].map, 459 atsc->ping_pong[i].buffer, sc->sc_rxfifosz, 460 at91_getaddr, &atsc->ping_pong[i].pa, 0); 461 if (err != 0) 462 goto errout; 463 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map, 464 BUS_DMASYNC_PREREAD); 465 } 466 atsc->ping = &atsc->ping_pong[0]; 467 atsc->pong = &atsc->ping_pong[1]; 468 } 469 470 /* Turn on rx and tx */ 471 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; 472 WR4(&sc->sc_bas, USART_CR, cr); 473 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 474 475 /* 476 * Setup the PDC to receive data. We use the ping-pong buffers 477 * so that we can more easily bounce between the two and so that 478 * we get an interrupt 1/2 way through the software 'fifo' we have 479 * to avoid overruns. 480 */ 481 if (atsc->flags & HAS_TIMEOUT) { 482 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 483 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 484 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 485 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 486 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 487 488 /* 489 * Set the receive timeout to be 1.5 character times 490 * assuming 8N1. 491 */ 492 WR4(&sc->sc_bas, USART_RTOR, 15); 493 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 494 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | 495 USART_CSR_RXBUFF | USART_CSR_ENDRX); 496 } else { 497 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 498 } 499 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS); 500 501 /* Prime sc->hwsig with the initial hw line states. */ 502 at91_usart_bus_getsig(sc); 503 504errout: 505 return (err); 506} 507 508static int 509at91_usart_bus_transmit(struct uart_softc *sc) 510{ 511 bus_addr_t addr; 512 struct at91_usart_softc *atsc; 513 int err; 514 515 err = 0; 516 atsc = (struct at91_usart_softc *)sc; 517 uart_lock(sc->sc_hwmtx); 518 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf, 519 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) { 520 err = EAGAIN; 521 goto errout; 522 } 523 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE); 524 sc->sc_txbusy = 1; 525 /* 526 * Setup the PDC to transfer the data and interrupt us when it 527 * is done. We've already requested the interrupt. 528 */ 529 WR4(&sc->sc_bas, PDC_TPR, addr); 530 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz); 531 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN); 532 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX); 533errout: 534 uart_unlock(sc->sc_hwmtx); 535 return (err); 536} 537 538static int 539at91_usart_bus_setsig(struct uart_softc *sc, int sig) 540{ 541 uint32_t new, old, cr; 542 struct at91_usart_softc *atsc; 543 544 atsc = (struct at91_usart_softc *)sc; 545 546 do { 547 old = sc->sc_hwsig; 548 new = old; 549 if (sig & SER_DDTR) 550 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 551 if (sig & SER_DRTS) 552 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 553 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 554 555 cr = 0; 556 if (new & SER_DTR) 557 cr |= USART_CR_DTREN; 558 else 559 cr |= USART_CR_DTRDIS; 560 if (new & SER_RTS) 561 cr |= USART_CR_RTSEN; 562 else 563 cr |= USART_CR_RTSDIS; 564 565 uart_lock(sc->sc_hwmtx); 566 WR4(&sc->sc_bas, USART_CR, cr); 567 if (atsc->flags & USE_RTS0_WORKAROUND) { 568 /* Signal is active-low. */ 569 if (new & SER_RTS) 570 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21); 571 else 572 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21); 573 } 574 uart_unlock(sc->sc_hwmtx); 575 576 return (0); 577} 578 579static int 580at91_usart_bus_receive(struct uart_softc *sc) 581{ 582 583 return (0); 584} 585 586static int 587at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits, 588 int stopbits, int parity) 589{ 590 591 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits, 592 parity)); 593} 594 595static __inline void 596at91_rx_put(struct uart_softc *sc, int key) 597{ 598 599#if defined(KDB) 600 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) 601 kdb_alt_break(key, &sc->sc_altbrk); 602#endif 603 uart_rx_put(sc, key); 604} 605 606static int 607at91_usart_bus_ipend(struct uart_softc *sc) 608{ 609 struct at91_usart_softc *atsc; 610 struct at91_usart_rx *p; 611 int i, ipend, len; 612 uint32_t csr; 613 614 ipend = 0; 615 atsc = (struct at91_usart_softc *)sc; 616 uart_lock(sc->sc_hwmtx); 617 csr = RD4(&sc->sc_bas, USART_CSR); 618 619 if (csr & USART_CSR_OVRE) { 620 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA); 621 ipend |= SER_INT_OVERRUN; 622 } 623 624 if (csr & USART_DCE_CHANGE_BITS) 625 ipend |= SER_INT_SIGCHG; 626 627 if (csr & USART_CSR_ENDTX) { 628 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, 629 BUS_DMASYNC_POSTWRITE); 630 bus_dmamap_unload(atsc->tx_tag, atsc->tx_map); 631 } 632 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) { 633 if (sc->sc_txbusy) 634 ipend |= SER_INT_TXIDLE; 635 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY | 636 USART_CSR_ENDTX)); 637 } 638 639 /* 640 * Due to the contraints of the DMA engine present in the 641 * atmel chip, I can't just say I have a rx interrupt pending 642 * and do all the work elsewhere. I need to look at the CSR 643 * bits right now and do things based on them to avoid races. 644 */ 645 if (atsc->flags & HAS_TIMEOUT) { 646 if (csr & USART_CSR_RXBUFF) { 647 /* 648 * We have a buffer overflow. Consume data from ping 649 * and give it back to the hardware before worrying 650 * about pong, to minimze data loss. Insert an overrun 651 * marker after the contents of the pong buffer. 652 */ 653 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 654 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 655 BUS_DMASYNC_POSTREAD); 656 for (i = 0; i < sc->sc_rxfifosz; i++) 657 at91_rx_put(sc, atsc->ping->buffer[i]); 658 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 659 BUS_DMASYNC_PREREAD); 660 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 661 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 662 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 663 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map, 664 BUS_DMASYNC_POSTREAD); 665 for (i = 0; i < sc->sc_rxfifosz; i++) 666 at91_rx_put(sc, atsc->pong->buffer[i]); 667 uart_rx_put(sc, UART_STAT_OVERRUN); 668 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map, 669 BUS_DMASYNC_PREREAD); 670 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 671 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 672 ipend |= SER_INT_RXREADY; 673 } else if (csr & USART_CSR_ENDRX) { 674 /* 675 * Consume data from ping of ping pong buffer, but leave 676 * current pong in place, as it has become the new ping. 677 * We need to copy data and setup the old ping as the 678 * new pong when we're done. 679 */ 680 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 681 BUS_DMASYNC_POSTREAD); 682 for (i = 0; i < sc->sc_rxfifosz; i++) 683 at91_rx_put(sc, atsc->ping->buffer[i]); 684 p = atsc->ping; 685 atsc->ping = atsc->pong; 686 atsc->pong = p; 687 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map, 688 BUS_DMASYNC_PREREAD); 689 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 690 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 691 ipend |= SER_INT_RXREADY; 692 } else if (csr & USART_CSR_TIMEOUT) { 693 /* 694 * On a timeout, one of the following applies: 695 * 1. Two empty buffers. The last received byte exactly 696 * filled a buffer, causing an ENDTX that got 697 * processed earlier; no new bytes have arrived. 698 * 2. Ping buffer contains some data and pong is empty. 699 * This should be the most common timeout condition. 700 * 3. Ping buffer is full and pong is now being filled. 701 * This is exceedingly rare; it can happen only if 702 * the ping buffer is almost full when a timeout is 703 * signaled, and then dataflow resumes and the ping 704 * buffer filled up between the time we read the 705 * status register above and the point where the 706 * RXTDIS takes effect here. Yes, it can happen. 707 * Because dataflow can resume at any time following a 708 * timeout (it may have already resumed before we get 709 * here), it's important to minimize the time the PDC is 710 * disabled -- just long enough to take the ping buffer 711 * out of service (so we can consume it) and install the 712 * pong buffer as the active one. Note that in case 3 713 * the hardware has already done the ping-pong swap. 714 */ 715 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 716 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) { 717 len = sc->sc_rxfifosz; 718 } else { 719 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); 720 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa); 721 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 722 WR4(&sc->sc_bas, PDC_RNCR, 0); 723 } 724 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 725 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 726 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 727 BUS_DMASYNC_POSTREAD); 728 for (i = 0; i < len; i++) 729 at91_rx_put(sc, atsc->ping->buffer[i]); 730 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map, 731 BUS_DMASYNC_PREREAD); 732 p = atsc->ping; 733 atsc->ping = atsc->pong; 734 atsc->pong = p; 735 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 736 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 737 ipend |= SER_INT_RXREADY; 738 } 739 } else if (csr & USART_CSR_RXRDY) { 740 /* 741 * We have another charater in a device that doesn't support 742 * timeouts, so we do it one character at a time. 743 */ 744 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); 745 ipend |= SER_INT_RXREADY; 746 } 747 748 if (csr & USART_CSR_RXBRK) { 749 ipend |= SER_INT_BREAK; 750 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA); 751 } 752 uart_unlock(sc->sc_hwmtx); 753 return (ipend); 754} 755 756static int 757at91_usart_bus_flush(struct uart_softc *sc, int what) 758{ 759 760 return (0); 761} 762 763static int 764at91_usart_bus_getsig(struct uart_softc *sc) 765{ 766 uint32_t csr, new, old, sig; 767 768 /* 769 * Note that the atmel channel status register DCE status bits reflect 770 * the electrical state of the lines, not the logical state. Since they 771 * are logically active-low signals, we invert the tests here. 772 */ 773 do { 774 old = sc->sc_hwsig; 775 sig = old; 776 csr = RD4(&sc->sc_bas, USART_CSR); 777 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR); 778 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS); 779 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD); 780 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI); 781 new = sig & ~SER_MASK_DELTA; 782 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 783 784 return (sig); 785} 786 787static int 788at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 789{ 790 791 switch (request) { 792 case UART_IOCTL_BREAK: 793 case UART_IOCTL_IFLOW: 794 case UART_IOCTL_OFLOW: 795 break; 796 case UART_IOCTL_BAUD: 797 /* only if we know our master clock rate */ 798 if (DEFAULT_RCLK != 0) 799 WR4(&sc->sc_bas, USART_BRGR, 800 BAUD2DIVISOR(*(int *)data)); 801 return (0); 802 } 803 return (EINVAL); 804} 805 806 807static void 808at91_usart_bus_grab(struct uart_softc *sc) 809{ 810 811 uart_lock(sc->sc_hwmtx); 812 WR4(&sc->sc_bas, USART_IDR, USART_CSR_RXRDY); 813 uart_unlock(sc->sc_hwmtx); 814} 815 816static void 817at91_usart_bus_ungrab(struct uart_softc *sc) 818{ 819 820 uart_lock(sc->sc_hwmtx); 821 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 822 uart_unlock(sc->sc_hwmtx); 823} 824 825struct uart_class at91_usart_class = { 826 "at91_usart", 827 at91_usart_methods, 828 sizeof(struct at91_usart_softc), 829 .uc_ops = &at91_usart_ops, 830 .uc_range = 8 831}; 832