uart_dev_at91usart.c revision 187602
1/*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 Olivier Houchard 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/arm/at91/uart_dev_at91usart.c 187602 2009-01-22 21:56:41Z imp $"); 31 32#include "opt_comconsole.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/conf.h> 38#include <sys/cons.h> 39#include <sys/tty.h> 40#include <machine/bus.h> 41 42#include <dev/uart/uart.h> 43#include <dev/uart/uart_cpu.h> 44#include <dev/uart/uart_bus.h> 45#include <arm/at91/at91rm92reg.h> 46#include <arm/at91/at91_usartreg.h> 47#include <arm/at91/at91_pdcreg.h> 48#include <arm/at91/at91var.h> 49 50#include "uart_if.h" 51 52#define DEFAULT_RCLK at91_master_clock 53#define USART_BUFFER_SIZE 128 54 55/* 56 * High-level UART interface. 57 */ 58struct at91_usart_rx { 59 bus_addr_t pa; 60 uint8_t buffer[USART_BUFFER_SIZE]; 61 bus_dmamap_t map; 62}; 63 64struct at91_usart_softc { 65 struct uart_softc base; 66 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */ 67 bus_dmamap_t tx_map; 68 uint32_t flags; 69#define HAS_TIMEOUT 1 70 struct at91_usart_rx ping_pong[2]; 71 struct at91_usart_rx *ping; 72 struct at91_usart_rx *pong; 73}; 74 75#define RD4(bas, reg) \ 76 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 77#define WR4(bas, reg, value) \ 78 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 79 80#define SIGCHG(c, i, s, d) \ 81 do { \ 82 if (c) { \ 83 i |= (i & s) ? s : s | d; \ 84 } else { \ 85 i = (i & s) ? (i & ~s) | d : i; \ 86 } \ 87 } while (0); 88 89#define BAUD2DIVISOR(b) \ 90 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10) 91 92/* 93 * Low-level UART interface. 94 */ 95static int at91_usart_probe(struct uart_bas *bas); 96static void at91_usart_init(struct uart_bas *bas, int, int, int, int); 97static void at91_usart_term(struct uart_bas *bas); 98static void at91_usart_putc(struct uart_bas *bas, int); 99static int at91_usart_rxready(struct uart_bas *bas); 100static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx); 101 102extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 103 104static int 105at91_usart_param(struct uart_bas *bas, int baudrate, int databits, 106 int stopbits, int parity) 107{ 108 uint32_t mr; 109 110 /* 111 * Assume 3-write RS-232 configuration. 112 * XXX Not sure how uart will present the other modes to us, so 113 * XXX they are unimplemented. maybe ioctl? 114 */ 115 mr = USART_MR_MODE_NORMAL; 116 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ 117 118 /* 119 * Or in the databits requested 120 */ 121 if (databits < 9) 122 mr &= ~USART_MR_MODE9; 123 switch (databits) { 124 case 5: 125 mr |= USART_MR_CHRL_5BITS; 126 break; 127 case 6: 128 mr |= USART_MR_CHRL_6BITS; 129 break; 130 case 7: 131 mr |= USART_MR_CHRL_7BITS; 132 break; 133 case 8: 134 mr |= USART_MR_CHRL_8BITS; 135 break; 136 case 9: 137 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; 138 break; 139 default: 140 return (EINVAL); 141 } 142 143 /* 144 * Or in the parity 145 */ 146 switch (parity) { 147 case UART_PARITY_NONE: 148 mr |= USART_MR_PAR_NONE; 149 break; 150 case UART_PARITY_ODD: 151 mr |= USART_MR_PAR_ODD; 152 break; 153 case UART_PARITY_EVEN: 154 mr |= USART_MR_PAR_EVEN; 155 break; 156 case UART_PARITY_MARK: 157 mr |= USART_MR_PAR_MARK; 158 break; 159 case UART_PARITY_SPACE: 160 mr |= USART_MR_PAR_SPACE; 161 break; 162 default: 163 return (EINVAL); 164 } 165 166 /* 167 * Or in the stop bits. Note: The hardware supports 1.5 stop 168 * bits in async mode, but there's no way to specify that 169 * AFAICT. Instead, rely on the convention documented at 170 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which 171 * states that 1.5 stop bits are used for 5 bit bytes and 172 * 2 stop bits only for longer bytes. 173 */ 174 if (stopbits == 1) 175 mr |= USART_MR_NBSTOP_1; 176 else if (databits > 5) 177 mr |= USART_MR_NBSTOP_2; 178 else 179 mr |= USART_MR_NBSTOP_1_5; 180 181 /* 182 * We want normal plumbing mode too, none of this fancy 183 * loopback or echo mode. 184 */ 185 mr |= USART_MR_CHMODE_NORMAL; 186 187 mr &= ~USART_MR_MSBF; /* lsb first */ 188 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ 189 190 WR4(bas, USART_MR, mr); 191 192 /* 193 * Set the baud rate 194 */ 195 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 196 197 /* XXX Need to take possible synchronous mode into account */ 198 return (0); 199} 200 201static struct uart_ops at91_usart_ops = { 202 .probe = at91_usart_probe, 203 .init = at91_usart_init, 204 .term = at91_usart_term, 205 .putc = at91_usart_putc, 206 .rxready = at91_usart_rxready, 207 .getc = at91_usart_getc, 208}; 209 210static int 211at91_usart_probe(struct uart_bas *bas) 212{ 213 /* We know that this is always here */ 214 return (0); 215} 216 217/* 218 * Initialize this device for use as a console. 219 */ 220static void 221at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 222 int parity) 223{ 224 225 at91_usart_param(bas, baudrate, databits, stopbits, parity); 226 227 /* Reset the rx and tx buffers and turn on rx and tx */ 228 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 229 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 230 WR4(bas, USART_IDR, 0xffffffff); 231} 232 233/* 234 * Free resources now that we're no longer the console. This appears to 235 * be never called, and I'm unsure quite what to do if I am called. 236 */ 237static void 238at91_usart_term(struct uart_bas *bas) 239{ 240 /* XXX */ 241} 242 243/* 244 * Put a character of console output (so we do it here polling rather than 245 * interrutp driven). 246 */ 247static void 248at91_usart_putc(struct uart_bas *bas, int c) 249{ 250 251 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 252 continue; 253 WR4(bas, USART_THR, c); 254} 255 256/* 257 * Check for a character available. 258 */ 259static int 260at91_usart_rxready(struct uart_bas *bas) 261{ 262 263 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0); 264} 265 266/* 267 * Block waiting for a character. 268 */ 269static int 270at91_usart_getc(struct uart_bas *bas, struct mtx *mtx) 271{ 272 int c; 273 274 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) 275 continue; 276 c = RD4(bas, USART_RHR); 277 c &= 0xff; 278 return (c); 279} 280 281static int at91_usart_bus_probe(struct uart_softc *sc); 282static int at91_usart_bus_attach(struct uart_softc *sc); 283static int at91_usart_bus_flush(struct uart_softc *, int); 284static int at91_usart_bus_getsig(struct uart_softc *); 285static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t); 286static int at91_usart_bus_ipend(struct uart_softc *); 287static int at91_usart_bus_param(struct uart_softc *, int, int, int, int); 288static int at91_usart_bus_receive(struct uart_softc *); 289static int at91_usart_bus_setsig(struct uart_softc *, int); 290static int at91_usart_bus_transmit(struct uart_softc *); 291 292static kobj_method_t at91_usart_methods[] = { 293 KOBJMETHOD(uart_probe, at91_usart_bus_probe), 294 KOBJMETHOD(uart_attach, at91_usart_bus_attach), 295 KOBJMETHOD(uart_flush, at91_usart_bus_flush), 296 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig), 297 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl), 298 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend), 299 KOBJMETHOD(uart_param, at91_usart_bus_param), 300 KOBJMETHOD(uart_receive, at91_usart_bus_receive), 301 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig), 302 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit), 303 304 { 0, 0 } 305}; 306 307int 308at91_usart_bus_probe(struct uart_softc *sc) 309{ 310 return (0); 311} 312 313#ifndef SKYEYE_WORKAROUNDS 314static void 315at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 316{ 317 if (error != 0) 318 return; 319 *(bus_addr_t *)arg = segs[0].ds_addr; 320} 321#endif 322 323static int 324at91_usart_bus_attach(struct uart_softc *sc) 325{ 326#ifndef SKYEYE_WORKAROUNDS 327 int err; 328 int i; 329#endif 330 uint32_t cr; 331 struct at91_usart_softc *atsc; 332 333 atsc = (struct at91_usart_softc *)sc; 334 335 /* 336 * See if we have a TIMEOUT bit. We disable all interrupts as 337 * a side effect. Boot loaders may have enabled them. Since 338 * a TIMEOUT interrupt can't happen without other setup, the 339 * apparent race here can't actually happen. 340 */ 341 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 342 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT); 343 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) 344 atsc->flags |= HAS_TIMEOUT; 345 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 346 347 sc->sc_txfifosz = USART_BUFFER_SIZE; 348 sc->sc_rxfifosz = USART_BUFFER_SIZE; 349 sc->sc_hwiflow = 0; 350 351#ifndef SKYEYE_WORKAROUNDS 352 /* 353 * Allocate DMA tags and maps 354 */ 355 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 356 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 357 USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, 358 NULL, &atsc->dmatag); 359 if (err != 0) 360 goto errout; 361 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map); 362 if (err != 0) 363 goto errout; 364 if (atsc->flags & HAS_TIMEOUT) { 365 for (i = 0; i < 2; i++) { 366 err = bus_dmamap_create(atsc->dmatag, 0, 367 &atsc->ping_pong[i].map); 368 if (err != 0) 369 goto errout; 370 err = bus_dmamap_load(atsc->dmatag, 371 atsc->ping_pong[i].map, 372 atsc->ping_pong[i].buffer, sc->sc_rxfifosz, 373 at91_getaddr, &atsc->ping_pong[i].pa, 0); 374 if (err != 0) 375 goto errout; 376 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map, 377 BUS_DMASYNC_PREREAD); 378 } 379 atsc->ping = &atsc->ping_pong[0]; 380 atsc->pong = &atsc->ping_pong[1]; 381 } 382#endif 383 384 /* 385 * Prime the pump with the RX buffer. We use two 64 byte bounce 386 * buffers here to avoid data overflow. 387 */ 388 389 /* Turn on rx and tx */ 390 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; 391 WR4(&sc->sc_bas, USART_CR, cr); 392 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 393 394 /* 395 * Setup the PDC to receive data. We use the ping-pong buffers 396 * so that we can more easily bounce between the two and so that 397 * we get an interrupt 1/2 way through the software 'fifo' we have 398 * to avoid overruns. 399 */ 400 if (atsc->flags & HAS_TIMEOUT) { 401 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 402 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 403 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 404 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 405 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 406 407 /* Set the receive timeout to be 1.5 character times. */ 408 WR4(&sc->sc_bas, USART_RTOR, 12); 409 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 410 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | 411 USART_CSR_RXBUFF | USART_CSR_ENDRX); 412 } else { 413 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 414 } 415 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK); 416#ifndef SKYEYE_WORKAROUNDS 417errout:; 418 // XXX bad 419 return (err); 420#else 421 return (0); 422#endif 423} 424 425static int 426at91_usart_bus_transmit(struct uart_softc *sc) 427{ 428#ifndef SKYEYE_WORKAROUNDS 429 bus_addr_t addr; 430#endif 431 struct at91_usart_softc *atsc; 432 433 atsc = (struct at91_usart_softc *)sc; 434#ifndef SKYEYE_WORKAROUNDS 435 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf, 436 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) 437 return (EAGAIN); 438 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE); 439#endif 440 441 uart_lock(sc->sc_hwmtx); 442 sc->sc_txbusy = 1; 443#ifndef SKYEYE_WORKAROUNDS 444 /* 445 * Setup the PDC to transfer the data and interrupt us when it 446 * is done. We've already requested the interrupt. 447 */ 448 WR4(&sc->sc_bas, PDC_TPR, addr); 449 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz); 450 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN); 451 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX); 452 uart_unlock(sc->sc_hwmtx); 453#else 454 for (int i = 0; i < sc->sc_txdatasz; i++) 455 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]); 456 /* 457 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the 458 * transfer is done, so simulate it. 459 */ 460 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY); 461#endif 462 return (0); 463} 464static int 465at91_usart_bus_setsig(struct uart_softc *sc, int sig) 466{ 467 uint32_t new, old, cr; 468 struct uart_bas *bas; 469 470 do { 471 old = sc->sc_hwsig; 472 new = old; 473 if (sig & SER_DDTR) 474 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 475 if (sig & SER_DRTS) 476 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 477 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 478 bas = &sc->sc_bas; 479 uart_lock(sc->sc_hwmtx); 480 cr = 0; 481 if (new & SER_DTR) 482 cr |= USART_CR_DTREN; 483 else 484 cr |= USART_CR_DTRDIS; 485 if (new & SER_RTS) 486 cr |= USART_CR_RTSEN; 487 else 488 cr |= USART_CR_RTSDIS; 489 WR4(bas, USART_CR, cr); 490 uart_unlock(sc->sc_hwmtx); 491 return (0); 492} 493static int 494at91_usart_bus_receive(struct uart_softc *sc) 495{ 496 497 return (0); 498} 499static int 500at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits, 501 int stopbits, int parity) 502{ 503 504 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits, 505 parity)); 506} 507 508static __inline void 509at91_rx_put(struct uart_softc *sc, int key) 510{ 511#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER) 512 int kdb_brk; 513 514 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 515 if ((kdb_brk = kdb_alt_break(key, &sc->sc_altbrk)) != 0) { 516 switch (kdb_brk) { 517 case KDB_REQ_DEBUGGER: 518 kdb_enter(KDB_WHY_BREAK, 519 "Break sequence on console"); 520 break; 521 case KDB_REQ_PANIC: 522 kdb_panic("Panic sequence on console"); 523 break; 524 case KDB_REQ_REBOOT: 525 kdb_reboot(); 526 break; 527 } 528 } 529 } 530#endif 531 uart_rx_put(sc, key); 532} 533 534static int 535at91_usart_bus_ipend(struct uart_softc *sc) 536{ 537 int csr = RD4(&sc->sc_bas, USART_CSR); 538 int ipend = 0, i, len; 539 struct at91_usart_softc *atsc; 540 struct at91_usart_rx *p; 541 542 atsc = (struct at91_usart_softc *)sc; 543 if (csr & USART_CSR_ENDTX) { 544 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, 545 BUS_DMASYNC_POSTWRITE); 546 bus_dmamap_unload(atsc->dmatag, atsc->tx_map); 547 } 548 uart_lock(sc->sc_hwmtx); 549 if (csr & USART_CSR_TXRDY) { 550 if (sc->sc_txbusy) 551 ipend |= SER_INT_TXIDLE; 552 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY); 553 } 554 if (csr & USART_CSR_ENDTX) { 555 if (sc->sc_txbusy) 556 ipend |= SER_INT_TXIDLE; 557 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX); 558 } 559 560 /* 561 * Due to the contraints of the DMA engine present in the 562 * atmel chip, I can't just say I have a rx interrupt pending 563 * and do all the work elsewhere. I need to look at the CSR 564 * bits right now and do things based on them to avoid races. 565 */ 566 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) { 567 // Have a buffer overflow. Copy all data from both 568 // ping and pong. Insert overflow character. Reset 569 // ping and pong and re-enable the PDC to receive 570 // characters again. 571 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 572 BUS_DMASYNC_POSTREAD); 573 bus_dmamap_sync(atsc->dmatag, atsc->pong->map, 574 BUS_DMASYNC_POSTREAD); 575 for (i = 0; i < sc->sc_rxfifosz; i++) 576 at91_rx_put(sc, atsc->ping->buffer[i]); 577 for (i = 0; i < sc->sc_rxfifosz; i++) 578 at91_rx_put(sc, atsc->pong->buffer[i]); 579 uart_rx_put(sc, UART_STAT_OVERRUN); 580 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT); 581 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 582 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 583 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 584 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 585 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 586 ipend |= SER_INT_RXREADY; 587 } 588 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) { 589 // Shuffle data from 'ping' of ping pong buffer, but 590 // leave current 'pong' in place, as it has become the 591 // new 'ping'. We need to copy data and setup the old 592 // 'ping' as the new 'pong' when we're done. 593 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 594 BUS_DMASYNC_POSTREAD); 595 for (i = 0; i < sc->sc_rxfifosz; i++) 596 at91_rx_put(sc, atsc->ping->buffer[i]); 597 p = atsc->ping; 598 atsc->ping = atsc->pong; 599 atsc->pong = p; 600 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 601 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 602 ipend |= SER_INT_RXREADY; 603 } 604 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) { 605 // We have one partial buffer. We need to stop the 606 // PDC, get the number of characters left and from 607 // that compute number of valid characters. We then 608 // need to reset ping and pong and reenable the PDC. 609 // Not sure if there's a race here at fast baud rates 610 // we need to worry about. 611 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 612 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 613 BUS_DMASYNC_POSTREAD); 614 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); 615 for (i = 0; i < len; i++) 616 at91_rx_put(sc, atsc->ping->buffer[i]); 617 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 618 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 619 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 620 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 621 ipend |= SER_INT_RXREADY; 622 } 623 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) { 624 // We have another charater in a device that doesn't support 625 // timeouts, so we do it one character at a time. 626 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); 627 ipend |= SER_INT_RXREADY; 628 } 629 630 if (csr & USART_CSR_RXBRK) { 631 unsigned int cr = USART_CR_RSTSTA; 632 633 ipend |= SER_INT_BREAK; 634 WR4(&sc->sc_bas, USART_CR, cr); 635 } 636 uart_unlock(sc->sc_hwmtx); 637 return (ipend); 638} 639static int 640at91_usart_bus_flush(struct uart_softc *sc, int what) 641{ 642 return (0); 643} 644 645static int 646at91_usart_bus_getsig(struct uart_softc *sc) 647{ 648 uint32_t new, sig; 649 uint8_t csr; 650 651 uart_lock(sc->sc_hwmtx); 652 csr = RD4(&sc->sc_bas, USART_CSR); 653 sig = 0; 654 if (csr & USART_CSR_CTS) 655 sig |= SER_CTS; 656 if (csr & USART_CSR_DCD) 657 sig |= SER_DCD; 658 if (csr & USART_CSR_DSR) 659 sig |= SER_DSR; 660 if (csr & USART_CSR_RI) 661 sig |= SER_RI; 662 new = sig & ~SER_MASK_DELTA; 663 sc->sc_hwsig = new; 664 uart_unlock(sc->sc_hwmtx); 665 return (sig); 666} 667 668static int 669at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 670{ 671 switch (request) { 672 case UART_IOCTL_BREAK: 673 case UART_IOCTL_IFLOW: 674 case UART_IOCTL_OFLOW: 675 break; 676 case UART_IOCTL_BAUD: 677 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data)); 678 return (0); 679 } 680 return (EINVAL); 681} 682 683struct uart_class at91_usart_class = { 684 "at91_usart", 685 at91_usart_methods, 686 sizeof(struct at91_usart_softc), 687 .uc_ops = &at91_usart_ops, 688 .uc_range = 8 689}; 690