uart_dev_at91usart.c revision 185049
1/*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 Olivier Houchard 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/arm/at91/uart_dev_at91usart.c 185049 2008-11-18 12:42:59Z stas $"); 30 31#include "opt_comconsole.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/cons.h> 38#include <sys/tty.h> 39#include <machine/bus.h> 40 41#include <dev/uart/uart.h> 42#include <dev/uart/uart_cpu.h> 43#include <dev/uart/uart_bus.h> 44#include <arm/at91/at91rm92reg.h> 45#include <arm/at91/at91_usartreg.h> 46#include <arm/at91/at91_pdcreg.h> 47 48#include "uart_if.h" 49 50#define DEFAULT_RCLK AT91C_MASTER_CLOCK 51#define USART_BUFFER_SIZE 128 52 53/* 54 * High-level UART interface. 55 */ 56struct at91_usart_rx { 57 bus_addr_t pa; 58 uint8_t buffer[USART_BUFFER_SIZE]; 59 bus_dmamap_t map; 60}; 61 62struct at91_usart_softc { 63 struct uart_softc base; 64 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */ 65 bus_dmamap_t tx_map; 66 uint32_t flags; 67#define HAS_TIMEOUT 1 68 struct at91_usart_rx ping_pong[2]; 69 struct at91_usart_rx *ping; 70 struct at91_usart_rx *pong; 71}; 72 73#define RD4(bas, reg) \ 74 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 75#define WR4(bas, reg, value) \ 76 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 77 78#define SIGCHG(c, i, s, d) \ 79 do { \ 80 if (c) { \ 81 i |= (i & s) ? s : s | d; \ 82 } else { \ 83 i = (i & s) ? (i & ~s) | d : i; \ 84 } \ 85 } while (0); 86 87#define BAUD2DIVISOR(b) \ 88 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10) 89 90/* 91 * Low-level UART interface. 92 */ 93static int at91_usart_probe(struct uart_bas *bas); 94static void at91_usart_init(struct uart_bas *bas, int, int, int, int); 95static void at91_usart_term(struct uart_bas *bas); 96static void at91_usart_putc(struct uart_bas *bas, int); 97static int at91_usart_rxready(struct uart_bas *bas); 98static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx); 99 100extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 101 102static int 103at91_usart_param(struct uart_bas *bas, int baudrate, int databits, 104 int stopbits, int parity) 105{ 106 uint32_t mr; 107 108 /* 109 * Assume 3-write RS-232 configuration. 110 * XXX Not sure how uart will present the other modes to us, so 111 * XXX they are unimplemented. maybe ioctl? 112 */ 113 mr = USART_MR_MODE_NORMAL; 114 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ 115 116 /* 117 * Or in the databits requested 118 */ 119 if (databits < 9) 120 mr &= ~USART_MR_MODE9; 121 switch (databits) { 122 case 5: 123 mr |= USART_MR_CHRL_5BITS; 124 break; 125 case 6: 126 mr |= USART_MR_CHRL_6BITS; 127 break; 128 case 7: 129 mr |= USART_MR_CHRL_7BITS; 130 break; 131 case 8: 132 mr |= USART_MR_CHRL_8BITS; 133 break; 134 case 9: 135 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; 136 break; 137 default: 138 return (EINVAL); 139 } 140 141 /* 142 * Or in the parity 143 */ 144 switch (parity) { 145 case UART_PARITY_NONE: 146 mr |= USART_MR_PAR_NONE; 147 break; 148 case UART_PARITY_ODD: 149 mr |= USART_MR_PAR_ODD; 150 break; 151 case UART_PARITY_EVEN: 152 mr |= USART_MR_PAR_EVEN; 153 break; 154 case UART_PARITY_MARK: 155 mr |= USART_MR_PAR_MARK; 156 break; 157 case UART_PARITY_SPACE: 158 mr |= USART_MR_PAR_SPACE; 159 break; 160 default: 161 return (EINVAL); 162 } 163 164 /* 165 * Or in the stop bits. Note: The hardware supports 1.5 stop 166 * bits in async mode, but there's no way to specify that 167 * AFAICT. Instead, rely on the convention documented at 168 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which 169 * states that 1.5 stop bits are used for 5 bit bytes and 170 * 2 stop bits only for longer bytes. 171 */ 172 if (stopbits == 1) 173 mr |= USART_MR_NBSTOP_1; 174 else if (databits > 5) 175 mr |= USART_MR_NBSTOP_2; 176 else 177 mr |= USART_MR_NBSTOP_1_5; 178 179 /* 180 * We want normal plumbing mode too, none of this fancy 181 * loopback or echo mode. 182 */ 183 mr |= USART_MR_CHMODE_NORMAL; 184 185 mr &= ~USART_MR_MSBF; /* lsb first */ 186 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ 187 188 WR4(bas, USART_MR, mr); 189 190 /* 191 * Set the baud rate 192 */ 193 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 194 195 /* XXX Need to take possible synchronous mode into account */ 196 return (0); 197} 198 199static struct uart_ops at91_usart_ops = { 200 .probe = at91_usart_probe, 201 .init = at91_usart_init, 202 .term = at91_usart_term, 203 .putc = at91_usart_putc, 204 .rxready = at91_usart_rxready, 205 .getc = at91_usart_getc, 206}; 207 208static int 209at91_usart_probe(struct uart_bas *bas) 210{ 211 /* We know that this is always here */ 212 return (0); 213} 214 215/* 216 * Initialize this device for use as a console. 217 */ 218static void 219at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 220 int parity) 221{ 222 223 at91_usart_param(bas, baudrate, databits, stopbits, parity); 224 225 /* Reset the rx and tx buffers and turn on rx and tx */ 226 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 227 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 228 WR4(bas, USART_IDR, 0xffffffff); 229} 230 231/* 232 * Free resources now that we're no longer the console. This appears to 233 * be never called, and I'm unsure quite what to do if I am called. 234 */ 235static void 236at91_usart_term(struct uart_bas *bas) 237{ 238 /* XXX */ 239} 240 241/* 242 * Put a character of console output (so we do it here polling rather than 243 * interrutp driven). 244 */ 245static void 246at91_usart_putc(struct uart_bas *bas, int c) 247{ 248 249 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 250 continue; 251 WR4(bas, USART_THR, c); 252} 253 254/* 255 * Check for a character available. 256 */ 257static int 258at91_usart_rxready(struct uart_bas *bas) 259{ 260 261 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0); 262} 263 264/* 265 * Block waiting for a character. 266 */ 267static int 268at91_usart_getc(struct uart_bas *bas, struct mtx *mtx) 269{ 270 int c; 271 272 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) 273 continue; 274 c = RD4(bas, USART_RHR); 275 c &= 0xff; 276 return (c); 277} 278 279static int at91_usart_bus_probe(struct uart_softc *sc); 280static int at91_usart_bus_attach(struct uart_softc *sc); 281static int at91_usart_bus_flush(struct uart_softc *, int); 282static int at91_usart_bus_getsig(struct uart_softc *); 283static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t); 284static int at91_usart_bus_ipend(struct uart_softc *); 285static int at91_usart_bus_param(struct uart_softc *, int, int, int, int); 286static int at91_usart_bus_receive(struct uart_softc *); 287static int at91_usart_bus_setsig(struct uart_softc *, int); 288static int at91_usart_bus_transmit(struct uart_softc *); 289 290static kobj_method_t at91_usart_methods[] = { 291 KOBJMETHOD(uart_probe, at91_usart_bus_probe), 292 KOBJMETHOD(uart_attach, at91_usart_bus_attach), 293 KOBJMETHOD(uart_flush, at91_usart_bus_flush), 294 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig), 295 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl), 296 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend), 297 KOBJMETHOD(uart_param, at91_usart_bus_param), 298 KOBJMETHOD(uart_receive, at91_usart_bus_receive), 299 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig), 300 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit), 301 302 { 0, 0 } 303}; 304 305int 306at91_usart_bus_probe(struct uart_softc *sc) 307{ 308 return (0); 309} 310 311#ifndef SKYEYE_WORKAROUNDS 312static void 313at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 314{ 315 if (error != 0) 316 return; 317 *(bus_addr_t *)arg = segs[0].ds_addr; 318} 319#endif 320 321static int 322at91_usart_bus_attach(struct uart_softc *sc) 323{ 324#ifndef SKYEYE_WORKAROUNDS 325 int err; 326 int i; 327#endif 328 uint32_t cr; 329 struct at91_usart_softc *atsc; 330 331 atsc = (struct at91_usart_softc *)sc; 332 333 /* 334 * See if we have a TIMEOUT bit. We disable all interrupts as 335 * a side effect. Boot loaders may have enabled them. Since 336 * a TIMEOUT interrupt can't happen without other setup, the 337 * apparent race here can't actually happen. 338 */ 339 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 340 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT); 341 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) 342 atsc->flags |= HAS_TIMEOUT; 343 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 344 345 sc->sc_txfifosz = USART_BUFFER_SIZE; 346 sc->sc_rxfifosz = USART_BUFFER_SIZE; 347 sc->sc_hwiflow = 0; 348 349#ifndef SKYEYE_WORKAROUNDS 350 /* 351 * Allocate DMA tags and maps 352 */ 353 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 354 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 355 USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, 356 NULL, &atsc->dmatag); 357 if (err != 0) 358 goto errout; 359 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map); 360 if (err != 0) 361 goto errout; 362 if (atsc->flags & HAS_TIMEOUT) { 363 for (i = 0; i < 2; i++) { 364 err = bus_dmamap_create(atsc->dmatag, 0, 365 &atsc->ping_pong[i].map); 366 if (err != 0) 367 goto errout; 368 err = bus_dmamap_load(atsc->dmatag, 369 atsc->ping_pong[i].map, 370 atsc->ping_pong[i].buffer, sc->sc_rxfifosz, 371 at91_getaddr, &atsc->ping_pong[i].pa, 0); 372 if (err != 0) 373 goto errout; 374 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map, 375 BUS_DMASYNC_PREREAD); 376 } 377 atsc->ping = &atsc->ping_pong[0]; 378 atsc->pong = &atsc->ping_pong[1]; 379 } 380#endif 381 382 /* 383 * Prime the pump with the RX buffer. We use two 64 byte bounce 384 * buffers here to avoid data overflow. 385 */ 386 387 /* Turn on rx and tx */ 388 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; 389 WR4(&sc->sc_bas, USART_CR, cr); 390 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 391 392 /* 393 * Setup the PDC to receive data. We use the ping-pong buffers 394 * so that we can more easily bounce between the two and so that 395 * we get an interrupt 1/2 way through the software 'fifo' we have 396 * to avoid overruns. 397 */ 398 if (atsc->flags & HAS_TIMEOUT) { 399 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 400 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 401 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 402 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 403 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 404 405 /* Set the receive timeout to be 1.5 character times. */ 406 WR4(&sc->sc_bas, USART_RTOR, 12); 407 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 408 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | 409 USART_CSR_RXBUFF | USART_CSR_ENDRX); 410 } else { 411 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 412 } 413 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK); 414#ifndef SKYEYE_WORKAROUNDS 415errout:; 416 // XXX bad 417 return (err); 418#else 419 return (0); 420#endif 421} 422 423static int 424at91_usart_bus_transmit(struct uart_softc *sc) 425{ 426#ifndef SKYEYE_WORKAROUNDS 427 bus_addr_t addr; 428#endif 429 struct at91_usart_softc *atsc; 430 431 atsc = (struct at91_usart_softc *)sc; 432#ifndef SKYEYE_WORKAROUNDS 433 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf, 434 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) 435 return (EAGAIN); 436 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE); 437#endif 438 439 uart_lock(sc->sc_hwmtx); 440 sc->sc_txbusy = 1; 441#ifndef SKYEYE_WORKAROUNDS 442 /* 443 * Setup the PDC to transfer the data and interrupt us when it 444 * is done. We've already requested the interrupt. 445 */ 446 WR4(&sc->sc_bas, PDC_TPR, addr); 447 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz); 448 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN); 449 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX); 450 uart_unlock(sc->sc_hwmtx); 451#else 452 for (int i = 0; i < sc->sc_txdatasz; i++) 453 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]); 454 /* 455 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the 456 * transfer is done, so simulate it. 457 */ 458 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY); 459#endif 460 return (0); 461} 462static int 463at91_usart_bus_setsig(struct uart_softc *sc, int sig) 464{ 465 uint32_t new, old, cr; 466 struct uart_bas *bas; 467 468 do { 469 old = sc->sc_hwsig; 470 new = old; 471 if (sig & SER_DDTR) 472 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 473 if (sig & SER_DRTS) 474 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 475 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 476 bas = &sc->sc_bas; 477 uart_lock(sc->sc_hwmtx); 478 cr = 0; 479 if (new & SER_DTR) 480 cr |= USART_CR_DTREN; 481 else 482 cr |= USART_CR_DTRDIS; 483 if (new & SER_RTS) 484 cr |= USART_CR_RTSEN; 485 else 486 cr |= USART_CR_RTSDIS; 487 WR4(bas, USART_CR, cr); 488 uart_unlock(sc->sc_hwmtx); 489 return (0); 490} 491static int 492at91_usart_bus_receive(struct uart_softc *sc) 493{ 494 495 return (0); 496} 497static int 498at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits, 499 int stopbits, int parity) 500{ 501 502 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits, 503 parity)); 504} 505 506static __inline void 507at91_rx_put(struct uart_softc *sc, int key) 508{ 509#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER) 510 int kdb_brk; 511 512 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 513 if ((kdb_brk = kdb_alt_break(key, &sc->sc_altbrk)) != 0) { 514 switch (kdb_brk) { 515 case KDB_REQ_DEBUGGER: 516 kdb_enter(KDB_WHY_BREAK, 517 "Break sequence on console"); 518 break; 519 case KDB_REQ_PANIC: 520 kdb_panic("Panic sequence on console"); 521 break; 522 case KDB_REQ_REBOOT: 523 kdb_reboot(); 524 break; 525 } 526 } 527 } 528#endif 529 uart_rx_put(sc, key); 530} 531 532static int 533at91_usart_bus_ipend(struct uart_softc *sc) 534{ 535 int csr = RD4(&sc->sc_bas, USART_CSR); 536 int ipend = 0, i, len; 537 struct at91_usart_softc *atsc; 538 struct at91_usart_rx *p; 539 540 atsc = (struct at91_usart_softc *)sc; 541 if (csr & USART_CSR_ENDTX) { 542 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, 543 BUS_DMASYNC_POSTWRITE); 544 bus_dmamap_unload(atsc->dmatag, atsc->tx_map); 545 } 546 uart_lock(sc->sc_hwmtx); 547 if (csr & USART_CSR_TXRDY) { 548 if (sc->sc_txbusy) 549 ipend |= SER_INT_TXIDLE; 550 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY); 551 } 552 if (csr & USART_CSR_ENDTX) { 553 if (sc->sc_txbusy) 554 ipend |= SER_INT_TXIDLE; 555 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX); 556 } 557 558 /* 559 * Due to the contraints of the DMA engine present in the 560 * atmel chip, I can't just say I have a rx interrupt pending 561 * and do all the work elsewhere. I need to look at the CSR 562 * bits right now and do things based on them to avoid races. 563 */ 564 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) { 565 // Have a buffer overflow. Copy all data from both 566 // ping and pong. Insert overflow character. Reset 567 // ping and pong and re-enable the PDC to receive 568 // characters again. 569 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 570 BUS_DMASYNC_POSTREAD); 571 bus_dmamap_sync(atsc->dmatag, atsc->pong->map, 572 BUS_DMASYNC_POSTREAD); 573 for (i = 0; i < sc->sc_rxfifosz; i++) 574 at91_rx_put(sc, atsc->ping->buffer[i]); 575 for (i = 0; i < sc->sc_rxfifosz; i++) 576 at91_rx_put(sc, atsc->pong->buffer[i]); 577 uart_rx_put(sc, UART_STAT_OVERRUN); 578 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT); 579 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 580 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 581 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 582 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 583 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 584 ipend |= SER_INT_RXREADY; 585 } 586 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) { 587 // Shuffle data from 'ping' of ping pong buffer, but 588 // leave current 'pong' in place, as it has become the 589 // new 'ping'. We need to copy data and setup the old 590 // 'ping' as the new 'pong' when we're done. 591 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 592 BUS_DMASYNC_POSTREAD); 593 for (i = 0; i < sc->sc_rxfifosz; i++) 594 at91_rx_put(sc, atsc->ping->buffer[i]); 595 p = atsc->ping; 596 atsc->ping = atsc->pong; 597 atsc->pong = p; 598 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 599 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 600 ipend |= SER_INT_RXREADY; 601 } 602 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) { 603 // We have one partial buffer. We need to stop the 604 // PDC, get the number of characters left and from 605 // that compute number of valid characters. We then 606 // need to reset ping and pong and reenable the PDC. 607 // Not sure if there's a race here at fast baud rates 608 // we need to worry about. 609 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 610 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 611 BUS_DMASYNC_POSTREAD); 612 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); 613 for (i = 0; i < len; i++) 614 at91_rx_put(sc, atsc->ping->buffer[i]); 615 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 616 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 617 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 618 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 619 ipend |= SER_INT_RXREADY; 620 } 621 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) { 622 // We have another charater in a device that doesn't support 623 // timeouts, so we do it one character at a time. 624 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); 625 ipend |= SER_INT_RXREADY; 626 } 627 628 if (csr & USART_CSR_RXBRK) { 629 unsigned int cr = USART_CR_RSTSTA; 630 631 ipend |= SER_INT_BREAK; 632 WR4(&sc->sc_bas, USART_CR, cr); 633 } 634 uart_unlock(sc->sc_hwmtx); 635 return (ipend); 636} 637static int 638at91_usart_bus_flush(struct uart_softc *sc, int what) 639{ 640 return (0); 641} 642 643static int 644at91_usart_bus_getsig(struct uart_softc *sc) 645{ 646 uint32_t new, sig; 647 uint8_t csr; 648 649 uart_lock(sc->sc_hwmtx); 650 csr = RD4(&sc->sc_bas, USART_CSR); 651 sig = 0; 652 if (csr & USART_CSR_CTS) 653 sig |= SER_CTS; 654 if (csr & USART_CSR_DCD) 655 sig |= SER_DCD; 656 if (csr & USART_CSR_DSR) 657 sig |= SER_DSR; 658 if (csr & USART_CSR_RI) 659 sig |= SER_RI; 660 new = sig & ~SER_MASK_DELTA; 661 sc->sc_hwsig = new; 662 uart_unlock(sc->sc_hwmtx); 663 return (sig); 664} 665 666static int 667at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 668{ 669 switch (request) { 670 case UART_IOCTL_BREAK: 671 case UART_IOCTL_IFLOW: 672 case UART_IOCTL_OFLOW: 673 break; 674 case UART_IOCTL_BAUD: 675 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data)); 676 return (0); 677 } 678 return (EINVAL); 679} 680 681struct uart_class at91_usart_class = { 682 "at91_usart", 683 at91_usart_methods, 684 sizeof(struct at91_usart_softc), 685 .uc_ops = &at91_usart_ops, 686 .uc_range = 8, 687 .uc_rclk = DEFAULT_RCLK 688}; 689