uart_dev_at91usart.c revision 160357
1/*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 Olivier Houchard 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/arm/at91/uart_dev_at91usart.c 160357 2006-07-14 21:33:04Z imp $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/cons.h> 36#include <sys/tty.h> 37#include <machine/bus.h> 38 39#include <dev/uart/uart.h> 40#include <dev/uart/uart_cpu.h> 41#include <dev/uart/uart_bus.h> 42#include <arm/at91/at91rm92reg.h> 43#include <arm/at91/at91_usartreg.h> 44#include <arm/at91/at91_pdcreg.h> 45 46#include "uart_if.h" 47 48#define DEFAULT_RCLK AT91C_MASTER_CLOCK 49#define USART_BUFFER_SIZE 128 50 51/* 52 * High-level UART interface. 53 */ 54struct at91_usart_rx { 55 bus_addr_t pa; 56 uint8_t buffer[USART_BUFFER_SIZE]; 57 bus_dmamap_t map; 58}; 59 60struct at91_usart_softc { 61 struct uart_softc base; 62 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */ 63 bus_dmamap_t tx_map; 64 uint32_t flags; 65#define HAS_TIMEOUT 1 66 struct at91_usart_rx ping_pong[2]; 67 struct at91_usart_rx *ping; 68 struct at91_usart_rx *pong; 69}; 70 71#define RD4(bas, reg) \ 72 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 73#define WR4(bas, reg, value) \ 74 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 75 76#define SIGCHG(c, i, s, d) \ 77 do { \ 78 if (c) { \ 79 i |= (i & s) ? s : s | d; \ 80 } else { \ 81 i = (i & s) ? (i & ~s) | d : i; \ 82 } \ 83 } while (0); 84 85#define BAUD2DIVISOR(b) \ 86 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10) 87 88/* 89 * Low-level UART interface. 90 */ 91static int at91_usart_probe(struct uart_bas *bas); 92static void at91_usart_init(struct uart_bas *bas, int, int, int, int); 93static void at91_usart_term(struct uart_bas *bas); 94static void at91_usart_putc(struct uart_bas *bas, int); 95static int at91_usart_poll(struct uart_bas *bas); 96static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx); 97 98extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 99 100static int 101at91_usart_param(struct uart_bas *bas, int baudrate, int databits, 102 int stopbits, int parity) 103{ 104 uint32_t mr; 105 106 /* 107 * Assume 3-write RS-232 configuration. 108 * XXX Not sure how uart will present the other modes to us, so 109 * XXX they are unimplemented. maybe ioctl? 110 */ 111 mr = USART_MR_MODE_NORMAL; 112 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ 113 114 /* 115 * Or in the databits requested 116 */ 117 if (databits < 9) 118 mr &= ~USART_MR_MODE9; 119 switch (databits) { 120 case 5: 121 mr |= USART_MR_CHRL_5BITS; 122 break; 123 case 6: 124 mr |= USART_MR_CHRL_6BITS; 125 break; 126 case 7: 127 mr |= USART_MR_CHRL_7BITS; 128 break; 129 case 8: 130 mr |= USART_MR_CHRL_8BITS; 131 break; 132 case 9: 133 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; 134 break; 135 default: 136 return (EINVAL); 137 } 138 139 /* 140 * Or in the parity 141 */ 142 switch (parity) { 143 case UART_PARITY_NONE: 144 mr |= USART_MR_PAR_NONE; 145 break; 146 case UART_PARITY_ODD: 147 mr |= USART_MR_PAR_ODD; 148 break; 149 case UART_PARITY_EVEN: 150 mr |= USART_MR_PAR_EVEN; 151 break; 152 case UART_PARITY_MARK: 153 mr |= USART_MR_PAR_MARK; 154 break; 155 case UART_PARITY_SPACE: 156 mr |= USART_MR_PAR_SPACE; 157 break; 158 default: 159 return (EINVAL); 160 } 161 162 /* 163 * Or in the stop bits. Note: The hardware supports 1.5 stop 164 * bits in async mode, but there's no way to specify that 165 * AFAICT. Instead, rely on the convention documented at 166 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which 167 * states that 1.5 stop bits are used for 5 bit bytes and 168 * 2 stop bits only for longer bytes. 169 */ 170 if (stopbits == 1) 171 mr |= USART_MR_NBSTOP_1; 172 else if (databits > 5) 173 mr |= USART_MR_NBSTOP_2; 174 else 175 mr |= USART_MR_NBSTOP_1_5; 176 177 /* 178 * We want normal plumbing mode too, none of this fancy 179 * loopback or echo mode. 180 */ 181 mr |= USART_MR_CHMODE_NORMAL; 182 183 mr &= ~USART_MR_MSBF; /* lsb first */ 184 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ 185 186 WR4(bas, USART_MR, mr); 187 188 /* 189 * Set the baud rate 190 */ 191 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 192 193 /* XXX Need to take possible synchronous mode into account */ 194 return (0); 195} 196 197struct uart_ops at91_usart_ops = { 198 .probe = at91_usart_probe, 199 .init = at91_usart_init, 200 .term = at91_usart_term, 201 .putc = at91_usart_putc, 202 .poll = at91_usart_poll, 203 .getc = at91_usart_getc, 204}; 205 206static int 207at91_usart_probe(struct uart_bas *bas) 208{ 209 /* We know that this is always here */ 210 return (0); 211} 212 213/* 214 * Initialize this device for use as a console. 215 */ 216static void 217at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 218 int parity) 219{ 220 221 at91_usart_param(bas, baudrate, databits, stopbits, parity); 222 223 /* Reset the rx and tx buffers and turn on rx and tx */ 224 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 225 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 226 WR4(bas, USART_IDR, 0xffffffff); 227} 228 229/* 230 * Free resources now that we're no longer the console. This appears to 231 * be never called, and I'm unsure quite what to do if I am called. 232 */ 233static void 234at91_usart_term(struct uart_bas *bas) 235{ 236 /* XXX */ 237} 238 239/* 240 * Put a character of console output (so we do it here polling rather than 241 * interrutp driven). 242 */ 243static void 244at91_usart_putc(struct uart_bas *bas, int c) 245{ 246 247 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 248 continue; 249 WR4(bas, USART_THR, c); 250} 251 252/* 253 * Poll for a character available 254 */ 255static int 256at91_usart_poll(struct uart_bas *bas) 257{ 258 259 if (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) 260 return (-1); 261 return (RD4(bas, USART_RHR) & 0xff); 262} 263 264/* 265 * Block waiting for a character. 266 */ 267static int 268at91_usart_getc(struct uart_bas *bas, struct mtx *mtx) 269{ 270 int c; 271 272 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) 273 continue; 274 c = RD4(bas, USART_RHR); 275 c &= 0xff; 276 return (c); 277} 278 279static int at91_usart_bus_probe(struct uart_softc *sc); 280static int at91_usart_bus_attach(struct uart_softc *sc); 281static int at91_usart_bus_flush(struct uart_softc *, int); 282static int at91_usart_bus_getsig(struct uart_softc *); 283static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t); 284static int at91_usart_bus_ipend(struct uart_softc *); 285static int at91_usart_bus_param(struct uart_softc *, int, int, int, int); 286static int at91_usart_bus_receive(struct uart_softc *); 287static int at91_usart_bus_setsig(struct uart_softc *, int); 288static int at91_usart_bus_transmit(struct uart_softc *); 289 290static kobj_method_t at91_usart_methods[] = { 291 KOBJMETHOD(uart_probe, at91_usart_bus_probe), 292 KOBJMETHOD(uart_attach, at91_usart_bus_attach), 293 KOBJMETHOD(uart_flush, at91_usart_bus_flush), 294 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig), 295 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl), 296 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend), 297 KOBJMETHOD(uart_param, at91_usart_bus_param), 298 KOBJMETHOD(uart_receive, at91_usart_bus_receive), 299 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig), 300 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit), 301 302 { 0, 0 } 303}; 304 305int 306at91_usart_bus_probe(struct uart_softc *sc) 307{ 308 return (0); 309} 310 311#ifndef SKYEYE_WORKAROUNDS 312static void 313at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 314{ 315 if (error != 0) 316 return; 317 *(bus_addr_t *)arg = segs[0].ds_addr; 318} 319#endif 320 321static int 322at91_usart_bus_attach(struct uart_softc *sc) 323{ 324 int err, i; 325 uint32_t cr; 326 struct at91_usart_softc *atsc; 327 328 atsc = (struct at91_usart_softc *)sc; 329 330 /* 331 * See if we have a TIMEOUT bit. We disable all interrupts as 332 * a side effect. Boot loaders may have enabled them. Since 333 * a TIMEOUT interrupt can't happen without other setup, the 334 * apparent race here can't actually happen. 335 */ 336 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 337 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT); 338 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) 339 atsc->flags |= HAS_TIMEOUT; 340 WR4(&sc->sc_bas, USART_IDR, 0xffffffff); 341 342 sc->sc_txfifosz = USART_BUFFER_SIZE; 343 sc->sc_rxfifosz = USART_BUFFER_SIZE; 344 sc->sc_hwiflow = 0; 345 346 /* 347 * Allocate DMA tags and maps 348 */ 349 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 350 BUS_SPACE_MAXADDR, NULL, NULL, USART_BUFFER_SIZE, 1, 351 USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &atsc->dmatag); 352 if (err != 0) 353 goto errout; 354 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map); 355 if (err != 0) 356 goto errout; 357 if (atsc->flags & HAS_TIMEOUT) { 358 for (i = 0; i < 2; i++) { 359 err = bus_dmamap_create(atsc->dmatag, 0, 360 &atsc->ping_pong[i].map); 361 if (err != 0) 362 goto errout; 363 err = bus_dmamap_load(atsc->dmatag, 364 atsc->ping_pong[i].map, 365 atsc->ping_pong[i].buffer, sc->sc_rxfifosz, 366 at91_getaddr, &atsc->ping_pong[i].pa, 0); 367 if (err != 0) 368 goto errout; 369 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map, 370 BUS_DMASYNC_PREREAD); 371 } 372 atsc->ping = &atsc->ping_pong[0]; 373 atsc->pong = &atsc->ping_pong[1]; 374 } 375 376 /* 377 * Prime the pump with the RX buffer. We use two 64 byte bounce 378 * buffers here to avoid data overflow. 379 */ 380 381 /* Turn on rx and tx */ 382 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; 383 WR4(&sc->sc_bas, USART_CR, cr); 384 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 385 386 /* 387 * Setup the PDC to receive data. We use the ping-pong buffers 388 * so that we can more easily bounce between the two and so that 389 * we get an interrupt 1/2 way through the software 'fifo' we have 390 * to avoid overruns. 391 */ 392 if (atsc->flags & HAS_TIMEOUT) { 393 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 394 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 395 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 396 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 397 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 398 399 /* Set the receive timeout to be 1.5 character times. */ 400 WR4(&sc->sc_bas, USART_RTOR, 12); 401 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 402 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT | 403 USART_CSR_RXBUFF | USART_CSR_ENDRX); 404 } else { 405 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY); 406 } 407 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK); 408errout:; 409 // XXX bad 410 return (err); 411} 412 413static int 414at91_usart_bus_transmit(struct uart_softc *sc) 415{ 416#ifndef SKYEYE_WORKAROUNDS 417 bus_addr_t addr; 418#endif 419 struct at91_usart_softc *atsc; 420 421 atsc = (struct at91_usart_softc *)sc; 422#ifndef SKYEYE_WORKAROUNDS 423 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf, 424 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) 425 return (EAGAIN); 426 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE); 427#endif 428 429 uart_lock(sc->sc_hwmtx); 430 sc->sc_txbusy = 1; 431#ifndef SKYEYE_WORKAROUNDS 432 /* 433 * Setup the PDC to transfer the data and interrupt us when it 434 * is done. We've already requested the interrupt. 435 */ 436 WR4(&sc->sc_bas, PDC_TPR, addr); 437 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz); 438 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN); 439 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX); 440 uart_unlock(sc->sc_hwmtx); 441#else 442 for (int i = 0; i < sc->sc_txdatasz; i++) 443 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]); 444 /* 445 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the 446 * transfer is done, so simulate it. 447 */ 448 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY); 449#endif 450 return (0); 451} 452static int 453at91_usart_bus_setsig(struct uart_softc *sc, int sig) 454{ 455 uint32_t new, old, cr; 456 struct uart_bas *bas; 457 458 do { 459 old = sc->sc_hwsig; 460 new = old; 461 if (sig & SER_DDTR) 462 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 463 if (sig & SER_DRTS) 464 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 465 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 466 bas = &sc->sc_bas; 467 uart_lock(sc->sc_hwmtx); 468 cr = 0; 469 if (new & SER_DTR) 470 cr |= USART_CR_DTREN; 471 else 472 cr |= USART_CR_DTRDIS; 473 if (new & SER_RTS) 474 cr |= USART_CR_RTSEN; 475 else 476 cr |= USART_CR_RTSDIS; 477 WR4(bas, USART_CR, cr); 478 uart_unlock(sc->sc_hwmtx); 479 return (0); 480} 481static int 482at91_usart_bus_receive(struct uart_softc *sc) 483{ 484 485 return (0); 486} 487static int 488at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits, 489 int stopbits, int parity) 490{ 491 492 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits, 493 parity)); 494} 495static int 496at91_usart_bus_ipend(struct uart_softc *sc) 497{ 498 int csr = RD4(&sc->sc_bas, USART_CSR); 499 int ipend = 0, i, len; 500 struct at91_usart_softc *atsc; 501 struct at91_usart_rx *p; 502 503 atsc = (struct at91_usart_softc *)sc; 504 if (csr & USART_CSR_ENDTX) { 505 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, 506 BUS_DMASYNC_POSTWRITE); 507 bus_dmamap_unload(atsc->dmatag, atsc->tx_map); 508 } 509 uart_lock(sc->sc_hwmtx); 510 if (csr & USART_CSR_TXRDY) { 511 if (sc->sc_txbusy) 512 ipend |= SER_INT_TXIDLE; 513 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY); 514 } 515 if (csr & USART_CSR_ENDTX) { 516 if (sc->sc_txbusy) 517 ipend |= SER_INT_TXIDLE; 518 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX); 519 } 520 521 /* 522 * Due to the contraints of the DMA engine present in the 523 * atmel chip, I can't just say I have a rx interrupt pending 524 * and do all the work elsewhere. I need to look at the CSR 525 * bits right now and do things based on them to avoid races. 526 */ 527 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) { 528 // Have a buffer overflow. Copy all data from both 529 // ping and pong. Insert overflow character. Reset 530 // ping and pong and re-enable the PDC to receive 531 // characters again. 532 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 533 BUS_DMASYNC_POSTREAD); 534 bus_dmamap_sync(atsc->dmatag, atsc->pong->map, 535 BUS_DMASYNC_POSTREAD); 536 for (i = 0; i < sc->sc_rxfifosz; i++) 537 uart_rx_put(sc, atsc->ping->buffer[i]); 538 for (i = 0; i < sc->sc_rxfifosz; i++) 539 uart_rx_put(sc, atsc->pong->buffer[i]); 540 uart_rx_put(sc, UART_STAT_OVERRUN); 541 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT); 542 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 543 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 544 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 545 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 546 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 547 ipend |= SER_INT_RXREADY; 548 } 549 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) { 550 // Shuffle data from 'ping' of ping pong buffer, but 551 // leave current 'pong' in place, as it has become the 552 // new 'ping'. We need to copy data and setup the old 553 // 'ping' as the new 'pong' when we're done. 554 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 555 BUS_DMASYNC_POSTREAD); 556 for (i = 0; i < sc->sc_rxfifosz; i++) 557 uart_rx_put(sc, atsc->ping->buffer[i]); 558 p = atsc->ping; 559 atsc->ping = atsc->pong; 560 atsc->pong = p; 561 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa); 562 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz); 563 ipend |= SER_INT_RXREADY; 564 } 565 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) { 566 // We have one partial buffer. We need to stop the 567 // PDC, get the number of characters left and from 568 // that compute number of valid characters. We then 569 // need to reset ping and pong and reenable the PDC. 570 // Not sure if there's a race here at fast baud rates 571 // we need to worry about. 572 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS); 573 bus_dmamap_sync(atsc->dmatag, atsc->ping->map, 574 BUS_DMASYNC_POSTREAD); 575 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); 576 for (i = 0; i < len; i++) 577 uart_rx_put(sc, atsc->ping->buffer[i]); 578 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa); 579 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz); 580 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO); 581 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN); 582 ipend |= SER_INT_RXREADY; 583 } 584 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) { 585 // We have another charater in a device that doesn't support 586 // timeouts, so we do it one character at a time. 587 uart_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); 588 ipend |= SER_INT_RXREADY; 589 } 590 591 if (csr & USART_CSR_RXBRK) { 592 unsigned int cr = USART_CR_RSTSTA; 593 594 ipend |= SER_INT_BREAK; 595 WR4(&sc->sc_bas, USART_CR, cr); 596 } 597 uart_unlock(sc->sc_hwmtx); 598 return (ipend); 599} 600static int 601at91_usart_bus_flush(struct uart_softc *sc, int what) 602{ 603 return (0); 604} 605 606static int 607at91_usart_bus_getsig(struct uart_softc *sc) 608{ 609 uint32_t new, sig; 610 uint8_t csr; 611 612 uart_lock(sc->sc_hwmtx); 613 csr = RD4(&sc->sc_bas, USART_CSR); 614 sig = 0; 615 if (csr & USART_CSR_CTS) 616 sig |= SER_CTS; 617 if (csr & USART_CSR_DCD) 618 sig |= SER_DCD; 619 if (csr & USART_CSR_DSR) 620 sig |= SER_DSR; 621 if (csr & USART_CSR_RI) 622 sig |= SER_RI; 623 new = sig & ~SER_MASK_DELTA; 624 sc->sc_hwsig = new; 625 uart_unlock(sc->sc_hwmtx); 626 return (sig); 627} 628 629static int 630at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 631{ 632 switch (request) { 633 case UART_IOCTL_BREAK: 634 case UART_IOCTL_IFLOW: 635 case UART_IOCTL_OFLOW: 636 break; 637 case UART_IOCTL_BAUD: 638 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data)); 639 return (0); 640 } 641 return (EINVAL); 642} 643struct uart_class at91_usart_class = { 644 "at91_usart class", 645 at91_usart_methods, 646 sizeof(struct at91_usart_softc), 647 .uc_range = 8, 648 .uc_rclk = DEFAULT_RCLK 649}; 650