at91_twireg.h revision 234291
113357Sarapte/*- 213357Sarapte * Copyright (c) 2006 M. Warner Losh. All rights reserved. 313357Sarapte * 413357Sarapte * Redistribution and use in source and binary forms, with or without 513357Sarapte * modification, are permitted provided that the following conditions 613357Sarapte * are met: 713357Sarapte * 1. Redistributions of source code must retain the above copyright 813357Sarapte * notice, this list of conditions and the following disclaimer. 913357Sarapte * 2. Redistributions in binary form must reproduce the above copyright 1013357Sarapte * notice, this list of conditions and the following disclaimer in the 1113357Sarapte * documentation and/or other materials provided with the distribution. 1213357Sarapte * 1313357Sarapte * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1413357Sarapte * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1513357Sarapte * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1613357Sarapte * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 1713357Sarapte * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1813357Sarapte * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 1913357Sarapte * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2013357Sarapte * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2113357Sarapte * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2213357Sarapte * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2313357Sarapte * SUCH DAMAGE. 2413357Sarapte */ 2513357Sarapte 2614851Sgoetz/* $FreeBSD: head/sys/arm/at91/at91_twireg.h 234291 2012-04-14 17:09:38Z marius $ */ 2713357Sarapte 2813357Sarapte#ifndef ARM_AT91_AT91_TWIREG_H 2913357Sarapte#define ARM_AT91_AT91_TWIREG_H 3013357Sarapte 3113357Sarapte#define TWI_CR 0x00 /* TWI Control Register */ 3213357Sarapte#define TWI_MMR 0x04 /* TWI Master Mode Register */ 3313357Sarapte#define TWI_SMR 0x08 /* TWI Master Mode Register */ 3413357Sarapte#define TWI_IADR 0x0c /* TWI Internal Address Register */ 3513357Sarapte#define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */ 3613357Sarapte /* 0x14 reserved */ 3713357Sarapte /* 0x18 reserved */ 3813357Sarapte /* 0x1c reserved */ 3913357Sarapte#define TWI_SR 0x20 /* TWI Status Register */ 4013357Sarapte#define TWI_IER 0x24 /* TWI Interrupt Enable Register */ 4113357Sarapte#define TWI_IDR 0x28 /* TWI Interrupt Disable Register */ 4213357Sarapte#define TWI_IMR 0x2c /* TWI Interrupt Mask Register */ 4313357Sarapte#define TWI_RHR 0x30 /* TWI Receiver Holding Register */ 4413357Sarapte#define TWI_THR 0x34 /* TWI Transmit Holding Register */ 4513357Sarapte 4613357Sarapte/* TWI_CR */ 4713357Sarapte#define TWI_CR_START (1U << 0) /* Send a start */ 4813357Sarapte#define TWI_CR_STOP (1U << 1) /* Send a stop */ 4913357Sarapte#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */ 5013357Sarapte#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */ 5113357Sarapte#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */ 5213357Sarapte#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */ 5313357Sarapte#define TWI_CR_SWRST (1U << 7) /* Software Reset */ 5413357Sarapte 5513357Sarapte/* TWI_MMR */ 5613357Sarapte/* TWI_SMR */ 5713357Sarapte#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */ 5813357Sarapte#define TWI_MMR_MWRITE 0U /* Master Read Direction */ 5913357Sarapte#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */ 6013357Sarapte#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */ 6113357Sarapte 6213357Sarapte/* TWI_CWGR */ 6313357Sarapte#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */ 6413357Sarapte#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */ 6513357Sarapte#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */ 6613357Sarapte#define TWI_CWGR_DIV(rate) \ 6713357Sarapte (at91_is_sam9() || at91_is_sam9xe() ? \ 6813357Sarapte ((at91_master_clock / (4 * (rate))) - 3) : \ 6913357Sarapte ((at91_master_clock / (4 * (rate))) - 2)) 7013357Sarapte 7113357Sarapte/* TWI_SR */ 7213357Sarapte/* TWI_IER */ 7313357Sarapte/* TWI_IDR */ 7413357Sarapte/* TWI_IMR */ 7513357Sarapte#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */ 7613357Sarapte#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */ 7713357Sarapte#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */ 7813357Sarapte#define TWI_SR_SVREAD (1U << 3) /* Slave Read */ 7913357Sarapte#define TWI_SR_SVACC (1U << 4) /* Slave Access */ 8013357Sarapte#define TWI_SR_GCACC (1U << 5) /* General Call Access */ 8113357Sarapte#define TWI_SR_OVRE (1U << 6) /* Overrun error */ 8213357Sarapte#define TWI_SR_UNRE (1U << 7) /* Underrun Error */ 8313357Sarapte#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */ 8413357Sarapte#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */ 8513357Sarapte 8613357Sarapte#endif /* ARM_AT91_AT91_TWIREG_H */ 8713357Sarapte