at91_rtcreg.h revision 157086
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* $FreeBSD: head/sys/arm/at91/at91_rtcreg.h 157086 2006-03-24 07:35:30Z imp $ */ 26 27#ifndef ARM_AT91_AT91_RTCREG_H 28#define ARM_AT91_AT91_RTCREG_H 29 30/* Registers */ 31#define RTC_CR 0x00 /* RTC Control Register */ 32#define RTC_MR 0x04 /* RTC Mode Register */ 33#define RTC_TIMR 0x08 /* RTC Time Register */ 34#define RTC_CALR 0x0c /* RTC Calendar Register */ 35#define RTC_TIMALR 0x10 /* RTC Time Alarm Register */ 36#define RTC_CALALR 0x14 /* RTC Calendar Alarm Register */ 37#define RTC_SR 0x18 /* RTC Status Register */ 38#define RTC_SCCR 0x1c /* RTC Status Command Clear Register */ 39#define RTC_IER 0x20 /* RTC Interrupt Enable Register */ 40#define RTC_IDR 0x24 /* RTC Interrupt Disable Register */ 41#define RTC_IMR 0x28 /* RTC Interrupt Mask Register */ 42#define RTC_VER 0x2c /* RTC Valid Entry Register */ 43 44/* TIMR */ 45#define RTC_TIMR_SEC_M 0x7fUL 46#define RTC_TIMR_SEC_S 0 47#define RTC_TIMR_SEC(x) FROMBCD(((x) & RTC_TIMR_SEC_M) >> RTC_TIMR_SEC_S) 48#define RTC_TIMR_MIN_M 0x7f00UL 49#define RTC_TIMR_MIN_S 8 50#define RTC_TIMR_MIN(x) FROMBCD(((x) & RTC_TIMR_MIN_M) >> RTC_TIMR_MIN_S) 51#define RTC_TIMR_HR_M 0x3f0000UL 52#define RTC_TIMR_HR_S 16 53#define RTC_TIMR_HR(x) FROMBCD(((x) & RTC_TIMR_HR_M) >> RTC_TIMR_HR_S) 54#define RTC_TIMR_MK(hr, min, sec) \ 55 ((TOBCD(hr) << RTC_TIMR_HR_S) | \ 56 (TOBCD(min) << RTC_TIMR_MIN_S) | \ 57 (TOBCD(sec) << RTC_TIMR_SEC_S)) 58#define RTC_TIMR_PM (1UL << 22) 59 60/* CALR */ 61#define RTC_CALR_CEN_M 0x0000007fUL 62#define RTC_CALR_CEN_S 0 63#define RTC_CALR_CEN(x) FROMBCD(((x) & RTC_CALR_CEN_M) >> RTC_CALR_CEN_S) 64#define RTC_CALR_YEAR_M 0x0000ff00UL 65#define RTC_CALR_YEAR_S 8 66#define RTC_CALR_YEAR(x) FROMBCD(((x) & RTC_CALR_YEAR_M) >> RTC_CALR_YEAR_S) 67#define RTC_CALR_MON_M 0x001f0000UL 68#define RTC_CALR_MON_S 16 69#define RTC_CALR_MON(x) FROMBCD(((x) & RTC_CALR_MON_M) >> RTC_CALR_MON_S) 70#define RTC_CALR_DOW_M 0x00d0000UL 71#define RTC_CALR_DOW_S 21 72#define RTC_CALR_DOW(x) FROMBCD(((x) & RTC_CALR_DOW_M) >> RTC_CALR_DOW_S) 73#define RTC_CALR_DAY_M 0x3f00000UL 74#define RTC_CALR_DAY_S 24 75#define RTC_CALR_DAY(x) FROMBCD(((x) & RTC_CALR_DAY_M) >> RTC_CALR_DAY_S) 76#define RTC_CALR_MK(yr, mon, day, dow) \ 77 ((TOBCD((yr) / 100 + 19) << RTC_CALR_CENTURY_S) | \ 78 (TOBCD((yr) % 100) << RTC_CALR_YEAR_S) | \ 79 (TOBCD(mon) << RTC_CALR_MON_S) | \ 80 (TOBCD(dow) << RTC_CALR_DOW_S) | \ 81 (TOBCD(day) << RTC_CALR_DAY_S)) 82 83#endif /* ARM_AT91_AT91_RTCREG_H */ 84