at91_pdcreg.h revision 158432
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* $FreeBSD: head/sys/arm/at91/at91_pdcreg.h 158432 2006-05-11 14:30:28Z cognet $ */ 26 27#ifndef ARM_AT91_AT91_PDCREG_H 28#define ARM_AT91_AT91_PDCREG_H 29 30#define PDC_RPR 0x100 /* PDC Receive Pointer Register */ 31#define PDC_RCR 0x104 /* PDC Receive Counter Register */ 32#define PDC_TPR 0x108 /* PDC Transmit Pointer Register */ 33#define PDC_TCR 0x10c /* PDC Transmit Counter Register */ 34#define PDC_RNPR 0x110 /* PDC Receive Next Pointer Register */ 35#define PDC_RNCR 0x114 /* PDC Receive Next Counter Register */ 36#define PDC_TNPR 0x118 /* PDC Transmit Next Pointer Reg */ 37#define PDC_TNCR 0x11c /* PDC Transmit Next Counter Reg */ 38#define PDC_PTCR 0x120 /* PDC Transfer Control Register */ 39#define PDC_PTSR 0x124 /* PDC Transfer Status Register */ 40 41/* PTCR/PTSR */ 42#define PDC_PTCR_RXTEN (1UL << 0) /* RXTEN: Receiver Transfer Enable */ 43#define PDC_PTCR_RXTDIS (1UL << 1) /* RXTDIS: Receiver Transfer Disable */ 44#define PDC_PTCR_TXTEN (1UL << 8) /* TXTEN: Transmitter Transfer En */ 45#define PDC_PTCR_TXTDIS (1UL << 9) /* TXTDIS: Transmitter Transmit Dis */ 46 47#endif /* ARM_AT91_AT91_PDCREG_H */ 48