mthca-abi.h revision 256281 
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3 * Copyright (c) 2006 Cisco Systems.  All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses.  You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 *     Redistribution and use in source and binary forms, with or
12 *     without modification, are permitted provided that the following
13 *     conditions are met:
14 *
15 *      - Redistributions of source code must retain the above
16 *        copyright notice, this list of conditions and the following
17 *        disclaimer.
18 *
19 *      - Redistributions in binary form must reproduce the above
20 *        copyright notice, this list of conditions and the following
21 *        disclaimer in the documentation and/or other materials
22 *        provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef MTHCA_ABI_H
35#define MTHCA_ABI_H
36
37#include <infiniband/kern-abi.h>
38
39#define MTHCA_UVERBS_ABI_VERSION	1
40
41struct mthca_alloc_ucontext_resp {
42	struct ibv_get_context_resp	ibv_resp;
43	__u32				qp_tab_size;
44	__u32				uarc_size;
45};
46
47struct mthca_alloc_pd_resp {
48	struct ibv_alloc_pd_resp	ibv_resp;
49	__u32				pdn;
50	__u32				reserved;
51};
52
53struct mthca_reg_mr {
54	struct ibv_reg_mr		ibv_cmd;
55/*
56 * Mark the memory region with a DMA attribute that causes
57 * in-flight DMA to be flushed when the region is written to:
58 */
59#define MTHCA_MR_DMASYNC	0x1
60	__u32				mr_attrs;
61	__u32				reserved;
62};
63
64struct mthca_create_cq {
65	struct ibv_create_cq		ibv_cmd;
66	__u32				lkey;
67	__u32				pdn;
68	__u64				arm_db_page;
69	__u64				set_db_page;
70	__u32				arm_db_index;
71	__u32				set_db_index;
72};
73
74struct mthca_create_cq_resp {
75	struct ibv_create_cq_resp	ibv_resp;
76	__u32				cqn;
77	__u32				reserved;
78};
79
80struct mthca_resize_cq {
81	struct ibv_resize_cq		ibv_cmd;
82	__u32				lkey;
83	__u32				reserved;
84};
85
86struct mthca_create_srq {
87	struct ibv_create_srq		ibv_cmd;
88	__u32				lkey;
89	__u32				db_index;
90	__u64				db_page;
91};
92
93struct mthca_create_srq_resp {
94	struct ibv_create_srq_resp	ibv_resp;
95	__u32				srqn;
96	__u32				reserved;
97};
98
99struct mthca_create_qp {
100	struct ibv_create_qp		ibv_cmd;
101	__u32				lkey;
102	__u32				reserved;
103	__u64				sq_db_page;
104	__u64				rq_db_page;
105	__u32				sq_db_index;
106	__u32				rq_db_index;
107};
108
109#endif /* MTHCA_ABI_H */
110