FastISelEmitter.cpp revision 208599
1//===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits code for use by the "fast" instruction 11// selection algorithm. See the comments at the top of 12// lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13// 14// This file scans through the target's tablegen instruction-info files 15// and extracts instructions with obvious-looking patterns, and it emits 16// code to look up these instructions by type and operator. 17// 18//===----------------------------------------------------------------------===// 19 20#include "FastISelEmitter.h" 21#include "Record.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/ADT/VectorExtras.h" 24using namespace llvm; 25 26namespace { 27 28/// InstructionMemo - This class holds additional information about an 29/// instruction needed to emit code for it. 30/// 31struct InstructionMemo { 32 std::string Name; 33 const CodeGenRegisterClass *RC; 34 std::string SubRegNo; 35 std::vector<std::string>* PhysRegs; 36}; 37 38/// OperandsSignature - This class holds a description of a list of operand 39/// types. It has utility methods for emitting text based on the operands. 40/// 41struct OperandsSignature { 42 std::vector<std::string> Operands; 43 44 bool operator<(const OperandsSignature &O) const { 45 return Operands < O.Operands; 46 } 47 48 bool empty() const { return Operands.empty(); } 49 50 /// initialize - Examine the given pattern and initialize the contents 51 /// of the Operands array accordingly. Return true if all the operands 52 /// are supported, false otherwise. 53 /// 54 bool initialize(TreePatternNode *InstPatNode, 55 const CodeGenTarget &Target, 56 MVT::SimpleValueType VT) { 57 if (!InstPatNode->isLeaf() && 58 InstPatNode->getOperator()->getName() == "imm") { 59 Operands.push_back("i"); 60 return true; 61 } 62 if (!InstPatNode->isLeaf() && 63 InstPatNode->getOperator()->getName() == "fpimm") { 64 Operands.push_back("f"); 65 return true; 66 } 67 68 const CodeGenRegisterClass *DstRC = 0; 69 70 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 71 TreePatternNode *Op = InstPatNode->getChild(i); 72 // For now, filter out any operand with a predicate. 73 // For now, filter out any operand with multiple values. 74 if (!Op->getPredicateFns().empty() || 75 Op->getNumTypes() != 1) 76 return false; 77 78 assert(Op->hasTypeSet(0) && "Type infererence not done?"); 79 // For now, all the operands must have the same type. 80 if (Op->getType(0) != VT) 81 return false; 82 83 if (!Op->isLeaf()) { 84 if (Op->getOperator()->getName() == "imm") { 85 Operands.push_back("i"); 86 continue; 87 } 88 if (Op->getOperator()->getName() == "fpimm") { 89 Operands.push_back("f"); 90 continue; 91 } 92 // For now, ignore other non-leaf nodes. 93 return false; 94 } 95 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 96 if (!OpDI) 97 return false; 98 Record *OpLeafRec = OpDI->getDef(); 99 // For now, the only other thing we accept is register operands. 100 101 const CodeGenRegisterClass *RC = 0; 102 if (OpLeafRec->isSubClassOf("RegisterClass")) 103 RC = &Target.getRegisterClass(OpLeafRec); 104 else if (OpLeafRec->isSubClassOf("Register")) 105 RC = Target.getRegisterClassForRegister(OpLeafRec); 106 else 107 return false; 108 // For now, require the register operands' register classes to all 109 // be the same. 110 if (!RC) 111 return false; 112 // For now, all the operands must have the same register class. 113 if (DstRC) { 114 if (DstRC != RC) 115 return false; 116 } else 117 DstRC = RC; 118 Operands.push_back("r"); 119 } 120 return true; 121 } 122 123 void PrintParameters(raw_ostream &OS) const { 124 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 125 if (Operands[i] == "r") { 126 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; 127 } else if (Operands[i] == "i") { 128 OS << "uint64_t imm" << i; 129 } else if (Operands[i] == "f") { 130 OS << "ConstantFP *f" << i; 131 } else { 132 assert("Unknown operand kind!"); 133 abort(); 134 } 135 if (i + 1 != e) 136 OS << ", "; 137 } 138 } 139 140 void PrintArguments(raw_ostream &OS, 141 const std::vector<std::string>& PR) const { 142 assert(PR.size() == Operands.size()); 143 bool PrintedArg = false; 144 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 145 if (PR[i] != "") 146 // Implicit physical register operand. 147 continue; 148 149 if (PrintedArg) 150 OS << ", "; 151 if (Operands[i] == "r") { 152 OS << "Op" << i << ", Op" << i << "IsKill"; 153 PrintedArg = true; 154 } else if (Operands[i] == "i") { 155 OS << "imm" << i; 156 PrintedArg = true; 157 } else if (Operands[i] == "f") { 158 OS << "f" << i; 159 PrintedArg = true; 160 } else { 161 assert("Unknown operand kind!"); 162 abort(); 163 } 164 } 165 } 166 167 void PrintArguments(raw_ostream &OS) const { 168 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 169 if (Operands[i] == "r") { 170 OS << "Op" << i << ", Op" << i << "IsKill"; 171 } else if (Operands[i] == "i") { 172 OS << "imm" << i; 173 } else if (Operands[i] == "f") { 174 OS << "f" << i; 175 } else { 176 assert("Unknown operand kind!"); 177 abort(); 178 } 179 if (i + 1 != e) 180 OS << ", "; 181 } 182 } 183 184 185 void PrintManglingSuffix(raw_ostream &OS, 186 const std::vector<std::string>& PR) const { 187 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 188 if (PR[i] != "") 189 // Implicit physical register operand. e.g. Instruction::Mul expect to 190 // select to a binary op. On x86, mul may take a single operand with 191 // the other operand being implicit. We must emit something that looks 192 // like a binary instruction except for the very inner FastEmitInst_* 193 // call. 194 continue; 195 OS << Operands[i]; 196 } 197 } 198 199 void PrintManglingSuffix(raw_ostream &OS) const { 200 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 201 OS << Operands[i]; 202 } 203 } 204}; 205 206class FastISelMap { 207 typedef std::map<std::string, InstructionMemo> PredMap; 208 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 209 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 210 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 211 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap; 212 213 OperandsOpcodeTypeRetPredMap SimplePatterns; 214 215 std::string InstNS; 216 217public: 218 explicit FastISelMap(std::string InstNS); 219 220 void CollectPatterns(CodeGenDAGPatterns &CGP); 221 void PrintFunctionDefinitions(raw_ostream &OS); 222}; 223 224} 225 226static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 227 return CGP.getSDNodeInfo(Op).getEnumName(); 228} 229 230static std::string getLegalCName(std::string OpName) { 231 std::string::size_type pos = OpName.find("::"); 232 if (pos != std::string::npos) 233 OpName.replace(pos, 2, "_"); 234 return OpName; 235} 236 237FastISelMap::FastISelMap(std::string instns) 238 : InstNS(instns) { 239} 240 241void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { 242 const CodeGenTarget &Target = CGP.getTargetInfo(); 243 244 // Determine the target's namespace name. 245 InstNS = Target.getInstNamespace() + "::"; 246 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 247 248 // Scan through all the patterns and record the simple ones. 249 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 250 E = CGP.ptm_end(); I != E; ++I) { 251 const PatternToMatch &Pattern = *I; 252 253 // For now, just look at Instructions, so that we don't have to worry 254 // about emitting multiple instructions for a pattern. 255 TreePatternNode *Dst = Pattern.getDstPattern(); 256 if (Dst->isLeaf()) continue; 257 Record *Op = Dst->getOperator(); 258 if (!Op->isSubClassOf("Instruction")) 259 continue; 260 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 261 if (II.OperandList.empty()) 262 continue; 263 264 // For now, ignore multi-instruction patterns. 265 bool MultiInsts = false; 266 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 267 TreePatternNode *ChildOp = Dst->getChild(i); 268 if (ChildOp->isLeaf()) 269 continue; 270 if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 271 MultiInsts = true; 272 break; 273 } 274 } 275 if (MultiInsts) 276 continue; 277 278 // For now, ignore instructions where the first operand is not an 279 // output register. 280 const CodeGenRegisterClass *DstRC = 0; 281 std::string SubRegNo; 282 if (Op->getName() != "EXTRACT_SUBREG") { 283 Record *Op0Rec = II.OperandList[0].Rec; 284 if (!Op0Rec->isSubClassOf("RegisterClass")) 285 continue; 286 DstRC = &Target.getRegisterClass(Op0Rec); 287 if (!DstRC) 288 continue; 289 } else { 290 DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue()); 291 if (SR) 292 SubRegNo = getQualifiedName(SR->getDef()); 293 else 294 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); 295 } 296 297 // Inspect the pattern. 298 TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 299 if (!InstPatNode) continue; 300 if (InstPatNode->isLeaf()) continue; 301 302 // Ignore multiple result nodes for now. 303 if (InstPatNode->getNumTypes() > 1) continue; 304 305 Record *InstPatOp = InstPatNode->getOperator(); 306 std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 307 MVT::SimpleValueType RetVT = MVT::isVoid; 308 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); 309 MVT::SimpleValueType VT = RetVT; 310 if (InstPatNode->getNumChildren()) { 311 assert(InstPatNode->getChild(0)->getNumTypes() == 1); 312 VT = InstPatNode->getChild(0)->getType(0); 313 } 314 315 // For now, filter out instructions which just set a register to 316 // an Operand or an immediate, like MOV32ri. 317 if (InstPatOp->isSubClassOf("Operand")) 318 continue; 319 320 // For now, filter out any instructions with predicates. 321 if (!InstPatNode->getPredicateFns().empty()) 322 continue; 323 324 // Check all the operands. 325 OperandsSignature Operands; 326 if (!Operands.initialize(InstPatNode, Target, VT)) 327 continue; 328 329 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 330 if (!InstPatNode->isLeaf() && 331 (InstPatNode->getOperator()->getName() == "imm" || 332 InstPatNode->getOperator()->getName() == "fpimmm")) 333 PhysRegInputs->push_back(""); 334 else if (!InstPatNode->isLeaf()) { 335 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 336 TreePatternNode *Op = InstPatNode->getChild(i); 337 if (!Op->isLeaf()) { 338 PhysRegInputs->push_back(""); 339 continue; 340 } 341 342 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 343 Record *OpLeafRec = OpDI->getDef(); 344 std::string PhysReg; 345 if (OpLeafRec->isSubClassOf("Register")) { 346 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 347 "Namespace")->getValue())->getValue(); 348 PhysReg += "::"; 349 350 std::vector<CodeGenRegister> Regs = Target.getRegisters(); 351 for (unsigned i = 0; i < Regs.size(); ++i) { 352 if (Regs[i].TheDef == OpLeafRec) { 353 PhysReg += Regs[i].getName(); 354 break; 355 } 356 } 357 } 358 359 PhysRegInputs->push_back(PhysReg); 360 } 361 } else 362 PhysRegInputs->push_back(""); 363 364 // Get the predicate that guards this pattern. 365 std::string PredicateCheck = Pattern.getPredicateCheck(); 366 367 // Ok, we found a pattern that we can handle. Remember it. 368 InstructionMemo Memo = { 369 Pattern.getDstPattern()->getOperator()->getName(), 370 DstRC, 371 SubRegNo, 372 PhysRegInputs 373 }; 374 assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) && 375 "Duplicate pattern!"); 376 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 377 } 378} 379 380void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { 381 // Now emit code for all the patterns that we collected. 382 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 383 OE = SimplePatterns.end(); OI != OE; ++OI) { 384 const OperandsSignature &Operands = OI->first; 385 const OpcodeTypeRetPredMap &OTM = OI->second; 386 387 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 388 I != E; ++I) { 389 const std::string &Opcode = I->first; 390 const TypeRetPredMap &TM = I->second; 391 392 OS << "// FastEmit functions for " << Opcode << ".\n"; 393 OS << "\n"; 394 395 // Emit one function for each opcode,type pair. 396 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 397 TI != TE; ++TI) { 398 MVT::SimpleValueType VT = TI->first; 399 const RetPredMap &RM = TI->second; 400 if (RM.size() != 1) { 401 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 402 RI != RE; ++RI) { 403 MVT::SimpleValueType RetVT = RI->first; 404 const PredMap &PM = RI->second; 405 bool HasPred = false; 406 407 OS << "unsigned FastEmit_" 408 << getLegalCName(Opcode) 409 << "_" << getLegalCName(getName(VT)) 410 << "_" << getLegalCName(getName(RetVT)) << "_"; 411 Operands.PrintManglingSuffix(OS); 412 OS << "("; 413 Operands.PrintParameters(OS); 414 OS << ") {\n"; 415 416 // Emit code for each possible instruction. There may be 417 // multiple if there are subtarget concerns. 418 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 419 PI != PE; ++PI) { 420 std::string PredicateCheck = PI->first; 421 const InstructionMemo &Memo = PI->second; 422 423 if (PredicateCheck.empty()) { 424 assert(!HasPred && 425 "Multiple instructions match, at least one has " 426 "a predicate and at least one doesn't!"); 427 } else { 428 OS << " if (" + PredicateCheck + ") {\n"; 429 OS << " "; 430 HasPred = true; 431 } 432 433 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 434 if ((*Memo.PhysRegs)[i] != "") 435 OS << " TII.copyRegToReg(*MBB, MBB->end(), " 436 << (*Memo.PhysRegs)[i] << ", Op" << i << ", " 437 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass(" 438 << (*Memo.PhysRegs)[i] << "), " 439 << "MRI.getRegClass(Op" << i << "), DL);\n"; 440 } 441 442 OS << " return FastEmitInst_"; 443 if (Memo.SubRegNo.empty()) { 444 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); 445 OS << "(" << InstNS << Memo.Name << ", "; 446 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 447 if (!Operands.empty()) 448 OS << ", "; 449 Operands.PrintArguments(OS, *Memo.PhysRegs); 450 OS << ");\n"; 451 } else { 452 OS << "extractsubreg(" << getName(RetVT); 453 OS << ", Op0, Op0IsKill, "; 454 OS << Memo.SubRegNo; 455 OS << ");\n"; 456 } 457 458 if (HasPred) 459 OS << " }\n"; 460 461 } 462 // Return 0 if none of the predicates were satisfied. 463 if (HasPred) 464 OS << " return 0;\n"; 465 OS << "}\n"; 466 OS << "\n"; 467 } 468 469 // Emit one function for the type that demultiplexes on return type. 470 OS << "unsigned FastEmit_" 471 << getLegalCName(Opcode) << "_" 472 << getLegalCName(getName(VT)) << "_"; 473 Operands.PrintManglingSuffix(OS); 474 OS << "(MVT RetVT"; 475 if (!Operands.empty()) 476 OS << ", "; 477 Operands.PrintParameters(OS); 478 OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 479 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 480 RI != RE; ++RI) { 481 MVT::SimpleValueType RetVT = RI->first; 482 OS << " case " << getName(RetVT) << ": return FastEmit_" 483 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 484 << "_" << getLegalCName(getName(RetVT)) << "_"; 485 Operands.PrintManglingSuffix(OS); 486 OS << "("; 487 Operands.PrintArguments(OS); 488 OS << ");\n"; 489 } 490 OS << " default: return 0;\n}\n}\n\n"; 491 492 } else { 493 // Non-variadic return type. 494 OS << "unsigned FastEmit_" 495 << getLegalCName(Opcode) << "_" 496 << getLegalCName(getName(VT)) << "_"; 497 Operands.PrintManglingSuffix(OS); 498 OS << "(MVT RetVT"; 499 if (!Operands.empty()) 500 OS << ", "; 501 Operands.PrintParameters(OS); 502 OS << ") {\n"; 503 504 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) 505 << ")\n return 0;\n"; 506 507 const PredMap &PM = RM.begin()->second; 508 bool HasPred = false; 509 510 // Emit code for each possible instruction. There may be 511 // multiple if there are subtarget concerns. 512 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 513 ++PI) { 514 std::string PredicateCheck = PI->first; 515 const InstructionMemo &Memo = PI->second; 516 517 if (PredicateCheck.empty()) { 518 assert(!HasPred && 519 "Multiple instructions match, at least one has " 520 "a predicate and at least one doesn't!"); 521 } else { 522 OS << " if (" + PredicateCheck + ") {\n"; 523 OS << " "; 524 HasPred = true; 525 } 526 527 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 528 if ((*Memo.PhysRegs)[i] != "") 529 OS << " TII.copyRegToReg(*MBB, MBB->end(), " 530 << (*Memo.PhysRegs)[i] << ", Op" << i << ", " 531 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass(" 532 << (*Memo.PhysRegs)[i] << "), " 533 << "MRI.getRegClass(Op" << i << "), DL);\n"; 534 } 535 536 OS << " return FastEmitInst_"; 537 538 if (Memo.SubRegNo.empty()) { 539 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); 540 OS << "(" << InstNS << Memo.Name << ", "; 541 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 542 if (!Operands.empty()) 543 OS << ", "; 544 Operands.PrintArguments(OS, *Memo.PhysRegs); 545 OS << ");\n"; 546 } else { 547 OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; 548 OS << Memo.SubRegNo; 549 OS << ");\n"; 550 } 551 552 if (HasPred) 553 OS << " }\n"; 554 } 555 556 // Return 0 if none of the predicates were satisfied. 557 if (HasPred) 558 OS << " return 0;\n"; 559 OS << "}\n"; 560 OS << "\n"; 561 } 562 } 563 564 // Emit one function for the opcode that demultiplexes based on the type. 565 OS << "unsigned FastEmit_" 566 << getLegalCName(Opcode) << "_"; 567 Operands.PrintManglingSuffix(OS); 568 OS << "(MVT VT, MVT RetVT"; 569 if (!Operands.empty()) 570 OS << ", "; 571 Operands.PrintParameters(OS); 572 OS << ") {\n"; 573 OS << " switch (VT.SimpleTy) {\n"; 574 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 575 TI != TE; ++TI) { 576 MVT::SimpleValueType VT = TI->first; 577 std::string TypeName = getName(VT); 578 OS << " case " << TypeName << ": return FastEmit_" 579 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 580 Operands.PrintManglingSuffix(OS); 581 OS << "(RetVT"; 582 if (!Operands.empty()) 583 OS << ", "; 584 Operands.PrintArguments(OS); 585 OS << ");\n"; 586 } 587 OS << " default: return 0;\n"; 588 OS << " }\n"; 589 OS << "}\n"; 590 OS << "\n"; 591 } 592 593 OS << "// Top-level FastEmit function.\n"; 594 OS << "\n"; 595 596 // Emit one function for the operand signature that demultiplexes based 597 // on opcode and type. 598 OS << "unsigned FastEmit_"; 599 Operands.PrintManglingSuffix(OS); 600 OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 601 if (!Operands.empty()) 602 OS << ", "; 603 Operands.PrintParameters(OS); 604 OS << ") {\n"; 605 OS << " switch (Opcode) {\n"; 606 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 607 I != E; ++I) { 608 const std::string &Opcode = I->first; 609 610 OS << " case " << Opcode << ": return FastEmit_" 611 << getLegalCName(Opcode) << "_"; 612 Operands.PrintManglingSuffix(OS); 613 OS << "(VT, RetVT"; 614 if (!Operands.empty()) 615 OS << ", "; 616 Operands.PrintArguments(OS); 617 OS << ");\n"; 618 } 619 OS << " default: return 0;\n"; 620 OS << " }\n"; 621 OS << "}\n"; 622 OS << "\n"; 623 } 624} 625 626void FastISelEmitter::run(raw_ostream &OS) { 627 const CodeGenTarget &Target = CGP.getTargetInfo(); 628 629 // Determine the target's namespace name. 630 std::string InstNS = Target.getInstNamespace() + "::"; 631 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 632 633 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + 634 Target.getName() + " target", OS); 635 636 FastISelMap F(InstNS); 637 F.CollectPatterns(CGP); 638 F.PrintFunctionDefinitions(OS); 639} 640 641FastISelEmitter::FastISelEmitter(RecordKeeper &R) 642 : Records(R), 643 CGP(R) { 644} 645 646