TargetInfo.cpp revision 256281
1296341Sdelphij//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===// 296593Smarkm// 396593Smarkm// The LLVM Compiler Infrastructure 4142429Snectar// 596593Smarkm// This file is distributed under the University of Illinois Open Source 696593Smarkm// License. See LICENSE.TXT for details. 796593Smarkm// 896593Smarkm//===----------------------------------------------------------------------===// 996593Smarkm// 1096593Smarkm// These classes wrap the information about a call or function 1196593Smarkm// definition used to handle ABI compliancy. 1296593Smarkm// 1396593Smarkm//===----------------------------------------------------------------------===// 1496593Smarkm 1596593Smarkm#include "TargetInfo.h" 1696593Smarkm#include "ABIInfo.h" 1796593Smarkm#include "CGCXXABI.h" 1896593Smarkm#include "CodeGenFunction.h" 1996593Smarkm#include "clang/AST/RecordLayout.h" 20215698Ssimon#include "clang/Frontend/CodeGenOptions.h" 21215698Ssimon#include "llvm/ADT/Triple.h" 22215698Ssimon#include "llvm/IR/DataLayout.h" 23215698Ssimon#include "llvm/IR/Type.h" 24215698Ssimon#include "llvm/Support/raw_ostream.h" 2596593Smarkmusing namespace clang; 2696593Smarkmusing namespace CodeGen; 2796593Smarkm 2896593Smarkmstatic void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, 2996593Smarkm llvm::Value *Array, 3096593Smarkm llvm::Value *Value, 3196593Smarkm unsigned FirstIndex, 3296593Smarkm unsigned LastIndex) { 3396593Smarkm // Alternatively, we could emit this as a loop in the source. 3496593Smarkm for (unsigned I = FirstIndex; I <= LastIndex; ++I) { 3596593Smarkm llvm::Value *Cell = Builder.CreateConstInBoundsGEP1_32(Array, I); 3696593Smarkm Builder.CreateStore(Value, Cell); 3796593Smarkm } 3896593Smarkm} 3996593Smarkm 4096593Smarkmstatic bool isAggregateTypeForABI(QualType T) { 41279264Sdelphij return !CodeGenFunction::hasScalarEvaluationKind(T) || 42279264Sdelphij T->isMemberFunctionPointerType(); 4396593Smarkm} 4496593Smarkm 45215698SsimonABIInfo::~ABIInfo() {} 46215698Ssimon 47215698Ssimonstatic bool isRecordReturnIndirect(const RecordType *RT, CodeGen::CodeGenTypes &CGT) { 48215698Ssimon const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 49142429Snectar if (!RD) 50215698Ssimon return false; 51142429Snectar return CGT.CGM.getCXXABI().isReturnTypeIndirect(RD); 52142429Snectar} 53279264Sdelphij 54279264Sdelphij 55279264Sdelphijstatic bool isRecordReturnIndirect(QualType T, CodeGen::CodeGenTypes &CGT) { 5696593Smarkm const RecordType *RT = T->getAs<RecordType>(); 57279264Sdelphij if (!RT) 58279264Sdelphij return false; 59279264Sdelphij return isRecordReturnIndirect(RT, CGT); 60279264Sdelphij} 61279264Sdelphij 62279264Sdelphijstatic CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, 63215698Ssimon CodeGen::CodeGenTypes &CGT) { 64279264Sdelphij const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 65279264Sdelphij if (!RD) 66279264Sdelphij return CGCXXABI::RAA_Default; 67279264Sdelphij return CGT.CGM.getCXXABI().getRecordArgABI(RD); 68279264Sdelphij} 69215698Ssimon 70279264Sdelphijstatic CGCXXABI::RecordArgABI getRecordArgABI(QualType T, 7196593Smarkm CodeGen::CodeGenTypes &CGT) { 7296593Smarkm const RecordType *RT = T->getAs<RecordType>(); 7396593Smarkm if (!RT) 7496593Smarkm return CGCXXABI::RAA_Default; 7596593Smarkm return getRecordArgABI(RT, CGT); 7696593Smarkm} 7796593Smarkm 7896593SmarkmASTContext &ABIInfo::getContext() const { 7996593Smarkm return CGT.getContext(); 8096593Smarkm} 8196593Smarkm 8296593Smarkmllvm::LLVMContext &ABIInfo::getVMContext() const { 8396593Smarkm return CGT.getLLVMContext(); 8496593Smarkm} 8596593Smarkm 8696593Smarkmconst llvm::DataLayout &ABIInfo::getDataLayout() const { 8796593Smarkm return CGT.getDataLayout(); 8896593Smarkm} 8996593Smarkm 9096593Smarkmconst TargetInfo &ABIInfo::getTarget() const { 9196593Smarkm return CGT.getTarget(); 9296593Smarkm} 9396593Smarkm 9496593Smarkmvoid ABIArgInfo::dump() const { 9596593Smarkm raw_ostream &OS = llvm::errs(); 9696593Smarkm OS << "(ABIArgInfo Kind="; 9796593Smarkm switch (TheKind) { 9896593Smarkm case Direct: 9996593Smarkm OS << "Direct Type="; 10096593Smarkm if (llvm::Type *Ty = getCoerceToType()) 10196593Smarkm Ty->print(OS); 10296593Smarkm else 10396593Smarkm OS << "null"; 10496593Smarkm break; 10596593Smarkm case Extend: 10696593Smarkm OS << "Extend"; 10796593Smarkm break; 10896593Smarkm case Ignore: 10996593Smarkm OS << "Ignore"; 11096593Smarkm break; 11196593Smarkm case Indirect: 11296593Smarkm OS << "Indirect Align=" << getIndirectAlign() 11396593Smarkm << " ByVal=" << getIndirectByVal() 11496593Smarkm << " Realign=" << getIndirectRealign(); 11596593Smarkm break; 11696593Smarkm case Expand: 11796593Smarkm OS << "Expand"; 11896593Smarkm break; 11996593Smarkm } 12096593Smarkm OS << ")\n"; 12196593Smarkm} 12296593Smarkm 12396593SmarkmTargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; } 12496593Smarkm 12596593Smarkm// If someone can figure out a general rule for this, that would be great. 12696593Smarkm// It's probably just doomed to be platform-dependent, though. 12796593Smarkmunsigned TargetCodeGenInfo::getSizeOfUnwindException() const { 12896593Smarkm // Verified for: 12996593Smarkm // x86-64 FreeBSD, Linux, Darwin 13096593Smarkm // x86-32 FreeBSD, Linux, Darwin 13196593Smarkm // PowerPC Linux, Darwin 13296593Smarkm // ARM Darwin (*not* EABI) 133142429Snectar // AArch64 Linux 13496593Smarkm return 32; 135100946Snectar} 136296341Sdelphij 137215698Ssimonbool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args, 138215698Ssimon const FunctionNoProtoType *fnType) const { 139215698Ssimon // The following conventions are known to require this to be false: 140215698Ssimon // x86_stdcall 14196593Smarkm // MIPS 14296593Smarkm // For everything else, we just prefer false unless we opt out. 14396593Smarkm return false; 14496593Smarkm} 14596593Smarkm 14696593Smarkmstatic bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays); 147215698Ssimon 14896593Smarkm/// isEmptyField - Return true iff a the field is "empty", that is it 14996593Smarkm/// is an unnamed bit-field or an (array of) empty record(s). 15096593Smarkmstatic bool isEmptyField(ASTContext &Context, const FieldDecl *FD, 15196593Smarkm bool AllowArrays) { 15296593Smarkm if (FD->isUnnamedBitfield()) 153279264Sdelphij return true; 15496593Smarkm 15596593Smarkm QualType FT = FD->getType(); 15696593Smarkm 15796593Smarkm // Constant arrays of empty records count as empty, strip them off. 15896593Smarkm // Constant arrays of zero length always count as empty. 15996593Smarkm if (AllowArrays) 16096593Smarkm while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 16196593Smarkm if (AT->getSize() == 0) 16296593Smarkm return true; 16396593Smarkm FT = AT->getElementType(); 16496593Smarkm } 16596593Smarkm 16696593Smarkm const RecordType *RT = FT->getAs<RecordType>(); 16796593Smarkm if (!RT) 16896593Smarkm return false; 16996593Smarkm 17096593Smarkm // C++ record fields are never empty, at least in the Itanium ABI. 17196593Smarkm // 172 // FIXME: We should use a predicate for whether this behavior is true in the 173 // current ABI. 174 if (isa<CXXRecordDecl>(RT->getDecl())) 175 return false; 176 177 return isEmptyRecord(Context, FT, AllowArrays); 178} 179 180/// isEmptyRecord - Return true iff a structure contains only empty 181/// fields. Note that a structure with a flexible array member is not 182/// considered empty. 183static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) { 184 const RecordType *RT = T->getAs<RecordType>(); 185 if (!RT) 186 return 0; 187 const RecordDecl *RD = RT->getDecl(); 188 if (RD->hasFlexibleArrayMember()) 189 return false; 190 191 // If this is a C++ record, check the bases first. 192 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 193 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 194 e = CXXRD->bases_end(); i != e; ++i) 195 if (!isEmptyRecord(Context, i->getType(), true)) 196 return false; 197 198 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 199 i != e; ++i) 200 if (!isEmptyField(Context, *i, AllowArrays)) 201 return false; 202 return true; 203} 204 205/// isSingleElementStruct - Determine if a structure is a "single 206/// element struct", i.e. it has exactly one non-empty field or 207/// exactly one field which is itself a single element 208/// struct. Structures with flexible array members are never 209/// considered single element structs. 210/// 211/// \return The field declaration for the single non-empty field, if 212/// it exists. 213static const Type *isSingleElementStruct(QualType T, ASTContext &Context) { 214 const RecordType *RT = T->getAsStructureType(); 215 if (!RT) 216 return 0; 217 218 const RecordDecl *RD = RT->getDecl(); 219 if (RD->hasFlexibleArrayMember()) 220 return 0; 221 222 const Type *Found = 0; 223 224 // If this is a C++ record, check the bases first. 225 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 226 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 227 e = CXXRD->bases_end(); i != e; ++i) { 228 // Ignore empty records. 229 if (isEmptyRecord(Context, i->getType(), true)) 230 continue; 231 232 // If we already found an element then this isn't a single-element struct. 233 if (Found) 234 return 0; 235 236 // If this is non-empty and not a single element struct, the composite 237 // cannot be a single element struct. 238 Found = isSingleElementStruct(i->getType(), Context); 239 if (!Found) 240 return 0; 241 } 242 } 243 244 // Check for single element. 245 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 246 i != e; ++i) { 247 const FieldDecl *FD = *i; 248 QualType FT = FD->getType(); 249 250 // Ignore empty fields. 251 if (isEmptyField(Context, FD, true)) 252 continue; 253 254 // If we already found an element then this isn't a single-element 255 // struct. 256 if (Found) 257 return 0; 258 259 // Treat single element arrays as the element. 260 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 261 if (AT->getSize().getZExtValue() != 1) 262 break; 263 FT = AT->getElementType(); 264 } 265 266 if (!isAggregateTypeForABI(FT)) { 267 Found = FT.getTypePtr(); 268 } else { 269 Found = isSingleElementStruct(FT, Context); 270 if (!Found) 271 return 0; 272 } 273 } 274 275 // We don't consider a struct a single-element struct if it has 276 // padding beyond the element type. 277 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T)) 278 return 0; 279 280 return Found; 281} 282 283static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) { 284 // Treat complex types as the element type. 285 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) 286 Ty = CTy->getElementType(); 287 288 // Check for a type which we know has a simple scalar argument-passing 289 // convention without any padding. (We're specifically looking for 32 290 // and 64-bit integer and integer-equivalents, float, and double.) 291 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() && 292 !Ty->isEnumeralType() && !Ty->isBlockPointerType()) 293 return false; 294 295 uint64_t Size = Context.getTypeSize(Ty); 296 return Size == 32 || Size == 64; 297} 298 299/// canExpandIndirectArgument - Test whether an argument type which is to be 300/// passed indirectly (on the stack) would have the equivalent layout if it was 301/// expanded into separate arguments. If so, we prefer to do the latter to avoid 302/// inhibiting optimizations. 303/// 304// FIXME: This predicate is missing many cases, currently it just follows 305// llvm-gcc (checks that all fields are 32-bit or 64-bit primitive types). We 306// should probably make this smarter, or better yet make the LLVM backend 307// capable of handling it. 308static bool canExpandIndirectArgument(QualType Ty, ASTContext &Context) { 309 // We can only expand structure types. 310 const RecordType *RT = Ty->getAs<RecordType>(); 311 if (!RT) 312 return false; 313 314 // We can only expand (C) structures. 315 // 316 // FIXME: This needs to be generalized to handle classes as well. 317 const RecordDecl *RD = RT->getDecl(); 318 if (!RD->isStruct() || isa<CXXRecordDecl>(RD)) 319 return false; 320 321 uint64_t Size = 0; 322 323 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 324 i != e; ++i) { 325 const FieldDecl *FD = *i; 326 327 if (!is32Or64BitBasicType(FD->getType(), Context)) 328 return false; 329 330 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know 331 // how to expand them yet, and the predicate for telling if a bitfield still 332 // counts as "basic" is more complicated than what we were doing previously. 333 if (FD->isBitField()) 334 return false; 335 336 Size += Context.getTypeSize(FD->getType()); 337 } 338 339 // Make sure there are not any holes in the struct. 340 if (Size != Context.getTypeSize(Ty)) 341 return false; 342 343 return true; 344} 345 346namespace { 347/// DefaultABIInfo - The default implementation for ABI specific 348/// details. This implementation provides information which results in 349/// self-consistent and sensible LLVM IR generation, but does not 350/// conform to any particular ABI. 351class DefaultABIInfo : public ABIInfo { 352public: 353 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 354 355 ABIArgInfo classifyReturnType(QualType RetTy) const; 356 ABIArgInfo classifyArgumentType(QualType RetTy) const; 357 358 virtual void computeInfo(CGFunctionInfo &FI) const { 359 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 360 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 361 it != ie; ++it) 362 it->info = classifyArgumentType(it->type); 363 } 364 365 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 366 CodeGenFunction &CGF) const; 367}; 368 369class DefaultTargetCodeGenInfo : public TargetCodeGenInfo { 370public: 371 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 372 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 373}; 374 375llvm::Value *DefaultABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 376 CodeGenFunction &CGF) const { 377 return 0; 378} 379 380ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const { 381 if (isAggregateTypeForABI(Ty)) { 382 // Records with non trivial destructors/constructors should not be passed 383 // by value. 384 if (isRecordReturnIndirect(Ty, CGT)) 385 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 386 387 return ABIArgInfo::getIndirect(0); 388 } 389 390 // Treat an enum type as its underlying type. 391 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 392 Ty = EnumTy->getDecl()->getIntegerType(); 393 394 return (Ty->isPromotableIntegerType() ? 395 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 396} 397 398ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const { 399 if (RetTy->isVoidType()) 400 return ABIArgInfo::getIgnore(); 401 402 if (isAggregateTypeForABI(RetTy)) 403 return ABIArgInfo::getIndirect(0); 404 405 // Treat an enum type as its underlying type. 406 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 407 RetTy = EnumTy->getDecl()->getIntegerType(); 408 409 return (RetTy->isPromotableIntegerType() ? 410 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 411} 412 413//===----------------------------------------------------------------------===// 414// le32/PNaCl bitcode ABI Implementation 415// 416// This is a simplified version of the x86_32 ABI. Arguments and return values 417// are always passed on the stack. 418//===----------------------------------------------------------------------===// 419 420class PNaClABIInfo : public ABIInfo { 421 public: 422 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 423 424 ABIArgInfo classifyReturnType(QualType RetTy) const; 425 ABIArgInfo classifyArgumentType(QualType RetTy) const; 426 427 virtual void computeInfo(CGFunctionInfo &FI) const; 428 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 429 CodeGenFunction &CGF) const; 430}; 431 432class PNaClTargetCodeGenInfo : public TargetCodeGenInfo { 433 public: 434 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 435 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {} 436}; 437 438void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const { 439 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 440 441 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 442 it != ie; ++it) 443 it->info = classifyArgumentType(it->type); 444 } 445 446llvm::Value *PNaClABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 447 CodeGenFunction &CGF) const { 448 return 0; 449} 450 451/// \brief Classify argument of given type \p Ty. 452ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const { 453 if (isAggregateTypeForABI(Ty)) { 454 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) 455 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 456 return ABIArgInfo::getIndirect(0); 457 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) { 458 // Treat an enum type as its underlying type. 459 Ty = EnumTy->getDecl()->getIntegerType(); 460 } else if (Ty->isFloatingType()) { 461 // Floating-point types don't go inreg. 462 return ABIArgInfo::getDirect(); 463 } 464 465 return (Ty->isPromotableIntegerType() ? 466 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 467} 468 469ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const { 470 if (RetTy->isVoidType()) 471 return ABIArgInfo::getIgnore(); 472 473 // In the PNaCl ABI we always return records/structures on the stack. 474 if (isAggregateTypeForABI(RetTy)) 475 return ABIArgInfo::getIndirect(0); 476 477 // Treat an enum type as its underlying type. 478 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 479 RetTy = EnumTy->getDecl()->getIntegerType(); 480 481 return (RetTy->isPromotableIntegerType() ? 482 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 483} 484 485/// IsX86_MMXType - Return true if this is an MMX type. 486bool IsX86_MMXType(llvm::Type *IRType) { 487 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>. 488 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && 489 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && 490 IRType->getScalarSizeInBits() != 64; 491} 492 493static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 494 StringRef Constraint, 495 llvm::Type* Ty) { 496 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) 497 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); 498 return Ty; 499} 500 501//===----------------------------------------------------------------------===// 502// X86-32 ABI Implementation 503//===----------------------------------------------------------------------===// 504 505/// X86_32ABIInfo - The X86-32 ABI information. 506class X86_32ABIInfo : public ABIInfo { 507 enum Class { 508 Integer, 509 Float 510 }; 511 512 static const unsigned MinABIStackAlignInBytes = 4; 513 514 bool IsDarwinVectorABI; 515 bool IsSmallStructInRegABI; 516 bool IsWin32StructABI; 517 unsigned DefaultNumRegisterParameters; 518 519 static bool isRegisterSize(unsigned Size) { 520 return (Size == 8 || Size == 16 || Size == 32 || Size == 64); 521 } 522 523 static bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context, 524 unsigned callingConvention); 525 526 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 527 /// such that the argument will be passed in memory. 528 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, 529 unsigned &FreeRegs) const; 530 531 /// \brief Return the alignment to use for the given type on the stack. 532 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const; 533 534 Class classify(QualType Ty) const; 535 ABIArgInfo classifyReturnType(QualType RetTy, 536 unsigned callingConvention) const; 537 ABIArgInfo classifyArgumentType(QualType RetTy, unsigned &FreeRegs, 538 bool IsFastCall) const; 539 bool shouldUseInReg(QualType Ty, unsigned &FreeRegs, 540 bool IsFastCall, bool &NeedsPadding) const; 541 542public: 543 544 virtual void computeInfo(CGFunctionInfo &FI) const; 545 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 546 CodeGenFunction &CGF) const; 547 548 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w, 549 unsigned r) 550 : ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p), 551 IsWin32StructABI(w), DefaultNumRegisterParameters(r) {} 552}; 553 554class X86_32TargetCodeGenInfo : public TargetCodeGenInfo { 555public: 556 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 557 bool d, bool p, bool w, unsigned r) 558 :TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {} 559 560 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 561 CodeGen::CodeGenModule &CGM) const; 562 563 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 564 // Darwin uses different dwarf register numbers for EH. 565 if (CGM.getTarget().getTriple().isOSDarwin()) return 5; 566 return 4; 567 } 568 569 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 570 llvm::Value *Address) const; 571 572 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 573 StringRef Constraint, 574 llvm::Type* Ty) const { 575 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 576 } 577 578}; 579 580} 581 582/// shouldReturnTypeInRegister - Determine if the given type should be 583/// passed in a register (for the Darwin ABI). 584bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty, 585 ASTContext &Context, 586 unsigned callingConvention) { 587 uint64_t Size = Context.getTypeSize(Ty); 588 589 // Type must be register sized. 590 if (!isRegisterSize(Size)) 591 return false; 592 593 if (Ty->isVectorType()) { 594 // 64- and 128- bit vectors inside structures are not returned in 595 // registers. 596 if (Size == 64 || Size == 128) 597 return false; 598 599 return true; 600 } 601 602 // If this is a builtin, pointer, enum, complex type, member pointer, or 603 // member function pointer it is ok. 604 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() || 605 Ty->isAnyComplexType() || Ty->isEnumeralType() || 606 Ty->isBlockPointerType() || Ty->isMemberPointerType()) 607 return true; 608 609 // Arrays are treated like records. 610 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) 611 return shouldReturnTypeInRegister(AT->getElementType(), Context, 612 callingConvention); 613 614 // Otherwise, it must be a record type. 615 const RecordType *RT = Ty->getAs<RecordType>(); 616 if (!RT) return false; 617 618 // FIXME: Traverse bases here too. 619 620 // For thiscall conventions, structures will never be returned in 621 // a register. This is for compatibility with the MSVC ABI 622 if (callingConvention == llvm::CallingConv::X86_ThisCall && 623 RT->isStructureType()) { 624 return false; 625 } 626 627 // Structure types are passed in register if all fields would be 628 // passed in a register. 629 for (RecordDecl::field_iterator i = RT->getDecl()->field_begin(), 630 e = RT->getDecl()->field_end(); i != e; ++i) { 631 const FieldDecl *FD = *i; 632 633 // Empty fields are ignored. 634 if (isEmptyField(Context, FD, true)) 635 continue; 636 637 // Check fields recursively. 638 if (!shouldReturnTypeInRegister(FD->getType(), Context, 639 callingConvention)) 640 return false; 641 } 642 return true; 643} 644 645ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, 646 unsigned callingConvention) const { 647 if (RetTy->isVoidType()) 648 return ABIArgInfo::getIgnore(); 649 650 if (const VectorType *VT = RetTy->getAs<VectorType>()) { 651 // On Darwin, some vectors are returned in registers. 652 if (IsDarwinVectorABI) { 653 uint64_t Size = getContext().getTypeSize(RetTy); 654 655 // 128-bit vectors are a special case; they are returned in 656 // registers and we need to make sure to pick a type the LLVM 657 // backend will like. 658 if (Size == 128) 659 return ABIArgInfo::getDirect(llvm::VectorType::get( 660 llvm::Type::getInt64Ty(getVMContext()), 2)); 661 662 // Always return in register if it fits in a general purpose 663 // register, or if it is 64 bits and has a single element. 664 if ((Size == 8 || Size == 16 || Size == 32) || 665 (Size == 64 && VT->getNumElements() == 1)) 666 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 667 Size)); 668 669 return ABIArgInfo::getIndirect(0); 670 } 671 672 return ABIArgInfo::getDirect(); 673 } 674 675 if (isAggregateTypeForABI(RetTy)) { 676 if (const RecordType *RT = RetTy->getAs<RecordType>()) { 677 if (isRecordReturnIndirect(RT, CGT)) 678 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 679 680 // Structures with flexible arrays are always indirect. 681 if (RT->getDecl()->hasFlexibleArrayMember()) 682 return ABIArgInfo::getIndirect(0); 683 } 684 685 // If specified, structs and unions are always indirect. 686 if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType()) 687 return ABIArgInfo::getIndirect(0); 688 689 // Small structures which are register sized are generally returned 690 // in a register. 691 if (X86_32ABIInfo::shouldReturnTypeInRegister(RetTy, getContext(), 692 callingConvention)) { 693 uint64_t Size = getContext().getTypeSize(RetTy); 694 695 // As a special-case, if the struct is a "single-element" struct, and 696 // the field is of type "float" or "double", return it in a 697 // floating-point register. (MSVC does not apply this special case.) 698 // We apply a similar transformation for pointer types to improve the 699 // quality of the generated IR. 700 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 701 if ((!IsWin32StructABI && SeltTy->isRealFloatingType()) 702 || SeltTy->hasPointerRepresentation()) 703 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 704 705 // FIXME: We should be able to narrow this integer in cases with dead 706 // padding. 707 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size)); 708 } 709 710 return ABIArgInfo::getIndirect(0); 711 } 712 713 // Treat an enum type as its underlying type. 714 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 715 RetTy = EnumTy->getDecl()->getIntegerType(); 716 717 return (RetTy->isPromotableIntegerType() ? 718 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 719} 720 721static bool isSSEVectorType(ASTContext &Context, QualType Ty) { 722 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128; 723} 724 725static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) { 726 const RecordType *RT = Ty->getAs<RecordType>(); 727 if (!RT) 728 return 0; 729 const RecordDecl *RD = RT->getDecl(); 730 731 // If this is a C++ record, check the bases first. 732 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 733 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 734 e = CXXRD->bases_end(); i != e; ++i) 735 if (!isRecordWithSSEVectorType(Context, i->getType())) 736 return false; 737 738 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 739 i != e; ++i) { 740 QualType FT = i->getType(); 741 742 if (isSSEVectorType(Context, FT)) 743 return true; 744 745 if (isRecordWithSSEVectorType(Context, FT)) 746 return true; 747 } 748 749 return false; 750} 751 752unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, 753 unsigned Align) const { 754 // Otherwise, if the alignment is less than or equal to the minimum ABI 755 // alignment, just use the default; the backend will handle this. 756 if (Align <= MinABIStackAlignInBytes) 757 return 0; // Use default alignment. 758 759 // On non-Darwin, the stack type alignment is always 4. 760 if (!IsDarwinVectorABI) { 761 // Set explicit alignment, since we may need to realign the top. 762 return MinABIStackAlignInBytes; 763 } 764 765 // Otherwise, if the type contains an SSE vector type, the alignment is 16. 766 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) || 767 isRecordWithSSEVectorType(getContext(), Ty))) 768 return 16; 769 770 return MinABIStackAlignInBytes; 771} 772 773ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal, 774 unsigned &FreeRegs) const { 775 if (!ByVal) { 776 if (FreeRegs) { 777 --FreeRegs; // Non byval indirects just use one pointer. 778 return ABIArgInfo::getIndirectInReg(0, false); 779 } 780 return ABIArgInfo::getIndirect(0, false); 781 } 782 783 // Compute the byval alignment. 784 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 785 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign); 786 if (StackAlign == 0) 787 return ABIArgInfo::getIndirect(4); 788 789 // If the stack alignment is less than the type alignment, realign the 790 // argument. 791 if (StackAlign < TypeAlign) 792 return ABIArgInfo::getIndirect(StackAlign, /*ByVal=*/true, 793 /*Realign=*/true); 794 795 return ABIArgInfo::getIndirect(StackAlign); 796} 797 798X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const { 799 const Type *T = isSingleElementStruct(Ty, getContext()); 800 if (!T) 801 T = Ty.getTypePtr(); 802 803 if (const BuiltinType *BT = T->getAs<BuiltinType>()) { 804 BuiltinType::Kind K = BT->getKind(); 805 if (K == BuiltinType::Float || K == BuiltinType::Double) 806 return Float; 807 } 808 return Integer; 809} 810 811bool X86_32ABIInfo::shouldUseInReg(QualType Ty, unsigned &FreeRegs, 812 bool IsFastCall, bool &NeedsPadding) const { 813 NeedsPadding = false; 814 Class C = classify(Ty); 815 if (C == Float) 816 return false; 817 818 unsigned Size = getContext().getTypeSize(Ty); 819 unsigned SizeInRegs = (Size + 31) / 32; 820 821 if (SizeInRegs == 0) 822 return false; 823 824 if (SizeInRegs > FreeRegs) { 825 FreeRegs = 0; 826 return false; 827 } 828 829 FreeRegs -= SizeInRegs; 830 831 if (IsFastCall) { 832 if (Size > 32) 833 return false; 834 835 if (Ty->isIntegralOrEnumerationType()) 836 return true; 837 838 if (Ty->isPointerType()) 839 return true; 840 841 if (Ty->isReferenceType()) 842 return true; 843 844 if (FreeRegs) 845 NeedsPadding = true; 846 847 return false; 848 } 849 850 return true; 851} 852 853ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, 854 unsigned &FreeRegs, 855 bool IsFastCall) const { 856 // FIXME: Set alignment on indirect arguments. 857 if (isAggregateTypeForABI(Ty)) { 858 if (const RecordType *RT = Ty->getAs<RecordType>()) { 859 if (IsWin32StructABI) 860 return getIndirectResult(Ty, true, FreeRegs); 861 862 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, CGT)) 863 return getIndirectResult(Ty, RAA == CGCXXABI::RAA_DirectInMemory, FreeRegs); 864 865 // Structures with flexible arrays are always indirect. 866 if (RT->getDecl()->hasFlexibleArrayMember()) 867 return getIndirectResult(Ty, true, FreeRegs); 868 } 869 870 // Ignore empty structs/unions. 871 if (isEmptyRecord(getContext(), Ty, true)) 872 return ABIArgInfo::getIgnore(); 873 874 llvm::LLVMContext &LLVMContext = getVMContext(); 875 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); 876 bool NeedsPadding; 877 if (shouldUseInReg(Ty, FreeRegs, IsFastCall, NeedsPadding)) { 878 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 879 SmallVector<llvm::Type*, 3> Elements; 880 for (unsigned I = 0; I < SizeInRegs; ++I) 881 Elements.push_back(Int32); 882 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 883 return ABIArgInfo::getDirectInReg(Result); 884 } 885 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : 0; 886 887 // Expand small (<= 128-bit) record types when we know that the stack layout 888 // of those arguments will match the struct. This is important because the 889 // LLVM backend isn't smart enough to remove byval, which inhibits many 890 // optimizations. 891 if (getContext().getTypeSize(Ty) <= 4*32 && 892 canExpandIndirectArgument(Ty, getContext())) 893 return ABIArgInfo::getExpandWithPadding(IsFastCall, PaddingType); 894 895 return getIndirectResult(Ty, true, FreeRegs); 896 } 897 898 if (const VectorType *VT = Ty->getAs<VectorType>()) { 899 // On Darwin, some vectors are passed in memory, we handle this by passing 900 // it as an i8/i16/i32/i64. 901 if (IsDarwinVectorABI) { 902 uint64_t Size = getContext().getTypeSize(Ty); 903 if ((Size == 8 || Size == 16 || Size == 32) || 904 (Size == 64 && VT->getNumElements() == 1)) 905 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 906 Size)); 907 } 908 909 if (IsX86_MMXType(CGT.ConvertType(Ty))) 910 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64)); 911 912 return ABIArgInfo::getDirect(); 913 } 914 915 916 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 917 Ty = EnumTy->getDecl()->getIntegerType(); 918 919 bool NeedsPadding; 920 bool InReg = shouldUseInReg(Ty, FreeRegs, IsFastCall, NeedsPadding); 921 922 if (Ty->isPromotableIntegerType()) { 923 if (InReg) 924 return ABIArgInfo::getExtendInReg(); 925 return ABIArgInfo::getExtend(); 926 } 927 if (InReg) 928 return ABIArgInfo::getDirectInReg(); 929 return ABIArgInfo::getDirect(); 930} 931 932void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { 933 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), 934 FI.getCallingConvention()); 935 936 unsigned CC = FI.getCallingConvention(); 937 bool IsFastCall = CC == llvm::CallingConv::X86_FastCall; 938 unsigned FreeRegs; 939 if (IsFastCall) 940 FreeRegs = 2; 941 else if (FI.getHasRegParm()) 942 FreeRegs = FI.getRegParm(); 943 else 944 FreeRegs = DefaultNumRegisterParameters; 945 946 // If the return value is indirect, then the hidden argument is consuming one 947 // integer register. 948 if (FI.getReturnInfo().isIndirect() && FreeRegs) { 949 --FreeRegs; 950 ABIArgInfo &Old = FI.getReturnInfo(); 951 Old = ABIArgInfo::getIndirectInReg(Old.getIndirectAlign(), 952 Old.getIndirectByVal(), 953 Old.getIndirectRealign()); 954 } 955 956 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 957 it != ie; ++it) 958 it->info = classifyArgumentType(it->type, FreeRegs, IsFastCall); 959} 960 961llvm::Value *X86_32ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 962 CodeGenFunction &CGF) const { 963 llvm::Type *BPP = CGF.Int8PtrPtrTy; 964 965 CGBuilderTy &Builder = CGF.Builder; 966 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 967 "ap"); 968 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 969 970 // Compute if the address needs to be aligned 971 unsigned Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); 972 Align = getTypeStackAlignInBytes(Ty, Align); 973 Align = std::max(Align, 4U); 974 if (Align > 4) { 975 // addr = (addr + align - 1) & -align; 976 llvm::Value *Offset = 977 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1); 978 Addr = CGF.Builder.CreateGEP(Addr, Offset); 979 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(Addr, 980 CGF.Int32Ty); 981 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align); 982 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 983 Addr->getType(), 984 "ap.cur.aligned"); 985 } 986 987 llvm::Type *PTy = 988 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 989 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 990 991 uint64_t Offset = 992 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, Align); 993 llvm::Value *NextAddr = 994 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 995 "ap.next"); 996 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 997 998 return AddrTyped; 999} 1000 1001void X86_32TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 1002 llvm::GlobalValue *GV, 1003 CodeGen::CodeGenModule &CGM) const { 1004 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 1005 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 1006 // Get the LLVM function. 1007 llvm::Function *Fn = cast<llvm::Function>(GV); 1008 1009 // Now add the 'alignstack' attribute with a value of 16. 1010 llvm::AttrBuilder B; 1011 B.addStackAlignmentAttr(16); 1012 Fn->addAttributes(llvm::AttributeSet::FunctionIndex, 1013 llvm::AttributeSet::get(CGM.getLLVMContext(), 1014 llvm::AttributeSet::FunctionIndex, 1015 B)); 1016 } 1017 } 1018} 1019 1020bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable( 1021 CodeGen::CodeGenFunction &CGF, 1022 llvm::Value *Address) const { 1023 CodeGen::CGBuilderTy &Builder = CGF.Builder; 1024 1025 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 1026 1027 // 0-7 are the eight integer registers; the order is different 1028 // on Darwin (for EH), but the range is the same. 1029 // 8 is %eip. 1030 AssignToArrayRange(Builder, Address, Four8, 0, 8); 1031 1032 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) { 1033 // 12-16 are st(0..4). Not sure why we stop at 4. 1034 // These have size 16, which is sizeof(long double) on 1035 // platforms with 8-byte alignment for that type. 1036 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 1037 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16); 1038 1039 } else { 1040 // 9 is %eflags, which doesn't get a size on Darwin for some 1041 // reason. 1042 Builder.CreateStore(Four8, Builder.CreateConstInBoundsGEP1_32(Address, 9)); 1043 1044 // 11-16 are st(0..5). Not sure why we stop at 5. 1045 // These have size 12, which is sizeof(long double) on 1046 // platforms with 4-byte alignment for that type. 1047 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12); 1048 AssignToArrayRange(Builder, Address, Twelve8, 11, 16); 1049 } 1050 1051 return false; 1052} 1053 1054//===----------------------------------------------------------------------===// 1055// X86-64 ABI Implementation 1056//===----------------------------------------------------------------------===// 1057 1058 1059namespace { 1060/// X86_64ABIInfo - The X86_64 ABI information. 1061class X86_64ABIInfo : public ABIInfo { 1062 enum Class { 1063 Integer = 0, 1064 SSE, 1065 SSEUp, 1066 X87, 1067 X87Up, 1068 ComplexX87, 1069 NoClass, 1070 Memory 1071 }; 1072 1073 /// merge - Implement the X86_64 ABI merging algorithm. 1074 /// 1075 /// Merge an accumulating classification \arg Accum with a field 1076 /// classification \arg Field. 1077 /// 1078 /// \param Accum - The accumulating classification. This should 1079 /// always be either NoClass or the result of a previous merge 1080 /// call. In addition, this should never be Memory (the caller 1081 /// should just return Memory for the aggregate). 1082 static Class merge(Class Accum, Class Field); 1083 1084 /// postMerge - Implement the X86_64 ABI post merging algorithm. 1085 /// 1086 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 1087 /// final MEMORY or SSE classes when necessary. 1088 /// 1089 /// \param AggregateSize - The size of the current aggregate in 1090 /// the classification process. 1091 /// 1092 /// \param Lo - The classification for the parts of the type 1093 /// residing in the low word of the containing object. 1094 /// 1095 /// \param Hi - The classification for the parts of the type 1096 /// residing in the higher words of the containing object. 1097 /// 1098 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 1099 1100 /// classify - Determine the x86_64 register classes in which the 1101 /// given type T should be passed. 1102 /// 1103 /// \param Lo - The classification for the parts of the type 1104 /// residing in the low word of the containing object. 1105 /// 1106 /// \param Hi - The classification for the parts of the type 1107 /// residing in the high word of the containing object. 1108 /// 1109 /// \param OffsetBase - The bit offset of this type in the 1110 /// containing object. Some parameters are classified different 1111 /// depending on whether they straddle an eightbyte boundary. 1112 /// 1113 /// If a word is unused its result will be NoClass; if a type should 1114 /// be passed in Memory then at least the classification of \arg Lo 1115 /// will be Memory. 1116 /// 1117 /// The \arg Lo class will be NoClass iff the argument is ignored. 1118 /// 1119 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 1120 /// also be ComplexX87. 1121 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const; 1122 1123 llvm::Type *GetByteVectorType(QualType Ty) const; 1124 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType, 1125 unsigned IROffset, QualType SourceTy, 1126 unsigned SourceOffset) const; 1127 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType, 1128 unsigned IROffset, QualType SourceTy, 1129 unsigned SourceOffset) const; 1130 1131 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1132 /// such that the argument will be returned in memory. 1133 ABIArgInfo getIndirectReturnResult(QualType Ty) const; 1134 1135 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1136 /// such that the argument will be passed in memory. 1137 /// 1138 /// \param freeIntRegs - The number of free integer registers remaining 1139 /// available. 1140 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const; 1141 1142 ABIArgInfo classifyReturnType(QualType RetTy) const; 1143 1144 ABIArgInfo classifyArgumentType(QualType Ty, 1145 unsigned freeIntRegs, 1146 unsigned &neededInt, 1147 unsigned &neededSSE) const; 1148 1149 bool IsIllegalVectorType(QualType Ty) const; 1150 1151 /// The 0.98 ABI revision clarified a lot of ambiguities, 1152 /// unfortunately in ways that were not always consistent with 1153 /// certain previous compilers. In particular, platforms which 1154 /// required strict binary compatibility with older versions of GCC 1155 /// may need to exempt themselves. 1156 bool honorsRevision0_98() const { 1157 return !getTarget().getTriple().isOSDarwin(); 1158 } 1159 1160 bool HasAVX; 1161 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on 1162 // 64-bit hardware. 1163 bool Has64BitPointers; 1164 1165public: 1166 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool hasavx) : 1167 ABIInfo(CGT), HasAVX(hasavx), 1168 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) { 1169 } 1170 1171 bool isPassedUsingAVXType(QualType type) const { 1172 unsigned neededInt, neededSSE; 1173 // The freeIntRegs argument doesn't matter here. 1174 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE); 1175 if (info.isDirect()) { 1176 llvm::Type *ty = info.getCoerceToType(); 1177 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty)) 1178 return (vectorTy->getBitWidth() > 128); 1179 } 1180 return false; 1181 } 1182 1183 virtual void computeInfo(CGFunctionInfo &FI) const; 1184 1185 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1186 CodeGenFunction &CGF) const; 1187}; 1188 1189/// WinX86_64ABIInfo - The Windows X86_64 ABI information. 1190class WinX86_64ABIInfo : public ABIInfo { 1191 1192 ABIArgInfo classify(QualType Ty, bool IsReturnType) const; 1193 1194public: 1195 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 1196 1197 virtual void computeInfo(CGFunctionInfo &FI) const; 1198 1199 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1200 CodeGenFunction &CGF) const; 1201}; 1202 1203class X86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1204public: 1205 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 1206 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, HasAVX)) {} 1207 1208 const X86_64ABIInfo &getABIInfo() const { 1209 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 1210 } 1211 1212 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1213 return 7; 1214 } 1215 1216 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1217 llvm::Value *Address) const { 1218 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1219 1220 // 0-15 are the 16 integer registers. 1221 // 16 is %rip. 1222 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1223 return false; 1224 } 1225 1226 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 1227 StringRef Constraint, 1228 llvm::Type* Ty) const { 1229 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 1230 } 1231 1232 bool isNoProtoCallVariadic(const CallArgList &args, 1233 const FunctionNoProtoType *fnType) const { 1234 // The default CC on x86-64 sets %al to the number of SSA 1235 // registers used, and GCC sets this when calling an unprototyped 1236 // function, so we override the default behavior. However, don't do 1237 // that when AVX types are involved: the ABI explicitly states it is 1238 // undefined, and it doesn't work in practice because of how the ABI 1239 // defines varargs anyway. 1240 if (fnType->getCallConv() == CC_Default || fnType->getCallConv() == CC_C) { 1241 bool HasAVXType = false; 1242 for (CallArgList::const_iterator 1243 it = args.begin(), ie = args.end(); it != ie; ++it) { 1244 if (getABIInfo().isPassedUsingAVXType(it->Ty)) { 1245 HasAVXType = true; 1246 break; 1247 } 1248 } 1249 1250 if (!HasAVXType) 1251 return true; 1252 } 1253 1254 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType); 1255 } 1256 1257}; 1258 1259class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1260public: 1261 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 1262 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {} 1263 1264 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1265 return 7; 1266 } 1267 1268 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1269 llvm::Value *Address) const { 1270 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1271 1272 // 0-15 are the 16 integer registers. 1273 // 16 is %rip. 1274 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1275 return false; 1276 } 1277}; 1278 1279} 1280 1281void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, 1282 Class &Hi) const { 1283 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done: 1284 // 1285 // (a) If one of the classes is Memory, the whole argument is passed in 1286 // memory. 1287 // 1288 // (b) If X87UP is not preceded by X87, the whole argument is passed in 1289 // memory. 1290 // 1291 // (c) If the size of the aggregate exceeds two eightbytes and the first 1292 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole 1293 // argument is passed in memory. NOTE: This is necessary to keep the 1294 // ABI working for processors that don't support the __m256 type. 1295 // 1296 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE. 1297 // 1298 // Some of these are enforced by the merging logic. Others can arise 1299 // only with unions; for example: 1300 // union { _Complex double; unsigned; } 1301 // 1302 // Note that clauses (b) and (c) were added in 0.98. 1303 // 1304 if (Hi == Memory) 1305 Lo = Memory; 1306 if (Hi == X87Up && Lo != X87 && honorsRevision0_98()) 1307 Lo = Memory; 1308 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) 1309 Lo = Memory; 1310 if (Hi == SSEUp && Lo != SSE) 1311 Hi = SSE; 1312} 1313 1314X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) { 1315 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is 1316 // classified recursively so that always two fields are 1317 // considered. The resulting class is calculated according to 1318 // the classes of the fields in the eightbyte: 1319 // 1320 // (a) If both classes are equal, this is the resulting class. 1321 // 1322 // (b) If one of the classes is NO_CLASS, the resulting class is 1323 // the other class. 1324 // 1325 // (c) If one of the classes is MEMORY, the result is the MEMORY 1326 // class. 1327 // 1328 // (d) If one of the classes is INTEGER, the result is the 1329 // INTEGER. 1330 // 1331 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class, 1332 // MEMORY is used as class. 1333 // 1334 // (f) Otherwise class SSE is used. 1335 1336 // Accum should never be memory (we should have returned) or 1337 // ComplexX87 (because this cannot be passed in a structure). 1338 assert((Accum != Memory && Accum != ComplexX87) && 1339 "Invalid accumulated classification during merge."); 1340 if (Accum == Field || Field == NoClass) 1341 return Accum; 1342 if (Field == Memory) 1343 return Memory; 1344 if (Accum == NoClass) 1345 return Field; 1346 if (Accum == Integer || Field == Integer) 1347 return Integer; 1348 if (Field == X87 || Field == X87Up || Field == ComplexX87 || 1349 Accum == X87 || Accum == X87Up) 1350 return Memory; 1351 return SSE; 1352} 1353 1354void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, 1355 Class &Lo, Class &Hi) const { 1356 // FIXME: This code can be simplified by introducing a simple value class for 1357 // Class pairs with appropriate constructor methods for the various 1358 // situations. 1359 1360 // FIXME: Some of the split computations are wrong; unaligned vectors 1361 // shouldn't be passed in registers for example, so there is no chance they 1362 // can straddle an eightbyte. Verify & simplify. 1363 1364 Lo = Hi = NoClass; 1365 1366 Class &Current = OffsetBase < 64 ? Lo : Hi; 1367 Current = Memory; 1368 1369 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 1370 BuiltinType::Kind k = BT->getKind(); 1371 1372 if (k == BuiltinType::Void) { 1373 Current = NoClass; 1374 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) { 1375 Lo = Integer; 1376 Hi = Integer; 1377 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) { 1378 Current = Integer; 1379 } else if ((k == BuiltinType::Float || k == BuiltinType::Double) || 1380 (k == BuiltinType::LongDouble && 1381 getTarget().getTriple().getOS() == llvm::Triple::NaCl)) { 1382 Current = SSE; 1383 } else if (k == BuiltinType::LongDouble) { 1384 Lo = X87; 1385 Hi = X87Up; 1386 } 1387 // FIXME: _Decimal32 and _Decimal64 are SSE. 1388 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp). 1389 return; 1390 } 1391 1392 if (const EnumType *ET = Ty->getAs<EnumType>()) { 1393 // Classify the underlying integer type. 1394 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi); 1395 return; 1396 } 1397 1398 if (Ty->hasPointerRepresentation()) { 1399 Current = Integer; 1400 return; 1401 } 1402 1403 if (Ty->isMemberPointerType()) { 1404 if (Ty->isMemberFunctionPointerType() && Has64BitPointers) 1405 Lo = Hi = Integer; 1406 else 1407 Current = Integer; 1408 return; 1409 } 1410 1411 if (const VectorType *VT = Ty->getAs<VectorType>()) { 1412 uint64_t Size = getContext().getTypeSize(VT); 1413 if (Size == 32) { 1414 // gcc passes all <4 x char>, <2 x short>, <1 x int>, <1 x 1415 // float> as integer. 1416 Current = Integer; 1417 1418 // If this type crosses an eightbyte boundary, it should be 1419 // split. 1420 uint64_t EB_Real = (OffsetBase) / 64; 1421 uint64_t EB_Imag = (OffsetBase + Size - 1) / 64; 1422 if (EB_Real != EB_Imag) 1423 Hi = Lo; 1424 } else if (Size == 64) { 1425 // gcc passes <1 x double> in memory. :( 1426 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) 1427 return; 1428 1429 // gcc passes <1 x long long> as INTEGER. 1430 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::LongLong) || 1431 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULongLong) || 1432 VT->getElementType()->isSpecificBuiltinType(BuiltinType::Long) || 1433 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULong)) 1434 Current = Integer; 1435 else 1436 Current = SSE; 1437 1438 // If this type crosses an eightbyte boundary, it should be 1439 // split. 1440 if (OffsetBase && OffsetBase != 64) 1441 Hi = Lo; 1442 } else if (Size == 128 || (HasAVX && Size == 256)) { 1443 // Arguments of 256-bits are split into four eightbyte chunks. The 1444 // least significant one belongs to class SSE and all the others to class 1445 // SSEUP. The original Lo and Hi design considers that types can't be 1446 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense. 1447 // This design isn't correct for 256-bits, but since there're no cases 1448 // where the upper parts would need to be inspected, avoid adding 1449 // complexity and just consider Hi to match the 64-256 part. 1450 Lo = SSE; 1451 Hi = SSEUp; 1452 } 1453 return; 1454 } 1455 1456 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 1457 QualType ET = getContext().getCanonicalType(CT->getElementType()); 1458 1459 uint64_t Size = getContext().getTypeSize(Ty); 1460 if (ET->isIntegralOrEnumerationType()) { 1461 if (Size <= 64) 1462 Current = Integer; 1463 else if (Size <= 128) 1464 Lo = Hi = Integer; 1465 } else if (ET == getContext().FloatTy) 1466 Current = SSE; 1467 else if (ET == getContext().DoubleTy || 1468 (ET == getContext().LongDoubleTy && 1469 getTarget().getTriple().getOS() == llvm::Triple::NaCl)) 1470 Lo = Hi = SSE; 1471 else if (ET == getContext().LongDoubleTy) 1472 Current = ComplexX87; 1473 1474 // If this complex type crosses an eightbyte boundary then it 1475 // should be split. 1476 uint64_t EB_Real = (OffsetBase) / 64; 1477 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64; 1478 if (Hi == NoClass && EB_Real != EB_Imag) 1479 Hi = Lo; 1480 1481 return; 1482 } 1483 1484 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 1485 // Arrays are treated like structures. 1486 1487 uint64_t Size = getContext().getTypeSize(Ty); 1488 1489 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1490 // than four eightbytes, ..., it has class MEMORY. 1491 if (Size > 256) 1492 return; 1493 1494 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned 1495 // fields, it has class MEMORY. 1496 // 1497 // Only need to check alignment of array base. 1498 if (OffsetBase % getContext().getTypeAlign(AT->getElementType())) 1499 return; 1500 1501 // Otherwise implement simplified merge. We could be smarter about 1502 // this, but it isn't worth it and would be harder to verify. 1503 Current = NoClass; 1504 uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); 1505 uint64_t ArraySize = AT->getSize().getZExtValue(); 1506 1507 // The only case a 256-bit wide vector could be used is when the array 1508 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1509 // to work for sizes wider than 128, early check and fallback to memory. 1510 if (Size > 128 && EltSize != 256) 1511 return; 1512 1513 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { 1514 Class FieldLo, FieldHi; 1515 classify(AT->getElementType(), Offset, FieldLo, FieldHi); 1516 Lo = merge(Lo, FieldLo); 1517 Hi = merge(Hi, FieldHi); 1518 if (Lo == Memory || Hi == Memory) 1519 break; 1520 } 1521 1522 postMerge(Size, Lo, Hi); 1523 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification."); 1524 return; 1525 } 1526 1527 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1528 uint64_t Size = getContext().getTypeSize(Ty); 1529 1530 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1531 // than four eightbytes, ..., it has class MEMORY. 1532 if (Size > 256) 1533 return; 1534 1535 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial 1536 // copy constructor or a non-trivial destructor, it is passed by invisible 1537 // reference. 1538 if (getRecordArgABI(RT, CGT)) 1539 return; 1540 1541 const RecordDecl *RD = RT->getDecl(); 1542 1543 // Assume variable sized types are passed in memory. 1544 if (RD->hasFlexibleArrayMember()) 1545 return; 1546 1547 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 1548 1549 // Reset Lo class, this will be recomputed. 1550 Current = NoClass; 1551 1552 // If this is a C++ record, classify the bases first. 1553 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1554 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1555 e = CXXRD->bases_end(); i != e; ++i) { 1556 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1557 "Unexpected base class!"); 1558 const CXXRecordDecl *Base = 1559 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1560 1561 // Classify this field. 1562 // 1563 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a 1564 // single eightbyte, each is classified separately. Each eightbyte gets 1565 // initialized to class NO_CLASS. 1566 Class FieldLo, FieldHi; 1567 uint64_t Offset = 1568 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base)); 1569 classify(i->getType(), Offset, FieldLo, FieldHi); 1570 Lo = merge(Lo, FieldLo); 1571 Hi = merge(Hi, FieldHi); 1572 if (Lo == Memory || Hi == Memory) 1573 break; 1574 } 1575 } 1576 1577 // Classify the fields one at a time, merging the results. 1578 unsigned idx = 0; 1579 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1580 i != e; ++i, ++idx) { 1581 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1582 bool BitField = i->isBitField(); 1583 1584 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than 1585 // four eightbytes, or it contains unaligned fields, it has class MEMORY. 1586 // 1587 // The only case a 256-bit wide vector could be used is when the struct 1588 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1589 // to work for sizes wider than 128, early check and fallback to memory. 1590 // 1591 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) { 1592 Lo = Memory; 1593 return; 1594 } 1595 // Note, skip this test for bit-fields, see below. 1596 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) { 1597 Lo = Memory; 1598 return; 1599 } 1600 1601 // Classify this field. 1602 // 1603 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate 1604 // exceeds a single eightbyte, each is classified 1605 // separately. Each eightbyte gets initialized to class 1606 // NO_CLASS. 1607 Class FieldLo, FieldHi; 1608 1609 // Bit-fields require special handling, they do not force the 1610 // structure to be passed in memory even if unaligned, and 1611 // therefore they can straddle an eightbyte. 1612 if (BitField) { 1613 // Ignore padding bit-fields. 1614 if (i->isUnnamedBitfield()) 1615 continue; 1616 1617 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1618 uint64_t Size = i->getBitWidthValue(getContext()); 1619 1620 uint64_t EB_Lo = Offset / 64; 1621 uint64_t EB_Hi = (Offset + Size - 1) / 64; 1622 FieldLo = FieldHi = NoClass; 1623 if (EB_Lo) { 1624 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes."); 1625 FieldLo = NoClass; 1626 FieldHi = Integer; 1627 } else { 1628 FieldLo = Integer; 1629 FieldHi = EB_Hi ? Integer : NoClass; 1630 } 1631 } else 1632 classify(i->getType(), Offset, FieldLo, FieldHi); 1633 Lo = merge(Lo, FieldLo); 1634 Hi = merge(Hi, FieldHi); 1635 if (Lo == Memory || Hi == Memory) 1636 break; 1637 } 1638 1639 postMerge(Size, Lo, Hi); 1640 } 1641} 1642 1643ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const { 1644 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1645 // place naturally. 1646 if (!isAggregateTypeForABI(Ty)) { 1647 // Treat an enum type as its underlying type. 1648 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1649 Ty = EnumTy->getDecl()->getIntegerType(); 1650 1651 return (Ty->isPromotableIntegerType() ? 1652 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1653 } 1654 1655 return ABIArgInfo::getIndirect(0); 1656} 1657 1658bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const { 1659 if (const VectorType *VecTy = Ty->getAs<VectorType>()) { 1660 uint64_t Size = getContext().getTypeSize(VecTy); 1661 unsigned LargestVector = HasAVX ? 256 : 128; 1662 if (Size <= 64 || Size > LargestVector) 1663 return true; 1664 } 1665 1666 return false; 1667} 1668 1669ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty, 1670 unsigned freeIntRegs) const { 1671 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1672 // place naturally. 1673 // 1674 // This assumption is optimistic, as there could be free registers available 1675 // when we need to pass this argument in memory, and LLVM could try to pass 1676 // the argument in the free register. This does not seem to happen currently, 1677 // but this code would be much safer if we could mark the argument with 1678 // 'onstack'. See PR12193. 1679 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) { 1680 // Treat an enum type as its underlying type. 1681 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1682 Ty = EnumTy->getDecl()->getIntegerType(); 1683 1684 return (Ty->isPromotableIntegerType() ? 1685 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1686 } 1687 1688 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) 1689 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 1690 1691 // Compute the byval alignment. We specify the alignment of the byval in all 1692 // cases so that the mid-level optimizer knows the alignment of the byval. 1693 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U); 1694 1695 // Attempt to avoid passing indirect results using byval when possible. This 1696 // is important for good codegen. 1697 // 1698 // We do this by coercing the value into a scalar type which the backend can 1699 // handle naturally (i.e., without using byval). 1700 // 1701 // For simplicity, we currently only do this when we have exhausted all of the 1702 // free integer registers. Doing this when there are free integer registers 1703 // would require more care, as we would have to ensure that the coerced value 1704 // did not claim the unused register. That would require either reording the 1705 // arguments to the function (so that any subsequent inreg values came first), 1706 // or only doing this optimization when there were no following arguments that 1707 // might be inreg. 1708 // 1709 // We currently expect it to be rare (particularly in well written code) for 1710 // arguments to be passed on the stack when there are still free integer 1711 // registers available (this would typically imply large structs being passed 1712 // by value), so this seems like a fair tradeoff for now. 1713 // 1714 // We can revisit this if the backend grows support for 'onstack' parameter 1715 // attributes. See PR12193. 1716 if (freeIntRegs == 0) { 1717 uint64_t Size = getContext().getTypeSize(Ty); 1718 1719 // If this type fits in an eightbyte, coerce it into the matching integral 1720 // type, which will end up on the stack (with alignment 8). 1721 if (Align == 8 && Size <= 64) 1722 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 1723 Size)); 1724 } 1725 1726 return ABIArgInfo::getIndirect(Align); 1727} 1728 1729/// GetByteVectorType - The ABI specifies that a value should be passed in an 1730/// full vector XMM/YMM register. Pick an LLVM IR type that will be passed as a 1731/// vector register. 1732llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const { 1733 llvm::Type *IRType = CGT.ConvertType(Ty); 1734 1735 // Wrapper structs that just contain vectors are passed just like vectors, 1736 // strip them off if present. 1737 llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType); 1738 while (STy && STy->getNumElements() == 1) { 1739 IRType = STy->getElementType(0); 1740 STy = dyn_cast<llvm::StructType>(IRType); 1741 } 1742 1743 // If the preferred type is a 16-byte vector, prefer to pass it. 1744 if (llvm::VectorType *VT = dyn_cast<llvm::VectorType>(IRType)){ 1745 llvm::Type *EltTy = VT->getElementType(); 1746 unsigned BitWidth = VT->getBitWidth(); 1747 if ((BitWidth >= 128 && BitWidth <= 256) && 1748 (EltTy->isFloatTy() || EltTy->isDoubleTy() || 1749 EltTy->isIntegerTy(8) || EltTy->isIntegerTy(16) || 1750 EltTy->isIntegerTy(32) || EltTy->isIntegerTy(64) || 1751 EltTy->isIntegerTy(128))) 1752 return VT; 1753 } 1754 1755 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()), 2); 1756} 1757 1758/// BitsContainNoUserData - Return true if the specified [start,end) bit range 1759/// is known to either be off the end of the specified type or being in 1760/// alignment padding. The user type specified is known to be at most 128 bits 1761/// in size, and have passed through X86_64ABIInfo::classify with a successful 1762/// classification that put one of the two halves in the INTEGER class. 1763/// 1764/// It is conservatively correct to return false. 1765static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, 1766 unsigned EndBit, ASTContext &Context) { 1767 // If the bytes being queried are off the end of the type, there is no user 1768 // data hiding here. This handles analysis of builtins, vectors and other 1769 // types that don't contain interesting padding. 1770 unsigned TySize = (unsigned)Context.getTypeSize(Ty); 1771 if (TySize <= StartBit) 1772 return true; 1773 1774 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 1775 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); 1776 unsigned NumElts = (unsigned)AT->getSize().getZExtValue(); 1777 1778 // Check each element to see if the element overlaps with the queried range. 1779 for (unsigned i = 0; i != NumElts; ++i) { 1780 // If the element is after the span we care about, then we're done.. 1781 unsigned EltOffset = i*EltSize; 1782 if (EltOffset >= EndBit) break; 1783 1784 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0; 1785 if (!BitsContainNoUserData(AT->getElementType(), EltStart, 1786 EndBit-EltOffset, Context)) 1787 return false; 1788 } 1789 // If it overlaps no elements, then it is safe to process as padding. 1790 return true; 1791 } 1792 1793 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1794 const RecordDecl *RD = RT->getDecl(); 1795 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 1796 1797 // If this is a C++ record, check the bases first. 1798 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1799 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1800 e = CXXRD->bases_end(); i != e; ++i) { 1801 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1802 "Unexpected base class!"); 1803 const CXXRecordDecl *Base = 1804 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1805 1806 // If the base is after the span we care about, ignore it. 1807 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base)); 1808 if (BaseOffset >= EndBit) continue; 1809 1810 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0; 1811 if (!BitsContainNoUserData(i->getType(), BaseStart, 1812 EndBit-BaseOffset, Context)) 1813 return false; 1814 } 1815 } 1816 1817 // Verify that no field has data that overlaps the region of interest. Yes 1818 // this could be sped up a lot by being smarter about queried fields, 1819 // however we're only looking at structs up to 16 bytes, so we don't care 1820 // much. 1821 unsigned idx = 0; 1822 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1823 i != e; ++i, ++idx) { 1824 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx); 1825 1826 // If we found a field after the region we care about, then we're done. 1827 if (FieldOffset >= EndBit) break; 1828 1829 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0; 1830 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset, 1831 Context)) 1832 return false; 1833 } 1834 1835 // If nothing in this record overlapped the area of interest, then we're 1836 // clean. 1837 return true; 1838 } 1839 1840 return false; 1841} 1842 1843/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a 1844/// float member at the specified offset. For example, {int,{float}} has a 1845/// float at offset 4. It is conservatively correct for this routine to return 1846/// false. 1847static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, 1848 const llvm::DataLayout &TD) { 1849 // Base case if we find a float. 1850 if (IROffset == 0 && IRType->isFloatTy()) 1851 return true; 1852 1853 // If this is a struct, recurse into the field at the specified offset. 1854 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1855 const llvm::StructLayout *SL = TD.getStructLayout(STy); 1856 unsigned Elt = SL->getElementContainingOffset(IROffset); 1857 IROffset -= SL->getElementOffset(Elt); 1858 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD); 1859 } 1860 1861 // If this is an array, recurse into the field at the specified offset. 1862 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1863 llvm::Type *EltTy = ATy->getElementType(); 1864 unsigned EltSize = TD.getTypeAllocSize(EltTy); 1865 IROffset -= IROffset/EltSize*EltSize; 1866 return ContainsFloatAtOffset(EltTy, IROffset, TD); 1867 } 1868 1869 return false; 1870} 1871 1872 1873/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the 1874/// low 8 bytes of an XMM register, corresponding to the SSE class. 1875llvm::Type *X86_64ABIInfo:: 1876GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1877 QualType SourceTy, unsigned SourceOffset) const { 1878 // The only three choices we have are either double, <2 x float>, or float. We 1879 // pass as float if the last 4 bytes is just padding. This happens for 1880 // structs that contain 3 floats. 1881 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32, 1882 SourceOffset*8+64, getContext())) 1883 return llvm::Type::getFloatTy(getVMContext()); 1884 1885 // We want to pass as <2 x float> if the LLVM IR type contains a float at 1886 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the 1887 // case. 1888 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) && 1889 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())) 1890 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2); 1891 1892 return llvm::Type::getDoubleTy(getVMContext()); 1893} 1894 1895 1896/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in 1897/// an 8-byte GPR. This means that we either have a scalar or we are talking 1898/// about the high or low part of an up-to-16-byte struct. This routine picks 1899/// the best LLVM IR type to represent this, which may be i64 or may be anything 1900/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*, 1901/// etc). 1902/// 1903/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for 1904/// the source type. IROffset is an offset in bytes into the LLVM IR type that 1905/// the 8-byte value references. PrefType may be null. 1906/// 1907/// SourceTy is the source level type for the entire argument. SourceOffset is 1908/// an offset into this that we're processing (which is always either 0 or 8). 1909/// 1910llvm::Type *X86_64ABIInfo:: 1911GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1912 QualType SourceTy, unsigned SourceOffset) const { 1913 // If we're dealing with an un-offset LLVM IR type, then it means that we're 1914 // returning an 8-byte unit starting with it. See if we can safely use it. 1915 if (IROffset == 0) { 1916 // Pointers and int64's always fill the 8-byte unit. 1917 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) || 1918 IRType->isIntegerTy(64)) 1919 return IRType; 1920 1921 // If we have a 1/2/4-byte integer, we can use it only if the rest of the 1922 // goodness in the source type is just tail padding. This is allowed to 1923 // kick in for struct {double,int} on the int, but not on 1924 // struct{double,int,int} because we wouldn't return the second int. We 1925 // have to do this analysis on the source type because we can't depend on 1926 // unions being lowered a specific way etc. 1927 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) || 1928 IRType->isIntegerTy(32) || 1929 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) { 1930 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 : 1931 cast<llvm::IntegerType>(IRType)->getBitWidth(); 1932 1933 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth, 1934 SourceOffset*8+64, getContext())) 1935 return IRType; 1936 } 1937 } 1938 1939 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1940 // If this is a struct, recurse into the field at the specified offset. 1941 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy); 1942 if (IROffset < SL->getSizeInBytes()) { 1943 unsigned FieldIdx = SL->getElementContainingOffset(IROffset); 1944 IROffset -= SL->getElementOffset(FieldIdx); 1945 1946 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset, 1947 SourceTy, SourceOffset); 1948 } 1949 } 1950 1951 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1952 llvm::Type *EltTy = ATy->getElementType(); 1953 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); 1954 unsigned EltOffset = IROffset/EltSize*EltSize; 1955 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy, 1956 SourceOffset); 1957 } 1958 1959 // Okay, we don't have any better idea of what to pass, so we pass this in an 1960 // integer register that isn't too big to fit the rest of the struct. 1961 unsigned TySizeInBytes = 1962 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity(); 1963 1964 assert(TySizeInBytes != SourceOffset && "Empty field?"); 1965 1966 // It is always safe to classify this as an integer type up to i64 that 1967 // isn't larger than the structure. 1968 return llvm::IntegerType::get(getVMContext(), 1969 std::min(TySizeInBytes-SourceOffset, 8U)*8); 1970} 1971 1972 1973/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally 1974/// be used as elements of a two register pair to pass or return, return a 1975/// first class aggregate to represent them. For example, if the low part of 1976/// a by-value argument should be passed as i32* and the high part as float, 1977/// return {i32*, float}. 1978static llvm::Type * 1979GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, 1980 const llvm::DataLayout &TD) { 1981 // In order to correctly satisfy the ABI, we need to the high part to start 1982 // at offset 8. If the high and low parts we inferred are both 4-byte types 1983 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have 1984 // the second element at offset 8. Check for this: 1985 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo); 1986 unsigned HiAlign = TD.getABITypeAlignment(Hi); 1987 unsigned HiStart = llvm::DataLayout::RoundUpAlignment(LoSize, HiAlign); 1988 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!"); 1989 1990 // To handle this, we have to increase the size of the low part so that the 1991 // second element will start at an 8 byte offset. We can't increase the size 1992 // of the second element because it might make us access off the end of the 1993 // struct. 1994 if (HiStart != 8) { 1995 // There are only two sorts of types the ABI generation code can produce for 1996 // the low part of a pair that aren't 8 bytes in size: float or i8/i16/i32. 1997 // Promote these to a larger type. 1998 if (Lo->isFloatTy()) 1999 Lo = llvm::Type::getDoubleTy(Lo->getContext()); 2000 else { 2001 assert(Lo->isIntegerTy() && "Invalid/unknown lo type"); 2002 Lo = llvm::Type::getInt64Ty(Lo->getContext()); 2003 } 2004 } 2005 2006 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, NULL); 2007 2008 2009 // Verify that the second element is at an 8-byte offset. 2010 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 && 2011 "Invalid x86-64 argument pair!"); 2012 return Result; 2013} 2014 2015ABIArgInfo X86_64ABIInfo:: 2016classifyReturnType(QualType RetTy) const { 2017 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the 2018 // classification algorithm. 2019 X86_64ABIInfo::Class Lo, Hi; 2020 classify(RetTy, 0, Lo, Hi); 2021 2022 // Check some invariants. 2023 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2024 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2025 2026 llvm::Type *ResType = 0; 2027 switch (Lo) { 2028 case NoClass: 2029 if (Hi == NoClass) 2030 return ABIArgInfo::getIgnore(); 2031 // If the low part is just padding, it takes no register, leave ResType 2032 // null. 2033 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2034 "Unknown missing lo part"); 2035 break; 2036 2037 case SSEUp: 2038 case X87Up: 2039 llvm_unreachable("Invalid classification for lo word."); 2040 2041 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via 2042 // hidden argument. 2043 case Memory: 2044 return getIndirectReturnResult(RetTy); 2045 2046 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next 2047 // available register of the sequence %rax, %rdx is used. 2048 case Integer: 2049 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2050 2051 // If we have a sign or zero extended integer, make sure to return Extend 2052 // so that the parameter gets the right LLVM IR attributes. 2053 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2054 // Treat an enum type as its underlying type. 2055 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 2056 RetTy = EnumTy->getDecl()->getIntegerType(); 2057 2058 if (RetTy->isIntegralOrEnumerationType() && 2059 RetTy->isPromotableIntegerType()) 2060 return ABIArgInfo::getExtend(); 2061 } 2062 break; 2063 2064 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next 2065 // available SSE register of the sequence %xmm0, %xmm1 is used. 2066 case SSE: 2067 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2068 break; 2069 2070 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is 2071 // returned on the X87 stack in %st0 as 80-bit x87 number. 2072 case X87: 2073 ResType = llvm::Type::getX86_FP80Ty(getVMContext()); 2074 break; 2075 2076 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real 2077 // part of the value is returned in %st0 and the imaginary part in 2078 // %st1. 2079 case ComplexX87: 2080 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification."); 2081 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()), 2082 llvm::Type::getX86_FP80Ty(getVMContext()), 2083 NULL); 2084 break; 2085 } 2086 2087 llvm::Type *HighPart = 0; 2088 switch (Hi) { 2089 // Memory was handled previously and X87 should 2090 // never occur as a hi class. 2091 case Memory: 2092 case X87: 2093 llvm_unreachable("Invalid classification for hi word."); 2094 2095 case ComplexX87: // Previously handled. 2096 case NoClass: 2097 break; 2098 2099 case Integer: 2100 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2101 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2102 return ABIArgInfo::getDirect(HighPart, 8); 2103 break; 2104 case SSE: 2105 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2106 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2107 return ABIArgInfo::getDirect(HighPart, 8); 2108 break; 2109 2110 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte 2111 // is passed in the next available eightbyte chunk if the last used 2112 // vector register. 2113 // 2114 // SSEUP should always be preceded by SSE, just widen. 2115 case SSEUp: 2116 assert(Lo == SSE && "Unexpected SSEUp classification."); 2117 ResType = GetByteVectorType(RetTy); 2118 break; 2119 2120 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is 2121 // returned together with the previous X87 value in %st0. 2122 case X87Up: 2123 // If X87Up is preceded by X87, we don't need to do 2124 // anything. However, in some cases with unions it may not be 2125 // preceded by X87. In such situations we follow gcc and pass the 2126 // extra bits in an SSE reg. 2127 if (Lo != X87) { 2128 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2129 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2130 return ABIArgInfo::getDirect(HighPart, 8); 2131 } 2132 break; 2133 } 2134 2135 // If a high part was specified, merge it together with the low part. It is 2136 // known to pass in the high eightbyte of the result. We do this by forming a 2137 // first class struct aggregate with the high and low part: {low, high} 2138 if (HighPart) 2139 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2140 2141 return ABIArgInfo::getDirect(ResType); 2142} 2143 2144ABIArgInfo X86_64ABIInfo::classifyArgumentType( 2145 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE) 2146 const 2147{ 2148 X86_64ABIInfo::Class Lo, Hi; 2149 classify(Ty, 0, Lo, Hi); 2150 2151 // Check some invariants. 2152 // FIXME: Enforce these by construction. 2153 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2154 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2155 2156 neededInt = 0; 2157 neededSSE = 0; 2158 llvm::Type *ResType = 0; 2159 switch (Lo) { 2160 case NoClass: 2161 if (Hi == NoClass) 2162 return ABIArgInfo::getIgnore(); 2163 // If the low part is just padding, it takes no register, leave ResType 2164 // null. 2165 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2166 "Unknown missing lo part"); 2167 break; 2168 2169 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument 2170 // on the stack. 2171 case Memory: 2172 2173 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or 2174 // COMPLEX_X87, it is passed in memory. 2175 case X87: 2176 case ComplexX87: 2177 if (getRecordArgABI(Ty, CGT) == CGCXXABI::RAA_Indirect) 2178 ++neededInt; 2179 return getIndirectResult(Ty, freeIntRegs); 2180 2181 case SSEUp: 2182 case X87Up: 2183 llvm_unreachable("Invalid classification for lo word."); 2184 2185 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next 2186 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8 2187 // and %r9 is used. 2188 case Integer: 2189 ++neededInt; 2190 2191 // Pick an 8-byte type based on the preferred type. 2192 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0); 2193 2194 // If we have a sign or zero extended integer, make sure to return Extend 2195 // so that the parameter gets the right LLVM IR attributes. 2196 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2197 // Treat an enum type as its underlying type. 2198 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2199 Ty = EnumTy->getDecl()->getIntegerType(); 2200 2201 if (Ty->isIntegralOrEnumerationType() && 2202 Ty->isPromotableIntegerType()) 2203 return ABIArgInfo::getExtend(); 2204 } 2205 2206 break; 2207 2208 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next 2209 // available SSE register is used, the registers are taken in the 2210 // order from %xmm0 to %xmm7. 2211 case SSE: { 2212 llvm::Type *IRType = CGT.ConvertType(Ty); 2213 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0); 2214 ++neededSSE; 2215 break; 2216 } 2217 } 2218 2219 llvm::Type *HighPart = 0; 2220 switch (Hi) { 2221 // Memory was handled previously, ComplexX87 and X87 should 2222 // never occur as hi classes, and X87Up must be preceded by X87, 2223 // which is passed in memory. 2224 case Memory: 2225 case X87: 2226 case ComplexX87: 2227 llvm_unreachable("Invalid classification for hi word."); 2228 2229 case NoClass: break; 2230 2231 case Integer: 2232 ++neededInt; 2233 // Pick an 8-byte type based on the preferred type. 2234 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2235 2236 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2237 return ABIArgInfo::getDirect(HighPart, 8); 2238 break; 2239 2240 // X87Up generally doesn't occur here (long double is passed in 2241 // memory), except in situations involving unions. 2242 case X87Up: 2243 case SSE: 2244 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2245 2246 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2247 return ABIArgInfo::getDirect(HighPart, 8); 2248 2249 ++neededSSE; 2250 break; 2251 2252 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the 2253 // eightbyte is passed in the upper half of the last used SSE 2254 // register. This only happens when 128-bit vectors are passed. 2255 case SSEUp: 2256 assert(Lo == SSE && "Unexpected SSEUp classification"); 2257 ResType = GetByteVectorType(Ty); 2258 break; 2259 } 2260 2261 // If a high part was specified, merge it together with the low part. It is 2262 // known to pass in the high eightbyte of the result. We do this by forming a 2263 // first class struct aggregate with the high and low part: {low, high} 2264 if (HighPart) 2265 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2266 2267 return ABIArgInfo::getDirect(ResType); 2268} 2269 2270void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2271 2272 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2273 2274 // Keep track of the number of assigned registers. 2275 unsigned freeIntRegs = 6, freeSSERegs = 8; 2276 2277 // If the return value is indirect, then the hidden argument is consuming one 2278 // integer register. 2279 if (FI.getReturnInfo().isIndirect()) 2280 --freeIntRegs; 2281 2282 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers 2283 // get assigned (in left-to-right order) for passing as follows... 2284 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2285 it != ie; ++it) { 2286 unsigned neededInt, neededSSE; 2287 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt, 2288 neededSSE); 2289 2290 // AMD64-ABI 3.2.3p3: If there are no registers available for any 2291 // eightbyte of an argument, the whole argument is passed on the 2292 // stack. If registers have already been assigned for some 2293 // eightbytes of such an argument, the assignments get reverted. 2294 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) { 2295 freeIntRegs -= neededInt; 2296 freeSSERegs -= neededSSE; 2297 } else { 2298 it->info = getIndirectResult(it->type, freeIntRegs); 2299 } 2300 } 2301} 2302 2303static llvm::Value *EmitVAArgFromMemory(llvm::Value *VAListAddr, 2304 QualType Ty, 2305 CodeGenFunction &CGF) { 2306 llvm::Value *overflow_arg_area_p = 2307 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p"); 2308 llvm::Value *overflow_arg_area = 2309 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area"); 2310 2311 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16 2312 // byte boundary if alignment needed by type exceeds 8 byte boundary. 2313 // It isn't stated explicitly in the standard, but in practice we use 2314 // alignment greater than 16 where necessary. 2315 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8; 2316 if (Align > 8) { 2317 // overflow_arg_area = (overflow_arg_area + align - 1) & -align; 2318 llvm::Value *Offset = 2319 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); 2320 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); 2321 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, 2322 CGF.Int64Ty); 2323 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align); 2324 overflow_arg_area = 2325 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 2326 overflow_arg_area->getType(), 2327 "overflow_arg_area.align"); 2328 } 2329 2330 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area. 2331 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2332 llvm::Value *Res = 2333 CGF.Builder.CreateBitCast(overflow_arg_area, 2334 llvm::PointerType::getUnqual(LTy)); 2335 2336 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to: 2337 // l->overflow_arg_area + sizeof(type). 2338 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to 2339 // an 8 byte boundary. 2340 2341 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8; 2342 llvm::Value *Offset = 2343 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7); 2344 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset, 2345 "overflow_arg_area.next"); 2346 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p); 2347 2348 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type. 2349 return Res; 2350} 2351 2352llvm::Value *X86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2353 CodeGenFunction &CGF) const { 2354 // Assume that va_list type is correct; should be pointer to LLVM type: 2355 // struct { 2356 // i32 gp_offset; 2357 // i32 fp_offset; 2358 // i8* overflow_arg_area; 2359 // i8* reg_save_area; 2360 // }; 2361 unsigned neededInt, neededSSE; 2362 2363 Ty = CGF.getContext().getCanonicalType(Ty); 2364 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE); 2365 2366 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed 2367 // in the registers. If not go to step 7. 2368 if (!neededInt && !neededSSE) 2369 return EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2370 2371 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of 2372 // general purpose registers needed to pass type and num_fp to hold 2373 // the number of floating point registers needed. 2374 2375 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into 2376 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or 2377 // l->fp_offset > 304 - num_fp * 16 go to step 7. 2378 // 2379 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of 2380 // register save space). 2381 2382 llvm::Value *InRegs = 0; 2383 llvm::Value *gp_offset_p = 0, *gp_offset = 0; 2384 llvm::Value *fp_offset_p = 0, *fp_offset = 0; 2385 if (neededInt) { 2386 gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p"); 2387 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset"); 2388 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8); 2389 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp"); 2390 } 2391 2392 if (neededSSE) { 2393 fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p"); 2394 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset"); 2395 llvm::Value *FitsInFP = 2396 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16); 2397 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp"); 2398 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP; 2399 } 2400 2401 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 2402 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 2403 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 2404 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 2405 2406 // Emit code to load the value if it was passed in registers. 2407 2408 CGF.EmitBlock(InRegBlock); 2409 2410 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with 2411 // an offset of l->gp_offset and/or l->fp_offset. This may require 2412 // copying to a temporary location in case the parameter is passed 2413 // in different register classes or requires an alignment greater 2414 // than 8 for general purpose registers and 16 for XMM registers. 2415 // 2416 // FIXME: This really results in shameful code when we end up needing to 2417 // collect arguments from different places; often what should result in a 2418 // simple assembling of a structure from scattered addresses has many more 2419 // loads than necessary. Can we clean this up? 2420 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2421 llvm::Value *RegAddr = 2422 CGF.Builder.CreateLoad(CGF.Builder.CreateStructGEP(VAListAddr, 3), 2423 "reg_save_area"); 2424 if (neededInt && neededSSE) { 2425 // FIXME: Cleanup. 2426 assert(AI.isDirect() && "Unexpected ABI info for mixed regs"); 2427 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType()); 2428 llvm::Value *Tmp = CGF.CreateTempAlloca(ST); 2429 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs"); 2430 llvm::Type *TyLo = ST->getElementType(0); 2431 llvm::Type *TyHi = ST->getElementType(1); 2432 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && 2433 "Unexpected ABI info for mixed regs"); 2434 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo); 2435 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi); 2436 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2437 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2438 llvm::Value *RegLoAddr = TyLo->isFloatingPointTy() ? FPAddr : GPAddr; 2439 llvm::Value *RegHiAddr = TyLo->isFloatingPointTy() ? GPAddr : FPAddr; 2440 llvm::Value *V = 2441 CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegLoAddr, PTyLo)); 2442 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2443 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegHiAddr, PTyHi)); 2444 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2445 2446 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2447 llvm::PointerType::getUnqual(LTy)); 2448 } else if (neededInt) { 2449 RegAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2450 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2451 llvm::PointerType::getUnqual(LTy)); 2452 } else if (neededSSE == 1) { 2453 RegAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2454 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2455 llvm::PointerType::getUnqual(LTy)); 2456 } else { 2457 assert(neededSSE == 2 && "Invalid number of needed registers!"); 2458 // SSE registers are spaced 16 bytes apart in the register save 2459 // area, we need to collect the two eightbytes together. 2460 llvm::Value *RegAddrLo = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2461 llvm::Value *RegAddrHi = CGF.Builder.CreateConstGEP1_32(RegAddrLo, 16); 2462 llvm::Type *DoubleTy = CGF.DoubleTy; 2463 llvm::Type *DblPtrTy = 2464 llvm::PointerType::getUnqual(DoubleTy); 2465 llvm::StructType *ST = llvm::StructType::get(DoubleTy, 2466 DoubleTy, NULL); 2467 llvm::Value *V, *Tmp = CGF.CreateTempAlloca(ST); 2468 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrLo, 2469 DblPtrTy)); 2470 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2471 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrHi, 2472 DblPtrTy)); 2473 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2474 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2475 llvm::PointerType::getUnqual(LTy)); 2476 } 2477 2478 // AMD64-ABI 3.5.7p5: Step 5. Set: 2479 // l->gp_offset = l->gp_offset + num_gp * 8 2480 // l->fp_offset = l->fp_offset + num_fp * 16. 2481 if (neededInt) { 2482 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8); 2483 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset), 2484 gp_offset_p); 2485 } 2486 if (neededSSE) { 2487 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16); 2488 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset), 2489 fp_offset_p); 2490 } 2491 CGF.EmitBranch(ContBlock); 2492 2493 // Emit code to load the value if it was passed in memory. 2494 2495 CGF.EmitBlock(InMemBlock); 2496 llvm::Value *MemAddr = EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2497 2498 // Return the appropriate result. 2499 2500 CGF.EmitBlock(ContBlock); 2501 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(RegAddr->getType(), 2, 2502 "vaarg.addr"); 2503 ResAddr->addIncoming(RegAddr, InRegBlock); 2504 ResAddr->addIncoming(MemAddr, InMemBlock); 2505 return ResAddr; 2506} 2507 2508ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, bool IsReturnType) const { 2509 2510 if (Ty->isVoidType()) 2511 return ABIArgInfo::getIgnore(); 2512 2513 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2514 Ty = EnumTy->getDecl()->getIntegerType(); 2515 2516 uint64_t Size = getContext().getTypeSize(Ty); 2517 2518 if (const RecordType *RT = Ty->getAs<RecordType>()) { 2519 if (IsReturnType) { 2520 if (isRecordReturnIndirect(RT, CGT)) 2521 return ABIArgInfo::getIndirect(0, false); 2522 } else { 2523 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, CGT)) 2524 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 2525 } 2526 2527 if (RT->getDecl()->hasFlexibleArrayMember()) 2528 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2529 2530 // FIXME: mingw-w64-gcc emits 128-bit struct as i128 2531 if (Size == 128 && getTarget().getTriple().getOS() == llvm::Triple::MinGW32) 2532 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2533 Size)); 2534 2535 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is 2536 // not 1, 2, 4, or 8 bytes, must be passed by reference." 2537 if (Size <= 64 && 2538 (Size & (Size - 1)) == 0) 2539 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2540 Size)); 2541 2542 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2543 } 2544 2545 if (Ty->isPromotableIntegerType()) 2546 return ABIArgInfo::getExtend(); 2547 2548 return ABIArgInfo::getDirect(); 2549} 2550 2551void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2552 2553 QualType RetTy = FI.getReturnType(); 2554 FI.getReturnInfo() = classify(RetTy, true); 2555 2556 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2557 it != ie; ++it) 2558 it->info = classify(it->type, false); 2559} 2560 2561llvm::Value *WinX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2562 CodeGenFunction &CGF) const { 2563 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2564 2565 CGBuilderTy &Builder = CGF.Builder; 2566 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 2567 "ap"); 2568 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2569 llvm::Type *PTy = 2570 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2571 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 2572 2573 uint64_t Offset = 2574 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 8); 2575 llvm::Value *NextAddr = 2576 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 2577 "ap.next"); 2578 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2579 2580 return AddrTyped; 2581} 2582 2583namespace { 2584 2585class NaClX86_64ABIInfo : public ABIInfo { 2586 public: 2587 NaClX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2588 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, HasAVX) {} 2589 virtual void computeInfo(CGFunctionInfo &FI) const; 2590 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2591 CodeGenFunction &CGF) const; 2592 private: 2593 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 2594 X86_64ABIInfo NInfo; // Used for everything else. 2595}; 2596 2597class NaClX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 2598 public: 2599 NaClX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2600 : TargetCodeGenInfo(new NaClX86_64ABIInfo(CGT, HasAVX)) {} 2601}; 2602 2603} 2604 2605void NaClX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2606 if (FI.getASTCallingConvention() == CC_PnaclCall) 2607 PInfo.computeInfo(FI); 2608 else 2609 NInfo.computeInfo(FI); 2610} 2611 2612llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2613 CodeGenFunction &CGF) const { 2614 // Always use the native convention; calling pnacl-style varargs functions 2615 // is unuspported. 2616 return NInfo.EmitVAArg(VAListAddr, Ty, CGF); 2617} 2618 2619 2620// PowerPC-32 2621 2622namespace { 2623class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2624public: 2625 PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2626 2627 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2628 // This is recovered from gcc output. 2629 return 1; // r1 is the dedicated stack pointer 2630 } 2631 2632 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2633 llvm::Value *Address) const; 2634}; 2635 2636} 2637 2638bool 2639PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2640 llvm::Value *Address) const { 2641 // This is calculated from the LLVM and GCC tables and verified 2642 // against gcc output. AFAIK all ABIs use the same encoding. 2643 2644 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2645 2646 llvm::IntegerType *i8 = CGF.Int8Ty; 2647 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2648 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2649 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2650 2651 // 0-31: r0-31, the 4-byte general-purpose registers 2652 AssignToArrayRange(Builder, Address, Four8, 0, 31); 2653 2654 // 32-63: fp0-31, the 8-byte floating-point registers 2655 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2656 2657 // 64-76 are various 4-byte special-purpose registers: 2658 // 64: mq 2659 // 65: lr 2660 // 66: ctr 2661 // 67: ap 2662 // 68-75 cr0-7 2663 // 76: xer 2664 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2665 2666 // 77-108: v0-31, the 16-byte vector registers 2667 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2668 2669 // 109: vrsave 2670 // 110: vscr 2671 // 111: spe_acc 2672 // 112: spefscr 2673 // 113: sfp 2674 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2675 2676 return false; 2677} 2678 2679// PowerPC-64 2680 2681namespace { 2682/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information. 2683class PPC64_SVR4_ABIInfo : public DefaultABIInfo { 2684 2685public: 2686 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 2687 2688 bool isPromotableTypeForABI(QualType Ty) const; 2689 2690 ABIArgInfo classifyReturnType(QualType RetTy) const; 2691 ABIArgInfo classifyArgumentType(QualType Ty) const; 2692 2693 // TODO: We can add more logic to computeInfo to improve performance. 2694 // Example: For aggregate arguments that fit in a register, we could 2695 // use getDirectInReg (as is done below for structs containing a single 2696 // floating-point value) to avoid pushing them to memory on function 2697 // entry. This would require changing the logic in PPCISelLowering 2698 // when lowering the parameters in the caller and args in the callee. 2699 virtual void computeInfo(CGFunctionInfo &FI) const { 2700 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2701 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2702 it != ie; ++it) { 2703 // We rely on the default argument classification for the most part. 2704 // One exception: An aggregate containing a single floating-point 2705 // item must be passed in a register if one is available. 2706 const Type *T = isSingleElementStruct(it->type, getContext()); 2707 if (T) { 2708 const BuiltinType *BT = T->getAs<BuiltinType>(); 2709 if (BT && BT->isFloatingPoint()) { 2710 QualType QT(T, 0); 2711 it->info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT)); 2712 continue; 2713 } 2714 } 2715 it->info = classifyArgumentType(it->type); 2716 } 2717 } 2718 2719 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, 2720 QualType Ty, 2721 CodeGenFunction &CGF) const; 2722}; 2723 2724class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo { 2725public: 2726 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT) 2727 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT)) {} 2728 2729 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2730 // This is recovered from gcc output. 2731 return 1; // r1 is the dedicated stack pointer 2732 } 2733 2734 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2735 llvm::Value *Address) const; 2736}; 2737 2738class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2739public: 2740 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2741 2742 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2743 // This is recovered from gcc output. 2744 return 1; // r1 is the dedicated stack pointer 2745 } 2746 2747 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2748 llvm::Value *Address) const; 2749}; 2750 2751} 2752 2753// Return true if the ABI requires Ty to be passed sign- or zero- 2754// extended to 64 bits. 2755bool 2756PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const { 2757 // Treat an enum type as its underlying type. 2758 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2759 Ty = EnumTy->getDecl()->getIntegerType(); 2760 2761 // Promotable integer types are required to be promoted by the ABI. 2762 if (Ty->isPromotableIntegerType()) 2763 return true; 2764 2765 // In addition to the usual promotable integer types, we also need to 2766 // extend all 32-bit types, since the ABI requires promotion to 64 bits. 2767 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 2768 switch (BT->getKind()) { 2769 case BuiltinType::Int: 2770 case BuiltinType::UInt: 2771 return true; 2772 default: 2773 break; 2774 } 2775 2776 return false; 2777} 2778 2779ABIArgInfo 2780PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const { 2781 if (Ty->isAnyComplexType()) 2782 return ABIArgInfo::getDirect(); 2783 2784 if (isAggregateTypeForABI(Ty)) { 2785 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) 2786 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 2787 2788 return ABIArgInfo::getIndirect(0); 2789 } 2790 2791 return (isPromotableTypeForABI(Ty) ? 2792 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 2793} 2794 2795ABIArgInfo 2796PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const { 2797 if (RetTy->isVoidType()) 2798 return ABIArgInfo::getIgnore(); 2799 2800 if (RetTy->isAnyComplexType()) 2801 return ABIArgInfo::getDirect(); 2802 2803 if (isAggregateTypeForABI(RetTy)) 2804 return ABIArgInfo::getIndirect(0); 2805 2806 return (isPromotableTypeForABI(RetTy) ? 2807 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 2808} 2809 2810// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine. 2811llvm::Value *PPC64_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr, 2812 QualType Ty, 2813 CodeGenFunction &CGF) const { 2814 llvm::Type *BP = CGF.Int8PtrTy; 2815 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2816 2817 CGBuilderTy &Builder = CGF.Builder; 2818 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 2819 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2820 2821 // Update the va_list pointer. The pointer should be bumped by the 2822 // size of the object. We can trust getTypeSize() except for a complex 2823 // type whose base type is smaller than a doubleword. For these, the 2824 // size of the object is 16 bytes; see below for further explanation. 2825 unsigned SizeInBytes = CGF.getContext().getTypeSize(Ty) / 8; 2826 QualType BaseTy; 2827 unsigned CplxBaseSize = 0; 2828 2829 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) { 2830 BaseTy = CTy->getElementType(); 2831 CplxBaseSize = CGF.getContext().getTypeSize(BaseTy) / 8; 2832 if (CplxBaseSize < 8) 2833 SizeInBytes = 16; 2834 } 2835 2836 unsigned Offset = llvm::RoundUpToAlignment(SizeInBytes, 8); 2837 llvm::Value *NextAddr = 2838 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), 2839 "ap.next"); 2840 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2841 2842 // If we have a complex type and the base type is smaller than 8 bytes, 2843 // the ABI calls for the real and imaginary parts to be right-adjusted 2844 // in separate doublewords. However, Clang expects us to produce a 2845 // pointer to a structure with the two parts packed tightly. So generate 2846 // loads of the real and imaginary parts relative to the va_list pointer, 2847 // and store them to a temporary structure. 2848 if (CplxBaseSize && CplxBaseSize < 8) { 2849 llvm::Value *RealAddr = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2850 llvm::Value *ImagAddr = RealAddr; 2851 RealAddr = Builder.CreateAdd(RealAddr, Builder.getInt64(8 - CplxBaseSize)); 2852 ImagAddr = Builder.CreateAdd(ImagAddr, Builder.getInt64(16 - CplxBaseSize)); 2853 llvm::Type *PBaseTy = llvm::PointerType::getUnqual(CGF.ConvertType(BaseTy)); 2854 RealAddr = Builder.CreateIntToPtr(RealAddr, PBaseTy); 2855 ImagAddr = Builder.CreateIntToPtr(ImagAddr, PBaseTy); 2856 llvm::Value *Real = Builder.CreateLoad(RealAddr, false, ".vareal"); 2857 llvm::Value *Imag = Builder.CreateLoad(ImagAddr, false, ".vaimag"); 2858 llvm::Value *Ptr = CGF.CreateTempAlloca(CGT.ConvertTypeForMem(Ty), 2859 "vacplx"); 2860 llvm::Value *RealPtr = Builder.CreateStructGEP(Ptr, 0, ".real"); 2861 llvm::Value *ImagPtr = Builder.CreateStructGEP(Ptr, 1, ".imag"); 2862 Builder.CreateStore(Real, RealPtr, false); 2863 Builder.CreateStore(Imag, ImagPtr, false); 2864 return Ptr; 2865 } 2866 2867 // If the argument is smaller than 8 bytes, it is right-adjusted in 2868 // its doubleword slot. Adjust the pointer to pick it up from the 2869 // correct offset. 2870 if (SizeInBytes < 8) { 2871 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2872 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(8 - SizeInBytes)); 2873 Addr = Builder.CreateIntToPtr(AddrAsInt, BP); 2874 } 2875 2876 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2877 return Builder.CreateBitCast(Addr, PTy); 2878} 2879 2880static bool 2881PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2882 llvm::Value *Address) { 2883 // This is calculated from the LLVM and GCC tables and verified 2884 // against gcc output. AFAIK all ABIs use the same encoding. 2885 2886 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2887 2888 llvm::IntegerType *i8 = CGF.Int8Ty; 2889 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2890 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2891 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2892 2893 // 0-31: r0-31, the 8-byte general-purpose registers 2894 AssignToArrayRange(Builder, Address, Eight8, 0, 31); 2895 2896 // 32-63: fp0-31, the 8-byte floating-point registers 2897 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2898 2899 // 64-76 are various 4-byte special-purpose registers: 2900 // 64: mq 2901 // 65: lr 2902 // 66: ctr 2903 // 67: ap 2904 // 68-75 cr0-7 2905 // 76: xer 2906 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2907 2908 // 77-108: v0-31, the 16-byte vector registers 2909 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2910 2911 // 109: vrsave 2912 // 110: vscr 2913 // 111: spe_acc 2914 // 112: spefscr 2915 // 113: sfp 2916 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2917 2918 return false; 2919} 2920 2921bool 2922PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable( 2923 CodeGen::CodeGenFunction &CGF, 2924 llvm::Value *Address) const { 2925 2926 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 2927} 2928 2929bool 2930PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2931 llvm::Value *Address) const { 2932 2933 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 2934} 2935 2936//===----------------------------------------------------------------------===// 2937// ARM ABI Implementation 2938//===----------------------------------------------------------------------===// 2939 2940namespace { 2941 2942class ARMABIInfo : public ABIInfo { 2943public: 2944 enum ABIKind { 2945 APCS = 0, 2946 AAPCS = 1, 2947 AAPCS_VFP 2948 }; 2949 2950private: 2951 ABIKind Kind; 2952 2953public: 2954 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) : ABIInfo(CGT), Kind(_Kind) { 2955 setRuntimeCC(); 2956 } 2957 2958 bool isEABI() const { 2959 StringRef Env = getTarget().getTriple().getEnvironmentName(); 2960 return (Env == "gnueabi" || Env == "eabi" || 2961 Env == "android" || Env == "androideabi"); 2962 } 2963 2964private: 2965 ABIKind getABIKind() const { return Kind; } 2966 2967 ABIArgInfo classifyReturnType(QualType RetTy) const; 2968 ABIArgInfo classifyArgumentType(QualType RetTy, int *VFPRegs, 2969 unsigned &AllocatedVFP, 2970 bool &IsHA) const; 2971 bool isIllegalVectorType(QualType Ty) const; 2972 2973 virtual void computeInfo(CGFunctionInfo &FI) const; 2974 2975 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2976 CodeGenFunction &CGF) const; 2977 2978 llvm::CallingConv::ID getLLVMDefaultCC() const; 2979 llvm::CallingConv::ID getABIDefaultCC() const; 2980 void setRuntimeCC(); 2981}; 2982 2983class ARMTargetCodeGenInfo : public TargetCodeGenInfo { 2984public: 2985 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) 2986 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {} 2987 2988 const ARMABIInfo &getABIInfo() const { 2989 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo()); 2990 } 2991 2992 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2993 return 13; 2994 } 2995 2996 StringRef getARCRetainAutoreleasedReturnValueMarker() const { 2997 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue"; 2998 } 2999 3000 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3001 llvm::Value *Address) const { 3002 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 3003 3004 // 0-15 are the 16 integer registers. 3005 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15); 3006 return false; 3007 } 3008 3009 unsigned getSizeOfUnwindException() const { 3010 if (getABIInfo().isEABI()) return 88; 3011 return TargetCodeGenInfo::getSizeOfUnwindException(); 3012 } 3013}; 3014 3015} 3016 3017void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3018 // To correctly handle Homogeneous Aggregate, we need to keep track of the 3019 // VFP registers allocated so far. 3020 // C.1.vfp If the argument is a VFP CPRC and there are sufficient consecutive 3021 // VFP registers of the appropriate type unallocated then the argument is 3022 // allocated to the lowest-numbered sequence of such registers. 3023 // C.2.vfp If the argument is a VFP CPRC then any VFP registers that are 3024 // unallocated are marked as unavailable. 3025 unsigned AllocatedVFP = 0; 3026 int VFPRegs[16] = { 0 }; 3027 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 3028 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3029 it != ie; ++it) { 3030 unsigned PreAllocation = AllocatedVFP; 3031 bool IsHA = false; 3032 // 6.1.2.3 There is one VFP co-processor register class using registers 3033 // s0-s15 (d0-d7) for passing arguments. 3034 const unsigned NumVFPs = 16; 3035 it->info = classifyArgumentType(it->type, VFPRegs, AllocatedVFP, IsHA); 3036 // If we do not have enough VFP registers for the HA, any VFP registers 3037 // that are unallocated are marked as unavailable. To achieve this, we add 3038 // padding of (NumVFPs - PreAllocation) floats. 3039 if (IsHA && AllocatedVFP > NumVFPs && PreAllocation < NumVFPs) { 3040 llvm::Type *PaddingTy = llvm::ArrayType::get( 3041 llvm::Type::getFloatTy(getVMContext()), NumVFPs - PreAllocation); 3042 it->info = ABIArgInfo::getExpandWithPadding(false, PaddingTy); 3043 } 3044 } 3045 3046 // Always honor user-specified calling convention. 3047 if (FI.getCallingConvention() != llvm::CallingConv::C) 3048 return; 3049 3050 llvm::CallingConv::ID cc = getRuntimeCC(); 3051 if (cc != llvm::CallingConv::C) 3052 FI.setEffectiveCallingConvention(cc); 3053} 3054 3055/// Return the default calling convention that LLVM will use. 3056llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const { 3057 // The default calling convention that LLVM will infer. 3058 if (getTarget().getTriple().getEnvironmentName()=="gnueabihf") 3059 return llvm::CallingConv::ARM_AAPCS_VFP; 3060 else if (isEABI()) 3061 return llvm::CallingConv::ARM_AAPCS; 3062 else 3063 return llvm::CallingConv::ARM_APCS; 3064} 3065 3066/// Return the calling convention that our ABI would like us to use 3067/// as the C calling convention. 3068llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const { 3069 switch (getABIKind()) { 3070 case APCS: return llvm::CallingConv::ARM_APCS; 3071 case AAPCS: return llvm::CallingConv::ARM_AAPCS; 3072 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP; 3073 } 3074 llvm_unreachable("bad ABI kind"); 3075} 3076 3077void ARMABIInfo::setRuntimeCC() { 3078 assert(getRuntimeCC() == llvm::CallingConv::C); 3079 3080 // Don't muddy up the IR with a ton of explicit annotations if 3081 // they'd just match what LLVM will infer from the triple. 3082 llvm::CallingConv::ID abiCC = getABIDefaultCC(); 3083 if (abiCC != getLLVMDefaultCC()) 3084 RuntimeCC = abiCC; 3085} 3086 3087/// isHomogeneousAggregate - Return true if a type is an AAPCS-VFP homogeneous 3088/// aggregate. If HAMembers is non-null, the number of base elements 3089/// contained in the type is returned through it; this is used for the 3090/// recursive calls that check aggregate component types. 3091static bool isHomogeneousAggregate(QualType Ty, const Type *&Base, 3092 ASTContext &Context, 3093 uint64_t *HAMembers = 0) { 3094 uint64_t Members = 0; 3095 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 3096 if (!isHomogeneousAggregate(AT->getElementType(), Base, Context, &Members)) 3097 return false; 3098 Members *= AT->getSize().getZExtValue(); 3099 } else if (const RecordType *RT = Ty->getAs<RecordType>()) { 3100 const RecordDecl *RD = RT->getDecl(); 3101 if (RD->hasFlexibleArrayMember()) 3102 return false; 3103 3104 Members = 0; 3105 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3106 i != e; ++i) { 3107 const FieldDecl *FD = *i; 3108 uint64_t FldMembers; 3109 if (!isHomogeneousAggregate(FD->getType(), Base, Context, &FldMembers)) 3110 return false; 3111 3112 Members = (RD->isUnion() ? 3113 std::max(Members, FldMembers) : Members + FldMembers); 3114 } 3115 } else { 3116 Members = 1; 3117 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 3118 Members = 2; 3119 Ty = CT->getElementType(); 3120 } 3121 3122 // Homogeneous aggregates for AAPCS-VFP must have base types of float, 3123 // double, or 64-bit or 128-bit vectors. 3124 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3125 if (BT->getKind() != BuiltinType::Float && 3126 BT->getKind() != BuiltinType::Double && 3127 BT->getKind() != BuiltinType::LongDouble) 3128 return false; 3129 } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 3130 unsigned VecSize = Context.getTypeSize(VT); 3131 if (VecSize != 64 && VecSize != 128) 3132 return false; 3133 } else { 3134 return false; 3135 } 3136 3137 // The base type must be the same for all members. Vector types of the 3138 // same total size are treated as being equivalent here. 3139 const Type *TyPtr = Ty.getTypePtr(); 3140 if (!Base) 3141 Base = TyPtr; 3142 if (Base != TyPtr && 3143 (!Base->isVectorType() || !TyPtr->isVectorType() || 3144 Context.getTypeSize(Base) != Context.getTypeSize(TyPtr))) 3145 return false; 3146 } 3147 3148 // Homogeneous Aggregates can have at most 4 members of the base type. 3149 if (HAMembers) 3150 *HAMembers = Members; 3151 3152 return (Members > 0 && Members <= 4); 3153} 3154 3155/// markAllocatedVFPs - update VFPRegs according to the alignment and 3156/// number of VFP registers (unit is S register) requested. 3157static void markAllocatedVFPs(int *VFPRegs, unsigned &AllocatedVFP, 3158 unsigned Alignment, 3159 unsigned NumRequired) { 3160 // Early Exit. 3161 if (AllocatedVFP >= 16) 3162 return; 3163 // C.1.vfp If the argument is a VFP CPRC and there are sufficient consecutive 3164 // VFP registers of the appropriate type unallocated then the argument is 3165 // allocated to the lowest-numbered sequence of such registers. 3166 for (unsigned I = 0; I < 16; I += Alignment) { 3167 bool FoundSlot = true; 3168 for (unsigned J = I, JEnd = I + NumRequired; J < JEnd; J++) 3169 if (J >= 16 || VFPRegs[J]) { 3170 FoundSlot = false; 3171 break; 3172 } 3173 if (FoundSlot) { 3174 for (unsigned J = I, JEnd = I + NumRequired; J < JEnd; J++) 3175 VFPRegs[J] = 1; 3176 AllocatedVFP += NumRequired; 3177 return; 3178 } 3179 } 3180 // C.2.vfp If the argument is a VFP CPRC then any VFP registers that are 3181 // unallocated are marked as unavailable. 3182 for (unsigned I = 0; I < 16; I++) 3183 VFPRegs[I] = 1; 3184 AllocatedVFP = 17; // We do not have enough VFP registers. 3185} 3186 3187ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, int *VFPRegs, 3188 unsigned &AllocatedVFP, 3189 bool &IsHA) const { 3190 // We update number of allocated VFPs according to 3191 // 6.1.2.1 The following argument types are VFP CPRCs: 3192 // A single-precision floating-point type (including promoted 3193 // half-precision types); A double-precision floating-point type; 3194 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate 3195 // with a Base Type of a single- or double-precision floating-point type, 3196 // 64-bit containerized vectors or 128-bit containerized vectors with one 3197 // to four Elements. 3198 3199 // Handle illegal vector types here. 3200 if (isIllegalVectorType(Ty)) { 3201 uint64_t Size = getContext().getTypeSize(Ty); 3202 if (Size <= 32) { 3203 llvm::Type *ResType = 3204 llvm::Type::getInt32Ty(getVMContext()); 3205 return ABIArgInfo::getDirect(ResType); 3206 } 3207 if (Size == 64) { 3208 llvm::Type *ResType = llvm::VectorType::get( 3209 llvm::Type::getInt32Ty(getVMContext()), 2); 3210 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, 2); 3211 return ABIArgInfo::getDirect(ResType); 3212 } 3213 if (Size == 128) { 3214 llvm::Type *ResType = llvm::VectorType::get( 3215 llvm::Type::getInt32Ty(getVMContext()), 4); 3216 markAllocatedVFPs(VFPRegs, AllocatedVFP, 4, 4); 3217 return ABIArgInfo::getDirect(ResType); 3218 } 3219 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3220 } 3221 // Update VFPRegs for legal vector types. 3222 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3223 uint64_t Size = getContext().getTypeSize(VT); 3224 // Size of a legal vector should be power of 2 and above 64. 3225 markAllocatedVFPs(VFPRegs, AllocatedVFP, Size >= 128 ? 4 : 2, Size / 32); 3226 } 3227 // Update VFPRegs for floating point types. 3228 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3229 if (BT->getKind() == BuiltinType::Half || 3230 BT->getKind() == BuiltinType::Float) 3231 markAllocatedVFPs(VFPRegs, AllocatedVFP, 1, 1); 3232 if (BT->getKind() == BuiltinType::Double || 3233 BT->getKind() == BuiltinType::LongDouble) 3234 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, 2); 3235 } 3236 3237 if (!isAggregateTypeForABI(Ty)) { 3238 // Treat an enum type as its underlying type. 3239 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3240 Ty = EnumTy->getDecl()->getIntegerType(); 3241 3242 return (Ty->isPromotableIntegerType() ? 3243 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3244 } 3245 3246 // Ignore empty records. 3247 if (isEmptyRecord(getContext(), Ty, true)) 3248 return ABIArgInfo::getIgnore(); 3249 3250 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) 3251 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 3252 3253 if (getABIKind() == ARMABIInfo::AAPCS_VFP) { 3254 // Homogeneous Aggregates need to be expanded when we can fit the aggregate 3255 // into VFP registers. 3256 const Type *Base = 0; 3257 uint64_t Members = 0; 3258 if (isHomogeneousAggregate(Ty, Base, getContext(), &Members)) { 3259 assert(Base && "Base class should be set for homogeneous aggregate"); 3260 // Base can be a floating-point or a vector. 3261 if (Base->isVectorType()) { 3262 // ElementSize is in number of floats. 3263 unsigned ElementSize = getContext().getTypeSize(Base) == 64 ? 2 : 4; 3264 markAllocatedVFPs(VFPRegs, AllocatedVFP, ElementSize, 3265 Members * ElementSize); 3266 } else if (Base->isSpecificBuiltinType(BuiltinType::Float)) 3267 markAllocatedVFPs(VFPRegs, AllocatedVFP, 1, Members); 3268 else { 3269 assert(Base->isSpecificBuiltinType(BuiltinType::Double) || 3270 Base->isSpecificBuiltinType(BuiltinType::LongDouble)); 3271 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, Members * 2); 3272 } 3273 IsHA = true; 3274 return ABIArgInfo::getExpand(); 3275 } 3276 } 3277 3278 // Support byval for ARM. 3279 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at 3280 // most 8-byte. We realign the indirect argument if type alignment is bigger 3281 // than ABI alignment. 3282 uint64_t ABIAlign = 4; 3283 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8; 3284 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3285 getABIKind() == ARMABIInfo::AAPCS) 3286 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3287 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) { 3288 return ABIArgInfo::getIndirect(0, /*ByVal=*/true, 3289 /*Realign=*/TyAlign > ABIAlign); 3290 } 3291 3292 // Otherwise, pass by coercing to a structure of the appropriate size. 3293 llvm::Type* ElemTy; 3294 unsigned SizeRegs; 3295 // FIXME: Try to match the types of the arguments more accurately where 3296 // we can. 3297 if (getContext().getTypeAlign(Ty) <= 32) { 3298 ElemTy = llvm::Type::getInt32Ty(getVMContext()); 3299 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32; 3300 } else { 3301 ElemTy = llvm::Type::getInt64Ty(getVMContext()); 3302 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64; 3303 } 3304 3305 llvm::Type *STy = 3306 llvm::StructType::get(llvm::ArrayType::get(ElemTy, SizeRegs), NULL); 3307 return ABIArgInfo::getDirect(STy); 3308} 3309 3310static bool isIntegerLikeType(QualType Ty, ASTContext &Context, 3311 llvm::LLVMContext &VMContext) { 3312 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure 3313 // is called integer-like if its size is less than or equal to one word, and 3314 // the offset of each of its addressable sub-fields is zero. 3315 3316 uint64_t Size = Context.getTypeSize(Ty); 3317 3318 // Check that the type fits in a word. 3319 if (Size > 32) 3320 return false; 3321 3322 // FIXME: Handle vector types! 3323 if (Ty->isVectorType()) 3324 return false; 3325 3326 // Float types are never treated as "integer like". 3327 if (Ty->isRealFloatingType()) 3328 return false; 3329 3330 // If this is a builtin or pointer type then it is ok. 3331 if (Ty->getAs<BuiltinType>() || Ty->isPointerType()) 3332 return true; 3333 3334 // Small complex integer types are "integer like". 3335 if (const ComplexType *CT = Ty->getAs<ComplexType>()) 3336 return isIntegerLikeType(CT->getElementType(), Context, VMContext); 3337 3338 // Single element and zero sized arrays should be allowed, by the definition 3339 // above, but they are not. 3340 3341 // Otherwise, it must be a record type. 3342 const RecordType *RT = Ty->getAs<RecordType>(); 3343 if (!RT) return false; 3344 3345 // Ignore records with flexible arrays. 3346 const RecordDecl *RD = RT->getDecl(); 3347 if (RD->hasFlexibleArrayMember()) 3348 return false; 3349 3350 // Check that all sub-fields are at offset 0, and are themselves "integer 3351 // like". 3352 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 3353 3354 bool HadField = false; 3355 unsigned idx = 0; 3356 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3357 i != e; ++i, ++idx) { 3358 const FieldDecl *FD = *i; 3359 3360 // Bit-fields are not addressable, we only need to verify they are "integer 3361 // like". We still have to disallow a subsequent non-bitfield, for example: 3362 // struct { int : 0; int x } 3363 // is non-integer like according to gcc. 3364 if (FD->isBitField()) { 3365 if (!RD->isUnion()) 3366 HadField = true; 3367 3368 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3369 return false; 3370 3371 continue; 3372 } 3373 3374 // Check if this field is at offset 0. 3375 if (Layout.getFieldOffset(idx) != 0) 3376 return false; 3377 3378 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3379 return false; 3380 3381 // Only allow at most one field in a structure. This doesn't match the 3382 // wording above, but follows gcc in situations with a field following an 3383 // empty structure. 3384 if (!RD->isUnion()) { 3385 if (HadField) 3386 return false; 3387 3388 HadField = true; 3389 } 3390 } 3391 3392 return true; 3393} 3394 3395ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy) const { 3396 if (RetTy->isVoidType()) 3397 return ABIArgInfo::getIgnore(); 3398 3399 // Large vector types should be returned via memory. 3400 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) 3401 return ABIArgInfo::getIndirect(0); 3402 3403 if (!isAggregateTypeForABI(RetTy)) { 3404 // Treat an enum type as its underlying type. 3405 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 3406 RetTy = EnumTy->getDecl()->getIntegerType(); 3407 3408 return (RetTy->isPromotableIntegerType() ? 3409 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3410 } 3411 3412 // Structures with either a non-trivial destructor or a non-trivial 3413 // copy constructor are always indirect. 3414 if (isRecordReturnIndirect(RetTy, CGT)) 3415 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3416 3417 // Are we following APCS? 3418 if (getABIKind() == APCS) { 3419 if (isEmptyRecord(getContext(), RetTy, false)) 3420 return ABIArgInfo::getIgnore(); 3421 3422 // Complex types are all returned as packed integers. 3423 // 3424 // FIXME: Consider using 2 x vector types if the back end handles them 3425 // correctly. 3426 if (RetTy->isAnyComplexType()) 3427 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 3428 getContext().getTypeSize(RetTy))); 3429 3430 // Integer like structures are returned in r0. 3431 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) { 3432 // Return in the smallest viable integer type. 3433 uint64_t Size = getContext().getTypeSize(RetTy); 3434 if (Size <= 8) 3435 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3436 if (Size <= 16) 3437 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3438 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3439 } 3440 3441 // Otherwise return in memory. 3442 return ABIArgInfo::getIndirect(0); 3443 } 3444 3445 // Otherwise this is an AAPCS variant. 3446 3447 if (isEmptyRecord(getContext(), RetTy, true)) 3448 return ABIArgInfo::getIgnore(); 3449 3450 // Check for homogeneous aggregates with AAPCS-VFP. 3451 if (getABIKind() == AAPCS_VFP) { 3452 const Type *Base = 0; 3453 if (isHomogeneousAggregate(RetTy, Base, getContext())) { 3454 assert(Base && "Base class should be set for homogeneous aggregate"); 3455 // Homogeneous Aggregates are returned directly. 3456 return ABIArgInfo::getDirect(); 3457 } 3458 } 3459 3460 // Aggregates <= 4 bytes are returned in r0; other aggregates 3461 // are returned indirectly. 3462 uint64_t Size = getContext().getTypeSize(RetTy); 3463 if (Size <= 32) { 3464 // Return in the smallest viable integer type. 3465 if (Size <= 8) 3466 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3467 if (Size <= 16) 3468 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3469 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3470 } 3471 3472 return ABIArgInfo::getIndirect(0); 3473} 3474 3475/// isIllegalVector - check whether Ty is an illegal vector type. 3476bool ARMABIInfo::isIllegalVectorType(QualType Ty) const { 3477 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3478 // Check whether VT is legal. 3479 unsigned NumElements = VT->getNumElements(); 3480 uint64_t Size = getContext().getTypeSize(VT); 3481 // NumElements should be power of 2. 3482 if ((NumElements & (NumElements - 1)) != 0) 3483 return true; 3484 // Size should be greater than 32 bits. 3485 return Size <= 32; 3486 } 3487 return false; 3488} 3489 3490llvm::Value *ARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3491 CodeGenFunction &CGF) const { 3492 llvm::Type *BP = CGF.Int8PtrTy; 3493 llvm::Type *BPP = CGF.Int8PtrPtrTy; 3494 3495 CGBuilderTy &Builder = CGF.Builder; 3496 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 3497 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 3498 3499 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8; 3500 uint64_t TyAlign = CGF.getContext().getTypeAlign(Ty) / 8; 3501 bool IsIndirect = false; 3502 3503 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for 3504 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte. 3505 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3506 getABIKind() == ARMABIInfo::AAPCS) 3507 TyAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3508 else 3509 TyAlign = 4; 3510 // Use indirect if size of the illegal vector is bigger than 16 bytes. 3511 if (isIllegalVectorType(Ty) && Size > 16) { 3512 IsIndirect = true; 3513 Size = 4; 3514 TyAlign = 4; 3515 } 3516 3517 // Handle address alignment for ABI alignment > 4 bytes. 3518 if (TyAlign > 4) { 3519 assert((TyAlign & (TyAlign - 1)) == 0 && 3520 "Alignment is not power of 2!"); 3521 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int32Ty); 3522 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt32(TyAlign - 1)); 3523 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt32(~(TyAlign - 1))); 3524 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align"); 3525 } 3526 3527 uint64_t Offset = 3528 llvm::RoundUpToAlignment(Size, 4); 3529 llvm::Value *NextAddr = 3530 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 3531 "ap.next"); 3532 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 3533 3534 if (IsIndirect) 3535 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP)); 3536 else if (TyAlign < CGF.getContext().getTypeAlign(Ty) / 8) { 3537 // We can't directly cast ap.cur to pointer to a vector type, since ap.cur 3538 // may not be correctly aligned for the vector type. We create an aligned 3539 // temporary space and copy the content over from ap.cur to the temporary 3540 // space. This is necessary if the natural alignment of the type is greater 3541 // than the ABI alignment. 3542 llvm::Type *I8PtrTy = Builder.getInt8PtrTy(); 3543 CharUnits CharSize = getContext().getTypeSizeInChars(Ty); 3544 llvm::Value *AlignedTemp = CGF.CreateTempAlloca(CGF.ConvertType(Ty), 3545 "var.align"); 3546 llvm::Value *Dst = Builder.CreateBitCast(AlignedTemp, I8PtrTy); 3547 llvm::Value *Src = Builder.CreateBitCast(Addr, I8PtrTy); 3548 Builder.CreateMemCpy(Dst, Src, 3549 llvm::ConstantInt::get(CGF.IntPtrTy, CharSize.getQuantity()), 3550 TyAlign, false); 3551 Addr = AlignedTemp; //The content is in aligned location. 3552 } 3553 llvm::Type *PTy = 3554 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 3555 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 3556 3557 return AddrTyped; 3558} 3559 3560namespace { 3561 3562class NaClARMABIInfo : public ABIInfo { 3563 public: 3564 NaClARMABIInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3565 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, Kind) {} 3566 virtual void computeInfo(CGFunctionInfo &FI) const; 3567 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3568 CodeGenFunction &CGF) const; 3569 private: 3570 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 3571 ARMABIInfo NInfo; // Used for everything else. 3572}; 3573 3574class NaClARMTargetCodeGenInfo : public TargetCodeGenInfo { 3575 public: 3576 NaClARMTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3577 : TargetCodeGenInfo(new NaClARMABIInfo(CGT, Kind)) {} 3578}; 3579 3580} 3581 3582void NaClARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3583 if (FI.getASTCallingConvention() == CC_PnaclCall) 3584 PInfo.computeInfo(FI); 3585 else 3586 static_cast<const ABIInfo&>(NInfo).computeInfo(FI); 3587} 3588 3589llvm::Value *NaClARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3590 CodeGenFunction &CGF) const { 3591 // Always use the native convention; calling pnacl-style varargs functions 3592 // is unsupported. 3593 return static_cast<const ABIInfo&>(NInfo).EmitVAArg(VAListAddr, Ty, CGF); 3594} 3595 3596//===----------------------------------------------------------------------===// 3597// AArch64 ABI Implementation 3598//===----------------------------------------------------------------------===// 3599 3600namespace { 3601 3602class AArch64ABIInfo : public ABIInfo { 3603public: 3604 AArch64ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 3605 3606private: 3607 // The AArch64 PCS is explicit about return types and argument types being 3608 // handled identically, so we don't need to draw a distinction between 3609 // Argument and Return classification. 3610 ABIArgInfo classifyGenericType(QualType Ty, int &FreeIntRegs, 3611 int &FreeVFPRegs) const; 3612 3613 ABIArgInfo tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, bool IsInt, 3614 llvm::Type *DirectTy = 0) const; 3615 3616 virtual void computeInfo(CGFunctionInfo &FI) const; 3617 3618 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3619 CodeGenFunction &CGF) const; 3620}; 3621 3622class AArch64TargetCodeGenInfo : public TargetCodeGenInfo { 3623public: 3624 AArch64TargetCodeGenInfo(CodeGenTypes &CGT) 3625 :TargetCodeGenInfo(new AArch64ABIInfo(CGT)) {} 3626 3627 const AArch64ABIInfo &getABIInfo() const { 3628 return static_cast<const AArch64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 3629 } 3630 3631 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 3632 return 31; 3633 } 3634 3635 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3636 llvm::Value *Address) const { 3637 // 0-31 are x0-x30 and sp: 8 bytes each 3638 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 3639 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 31); 3640 3641 // 64-95 are v0-v31: 16 bytes each 3642 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 3643 AssignToArrayRange(CGF.Builder, Address, Sixteen8, 64, 95); 3644 3645 return false; 3646 } 3647 3648}; 3649 3650} 3651 3652void AArch64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 3653 int FreeIntRegs = 8, FreeVFPRegs = 8; 3654 3655 FI.getReturnInfo() = classifyGenericType(FI.getReturnType(), 3656 FreeIntRegs, FreeVFPRegs); 3657 3658 FreeIntRegs = FreeVFPRegs = 8; 3659 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3660 it != ie; ++it) { 3661 it->info = classifyGenericType(it->type, FreeIntRegs, FreeVFPRegs); 3662 3663 } 3664} 3665 3666ABIArgInfo 3667AArch64ABIInfo::tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, 3668 bool IsInt, llvm::Type *DirectTy) const { 3669 if (FreeRegs >= RegsNeeded) { 3670 FreeRegs -= RegsNeeded; 3671 return ABIArgInfo::getDirect(DirectTy); 3672 } 3673 3674 llvm::Type *Padding = 0; 3675 3676 // We need padding so that later arguments don't get filled in anyway. That 3677 // wouldn't happen if only ByVal arguments followed in the same category, but 3678 // a large structure will simply seem to be a pointer as far as LLVM is 3679 // concerned. 3680 if (FreeRegs > 0) { 3681 if (IsInt) 3682 Padding = llvm::Type::getInt64Ty(getVMContext()); 3683 else 3684 Padding = llvm::Type::getFloatTy(getVMContext()); 3685 3686 // Either [N x i64] or [N x float]. 3687 Padding = llvm::ArrayType::get(Padding, FreeRegs); 3688 FreeRegs = 0; 3689 } 3690 3691 return ABIArgInfo::getIndirect(getContext().getTypeAlign(Ty) / 8, 3692 /*IsByVal=*/ true, /*Realign=*/ false, 3693 Padding); 3694} 3695 3696 3697ABIArgInfo AArch64ABIInfo::classifyGenericType(QualType Ty, 3698 int &FreeIntRegs, 3699 int &FreeVFPRegs) const { 3700 // Can only occurs for return, but harmless otherwise. 3701 if (Ty->isVoidType()) 3702 return ABIArgInfo::getIgnore(); 3703 3704 // Large vector types should be returned via memory. There's no such concept 3705 // in the ABI, but they'd be over 16 bytes anyway so no matter how they're 3706 // classified they'd go into memory (see B.3). 3707 if (Ty->isVectorType() && getContext().getTypeSize(Ty) > 128) { 3708 if (FreeIntRegs > 0) 3709 --FreeIntRegs; 3710 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3711 } 3712 3713 // All non-aggregate LLVM types have a concrete ABI representation so they can 3714 // be passed directly. After this block we're guaranteed to be in a 3715 // complicated case. 3716 if (!isAggregateTypeForABI(Ty)) { 3717 // Treat an enum type as its underlying type. 3718 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3719 Ty = EnumTy->getDecl()->getIntegerType(); 3720 3721 if (Ty->isFloatingType() || Ty->isVectorType()) 3722 return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ false); 3723 3724 assert(getContext().getTypeSize(Ty) <= 128 && 3725 "unexpectedly large scalar type"); 3726 3727 int RegsNeeded = getContext().getTypeSize(Ty) > 64 ? 2 : 1; 3728 3729 // If the type may need padding registers to ensure "alignment", we must be 3730 // careful when this is accounted for. Increasing the effective size covers 3731 // all cases. 3732 if (getContext().getTypeAlign(Ty) == 128) 3733 RegsNeeded += FreeIntRegs % 2 != 0; 3734 3735 return tryUseRegs(Ty, FreeIntRegs, RegsNeeded, /*IsInt=*/ true); 3736 } 3737 3738 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) { 3739 if (FreeIntRegs > 0 && RAA == CGCXXABI::RAA_Indirect) 3740 --FreeIntRegs; 3741 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 3742 } 3743 3744 if (isEmptyRecord(getContext(), Ty, true)) { 3745 if (!getContext().getLangOpts().CPlusPlus) { 3746 // Empty structs outside C++ mode are a GNU extension, so no ABI can 3747 // possibly tell us what to do. It turns out (I believe) that GCC ignores 3748 // the object for parameter-passsing purposes. 3749 return ABIArgInfo::getIgnore(); 3750 } 3751 3752 // The combination of C++98 9p5 (sizeof(struct) != 0) and the pseudocode 3753 // description of va_arg in the PCS require that an empty struct does 3754 // actually occupy space for parameter-passing. I'm hoping for a 3755 // clarification giving an explicit paragraph to point to in future. 3756 return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ true, 3757 llvm::Type::getInt8Ty(getVMContext())); 3758 } 3759 3760 // Homogeneous vector aggregates get passed in registers or on the stack. 3761 const Type *Base = 0; 3762 uint64_t NumMembers = 0; 3763 if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers)) { 3764 assert(Base && "Base class should be set for homogeneous aggregate"); 3765 // Homogeneous aggregates are passed and returned directly. 3766 return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ NumMembers, 3767 /*IsInt=*/ false); 3768 } 3769 3770 uint64_t Size = getContext().getTypeSize(Ty); 3771 if (Size <= 128) { 3772 // Small structs can use the same direct type whether they're in registers 3773 // or on the stack. 3774 llvm::Type *BaseTy; 3775 unsigned NumBases; 3776 int SizeInRegs = (Size + 63) / 64; 3777 3778 if (getContext().getTypeAlign(Ty) == 128) { 3779 BaseTy = llvm::Type::getIntNTy(getVMContext(), 128); 3780 NumBases = 1; 3781 3782 // If the type may need padding registers to ensure "alignment", we must 3783 // be careful when this is accounted for. Increasing the effective size 3784 // covers all cases. 3785 SizeInRegs += FreeIntRegs % 2 != 0; 3786 } else { 3787 BaseTy = llvm::Type::getInt64Ty(getVMContext()); 3788 NumBases = SizeInRegs; 3789 } 3790 llvm::Type *DirectTy = llvm::ArrayType::get(BaseTy, NumBases); 3791 3792 return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ SizeInRegs, 3793 /*IsInt=*/ true, DirectTy); 3794 } 3795 3796 // If the aggregate is > 16 bytes, it's passed and returned indirectly. In 3797 // LLVM terms the return uses an "sret" pointer, but that's handled elsewhere. 3798 --FreeIntRegs; 3799 return ABIArgInfo::getIndirect(0, /* byVal = */ false); 3800} 3801 3802llvm::Value *AArch64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3803 CodeGenFunction &CGF) const { 3804 // The AArch64 va_list type and handling is specified in the Procedure Call 3805 // Standard, section B.4: 3806 // 3807 // struct { 3808 // void *__stack; 3809 // void *__gr_top; 3810 // void *__vr_top; 3811 // int __gr_offs; 3812 // int __vr_offs; 3813 // }; 3814 3815 assert(!CGF.CGM.getDataLayout().isBigEndian() 3816 && "va_arg not implemented for big-endian AArch64"); 3817 3818 int FreeIntRegs = 8, FreeVFPRegs = 8; 3819 Ty = CGF.getContext().getCanonicalType(Ty); 3820 ABIArgInfo AI = classifyGenericType(Ty, FreeIntRegs, FreeVFPRegs); 3821 3822 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg"); 3823 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 3824 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack"); 3825 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 3826 3827 llvm::Value *reg_offs_p = 0, *reg_offs = 0; 3828 int reg_top_index; 3829 int RegSize; 3830 if (FreeIntRegs < 8) { 3831 assert(FreeVFPRegs == 8 && "Arguments never split between int & VFP regs"); 3832 // 3 is the field number of __gr_offs 3833 reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p"); 3834 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs"); 3835 reg_top_index = 1; // field number for __gr_top 3836 RegSize = 8 * (8 - FreeIntRegs); 3837 } else { 3838 assert(FreeVFPRegs < 8 && "Argument must go in VFP or int regs"); 3839 // 4 is the field number of __vr_offs. 3840 reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p"); 3841 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs"); 3842 reg_top_index = 2; // field number for __vr_top 3843 RegSize = 16 * (8 - FreeVFPRegs); 3844 } 3845 3846 //======================================= 3847 // Find out where argument was passed 3848 //======================================= 3849 3850 // If reg_offs >= 0 we're already using the stack for this type of 3851 // argument. We don't want to keep updating reg_offs (in case it overflows, 3852 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves 3853 // whatever they get). 3854 llvm::Value *UsingStack = 0; 3855 UsingStack = CGF.Builder.CreateICmpSGE(reg_offs, 3856 llvm::ConstantInt::get(CGF.Int32Ty, 0)); 3857 3858 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock); 3859 3860 // Otherwise, at least some kind of argument could go in these registers, the 3861 // quesiton is whether this particular type is too big. 3862 CGF.EmitBlock(MaybeRegBlock); 3863 3864 // Integer arguments may need to correct register alignment (for example a 3865 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we 3866 // align __gr_offs to calculate the potential address. 3867 if (FreeIntRegs < 8 && AI.isDirect() && getContext().getTypeAlign(Ty) > 64) { 3868 int Align = getContext().getTypeAlign(Ty) / 8; 3869 3870 reg_offs = CGF.Builder.CreateAdd(reg_offs, 3871 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1), 3872 "align_regoffs"); 3873 reg_offs = CGF.Builder.CreateAnd(reg_offs, 3874 llvm::ConstantInt::get(CGF.Int32Ty, -Align), 3875 "aligned_regoffs"); 3876 } 3877 3878 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list. 3879 llvm::Value *NewOffset = 0; 3880 NewOffset = CGF.Builder.CreateAdd(reg_offs, 3881 llvm::ConstantInt::get(CGF.Int32Ty, RegSize), 3882 "new_reg_offs"); 3883 CGF.Builder.CreateStore(NewOffset, reg_offs_p); 3884 3885 // Now we're in a position to decide whether this argument really was in 3886 // registers or not. 3887 llvm::Value *InRegs = 0; 3888 InRegs = CGF.Builder.CreateICmpSLE(NewOffset, 3889 llvm::ConstantInt::get(CGF.Int32Ty, 0), 3890 "inreg"); 3891 3892 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock); 3893 3894 //======================================= 3895 // Argument was in registers 3896 //======================================= 3897 3898 // Now we emit the code for if the argument was originally passed in 3899 // registers. First start the appropriate block: 3900 CGF.EmitBlock(InRegBlock); 3901 3902 llvm::Value *reg_top_p = 0, *reg_top = 0; 3903 reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p"); 3904 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top"); 3905 llvm::Value *BaseAddr = CGF.Builder.CreateGEP(reg_top, reg_offs); 3906 llvm::Value *RegAddr = 0; 3907 llvm::Type *MemTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); 3908 3909 if (!AI.isDirect()) { 3910 // If it's been passed indirectly (actually a struct), whatever we find from 3911 // stored registers or on the stack will actually be a struct **. 3912 MemTy = llvm::PointerType::getUnqual(MemTy); 3913 } 3914 3915 const Type *Base = 0; 3916 uint64_t NumMembers; 3917 if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers) 3918 && NumMembers > 1) { 3919 // Homogeneous aggregates passed in registers will have their elements split 3920 // and stored 16-bytes apart regardless of size (they're notionally in qN, 3921 // qN+1, ...). We reload and store into a temporary local variable 3922 // contiguously. 3923 assert(AI.isDirect() && "Homogeneous aggregates should be passed directly"); 3924 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0)); 3925 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers); 3926 llvm::Value *Tmp = CGF.CreateTempAlloca(HFATy); 3927 3928 for (unsigned i = 0; i < NumMembers; ++i) { 3929 llvm::Value *BaseOffset = llvm::ConstantInt::get(CGF.Int32Ty, 16 * i); 3930 llvm::Value *LoadAddr = CGF.Builder.CreateGEP(BaseAddr, BaseOffset); 3931 LoadAddr = CGF.Builder.CreateBitCast(LoadAddr, 3932 llvm::PointerType::getUnqual(BaseTy)); 3933 llvm::Value *StoreAddr = CGF.Builder.CreateStructGEP(Tmp, i); 3934 3935 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr); 3936 CGF.Builder.CreateStore(Elem, StoreAddr); 3937 } 3938 3939 RegAddr = CGF.Builder.CreateBitCast(Tmp, MemTy); 3940 } else { 3941 // Otherwise the object is contiguous in memory 3942 RegAddr = CGF.Builder.CreateBitCast(BaseAddr, MemTy); 3943 } 3944 3945 CGF.EmitBranch(ContBlock); 3946 3947 //======================================= 3948 // Argument was on the stack 3949 //======================================= 3950 CGF.EmitBlock(OnStackBlock); 3951 3952 llvm::Value *stack_p = 0, *OnStackAddr = 0; 3953 stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p"); 3954 OnStackAddr = CGF.Builder.CreateLoad(stack_p, "stack"); 3955 3956 // Again, stack arguments may need realigmnent. In this case both integer and 3957 // floating-point ones might be affected. 3958 if (AI.isDirect() && getContext().getTypeAlign(Ty) > 64) { 3959 int Align = getContext().getTypeAlign(Ty) / 8; 3960 3961 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty); 3962 3963 OnStackAddr = CGF.Builder.CreateAdd(OnStackAddr, 3964 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1), 3965 "align_stack"); 3966 OnStackAddr = CGF.Builder.CreateAnd(OnStackAddr, 3967 llvm::ConstantInt::get(CGF.Int64Ty, -Align), 3968 "align_stack"); 3969 3970 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy); 3971 } 3972 3973 uint64_t StackSize; 3974 if (AI.isDirect()) 3975 StackSize = getContext().getTypeSize(Ty) / 8; 3976 else 3977 StackSize = 8; 3978 3979 // All stack slots are 8 bytes 3980 StackSize = llvm::RoundUpToAlignment(StackSize, 8); 3981 3982 llvm::Value *StackSizeC = llvm::ConstantInt::get(CGF.Int32Ty, StackSize); 3983 llvm::Value *NewStack = CGF.Builder.CreateGEP(OnStackAddr, StackSizeC, 3984 "new_stack"); 3985 3986 // Write the new value of __stack for the next call to va_arg 3987 CGF.Builder.CreateStore(NewStack, stack_p); 3988 3989 OnStackAddr = CGF.Builder.CreateBitCast(OnStackAddr, MemTy); 3990 3991 CGF.EmitBranch(ContBlock); 3992 3993 //======================================= 3994 // Tidy up 3995 //======================================= 3996 CGF.EmitBlock(ContBlock); 3997 3998 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(MemTy, 2, "vaarg.addr"); 3999 ResAddr->addIncoming(RegAddr, InRegBlock); 4000 ResAddr->addIncoming(OnStackAddr, OnStackBlock); 4001 4002 if (AI.isDirect()) 4003 return ResAddr; 4004 4005 return CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"); 4006} 4007 4008//===----------------------------------------------------------------------===// 4009// NVPTX ABI Implementation 4010//===----------------------------------------------------------------------===// 4011 4012namespace { 4013 4014class NVPTXABIInfo : public ABIInfo { 4015public: 4016 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4017 4018 ABIArgInfo classifyReturnType(QualType RetTy) const; 4019 ABIArgInfo classifyArgumentType(QualType Ty) const; 4020 4021 virtual void computeInfo(CGFunctionInfo &FI) const; 4022 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4023 CodeGenFunction &CFG) const; 4024}; 4025 4026class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo { 4027public: 4028 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT) 4029 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {} 4030 4031 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4032 CodeGen::CodeGenModule &M) const; 4033private: 4034 static void addKernelMetadata(llvm::Function *F); 4035}; 4036 4037ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const { 4038 if (RetTy->isVoidType()) 4039 return ABIArgInfo::getIgnore(); 4040 if (isAggregateTypeForABI(RetTy)) 4041 return ABIArgInfo::getIndirect(0); 4042 return ABIArgInfo::getDirect(); 4043} 4044 4045ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const { 4046 if (isAggregateTypeForABI(Ty)) 4047 return ABIArgInfo::getIndirect(0); 4048 4049 return ABIArgInfo::getDirect(); 4050} 4051 4052void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const { 4053 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4054 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4055 it != ie; ++it) 4056 it->info = classifyArgumentType(it->type); 4057 4058 // Always honor user-specified calling convention. 4059 if (FI.getCallingConvention() != llvm::CallingConv::C) 4060 return; 4061 4062 FI.setEffectiveCallingConvention(getRuntimeCC()); 4063} 4064 4065llvm::Value *NVPTXABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4066 CodeGenFunction &CFG) const { 4067 llvm_unreachable("NVPTX does not support varargs"); 4068} 4069 4070void NVPTXTargetCodeGenInfo:: 4071SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4072 CodeGen::CodeGenModule &M) const{ 4073 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4074 if (!FD) return; 4075 4076 llvm::Function *F = cast<llvm::Function>(GV); 4077 4078 // Perform special handling in OpenCL mode 4079 if (M.getLangOpts().OpenCL) { 4080 // Use OpenCL function attributes to check for kernel functions 4081 // By default, all functions are device functions 4082 if (FD->hasAttr<OpenCLKernelAttr>()) { 4083 // OpenCL __kernel functions get kernel metadata 4084 addKernelMetadata(F); 4085 // And kernel functions are not subject to inlining 4086 F->addFnAttr(llvm::Attribute::NoInline); 4087 } 4088 } 4089 4090 // Perform special handling in CUDA mode. 4091 if (M.getLangOpts().CUDA) { 4092 // CUDA __global__ functions get a kernel metadata entry. Since 4093 // __global__ functions cannot be called from the device, we do not 4094 // need to set the noinline attribute. 4095 if (FD->getAttr<CUDAGlobalAttr>()) 4096 addKernelMetadata(F); 4097 } 4098} 4099 4100void NVPTXTargetCodeGenInfo::addKernelMetadata(llvm::Function *F) { 4101 llvm::Module *M = F->getParent(); 4102 llvm::LLVMContext &Ctx = M->getContext(); 4103 4104 // Get "nvvm.annotations" metadata node 4105 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations"); 4106 4107 // Create !{<func-ref>, metadata !"kernel", i32 1} node 4108 llvm::SmallVector<llvm::Value *, 3> MDVals; 4109 MDVals.push_back(F); 4110 MDVals.push_back(llvm::MDString::get(Ctx, "kernel")); 4111 MDVals.push_back(llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), 1)); 4112 4113 // Append metadata to nvvm.annotations 4114 MD->addOperand(llvm::MDNode::get(Ctx, MDVals)); 4115} 4116 4117} 4118 4119//===----------------------------------------------------------------------===// 4120// SystemZ ABI Implementation 4121//===----------------------------------------------------------------------===// 4122 4123namespace { 4124 4125class SystemZABIInfo : public ABIInfo { 4126public: 4127 SystemZABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4128 4129 bool isPromotableIntegerType(QualType Ty) const; 4130 bool isCompoundType(QualType Ty) const; 4131 bool isFPArgumentType(QualType Ty) const; 4132 4133 ABIArgInfo classifyReturnType(QualType RetTy) const; 4134 ABIArgInfo classifyArgumentType(QualType ArgTy) const; 4135 4136 virtual void computeInfo(CGFunctionInfo &FI) const { 4137 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4138 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4139 it != ie; ++it) 4140 it->info = classifyArgumentType(it->type); 4141 } 4142 4143 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4144 CodeGenFunction &CGF) const; 4145}; 4146 4147class SystemZTargetCodeGenInfo : public TargetCodeGenInfo { 4148public: 4149 SystemZTargetCodeGenInfo(CodeGenTypes &CGT) 4150 : TargetCodeGenInfo(new SystemZABIInfo(CGT)) {} 4151}; 4152 4153} 4154 4155bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const { 4156 // Treat an enum type as its underlying type. 4157 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4158 Ty = EnumTy->getDecl()->getIntegerType(); 4159 4160 // Promotable integer types are required to be promoted by the ABI. 4161 if (Ty->isPromotableIntegerType()) 4162 return true; 4163 4164 // 32-bit values must also be promoted. 4165 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4166 switch (BT->getKind()) { 4167 case BuiltinType::Int: 4168 case BuiltinType::UInt: 4169 return true; 4170 default: 4171 return false; 4172 } 4173 return false; 4174} 4175 4176bool SystemZABIInfo::isCompoundType(QualType Ty) const { 4177 return Ty->isAnyComplexType() || isAggregateTypeForABI(Ty); 4178} 4179 4180bool SystemZABIInfo::isFPArgumentType(QualType Ty) const { 4181 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4182 switch (BT->getKind()) { 4183 case BuiltinType::Float: 4184 case BuiltinType::Double: 4185 return true; 4186 default: 4187 return false; 4188 } 4189 4190 if (const RecordType *RT = Ty->getAsStructureType()) { 4191 const RecordDecl *RD = RT->getDecl(); 4192 bool Found = false; 4193 4194 // If this is a C++ record, check the bases first. 4195 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 4196 for (CXXRecordDecl::base_class_const_iterator I = CXXRD->bases_begin(), 4197 E = CXXRD->bases_end(); I != E; ++I) { 4198 QualType Base = I->getType(); 4199 4200 // Empty bases don't affect things either way. 4201 if (isEmptyRecord(getContext(), Base, true)) 4202 continue; 4203 4204 if (Found) 4205 return false; 4206 Found = isFPArgumentType(Base); 4207 if (!Found) 4208 return false; 4209 } 4210 4211 // Check the fields. 4212 for (RecordDecl::field_iterator I = RD->field_begin(), 4213 E = RD->field_end(); I != E; ++I) { 4214 const FieldDecl *FD = *I; 4215 4216 // Empty bitfields don't affect things either way. 4217 // Unlike isSingleElementStruct(), empty structure and array fields 4218 // do count. So do anonymous bitfields that aren't zero-sized. 4219 if (FD->isBitField() && FD->getBitWidthValue(getContext()) == 0) 4220 return true; 4221 4222 // Unlike isSingleElementStruct(), arrays do not count. 4223 // Nested isFPArgumentType structures still do though. 4224 if (Found) 4225 return false; 4226 Found = isFPArgumentType(FD->getType()); 4227 if (!Found) 4228 return false; 4229 } 4230 4231 // Unlike isSingleElementStruct(), trailing padding is allowed. 4232 // An 8-byte aligned struct s { float f; } is passed as a double. 4233 return Found; 4234 } 4235 4236 return false; 4237} 4238 4239llvm::Value *SystemZABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4240 CodeGenFunction &CGF) const { 4241 // Assume that va_list type is correct; should be pointer to LLVM type: 4242 // struct { 4243 // i64 __gpr; 4244 // i64 __fpr; 4245 // i8 *__overflow_arg_area; 4246 // i8 *__reg_save_area; 4247 // }; 4248 4249 // Every argument occupies 8 bytes and is passed by preference in either 4250 // GPRs or FPRs. 4251 Ty = CGF.getContext().getCanonicalType(Ty); 4252 ABIArgInfo AI = classifyArgumentType(Ty); 4253 bool InFPRs = isFPArgumentType(Ty); 4254 4255 llvm::Type *APTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); 4256 bool IsIndirect = AI.isIndirect(); 4257 unsigned UnpaddedBitSize; 4258 if (IsIndirect) { 4259 APTy = llvm::PointerType::getUnqual(APTy); 4260 UnpaddedBitSize = 64; 4261 } else 4262 UnpaddedBitSize = getContext().getTypeSize(Ty); 4263 unsigned PaddedBitSize = 64; 4264 assert((UnpaddedBitSize <= PaddedBitSize) && "Invalid argument size."); 4265 4266 unsigned PaddedSize = PaddedBitSize / 8; 4267 unsigned Padding = (PaddedBitSize - UnpaddedBitSize) / 8; 4268 4269 unsigned MaxRegs, RegCountField, RegSaveIndex, RegPadding; 4270 if (InFPRs) { 4271 MaxRegs = 4; // Maximum of 4 FPR arguments 4272 RegCountField = 1; // __fpr 4273 RegSaveIndex = 16; // save offset for f0 4274 RegPadding = 0; // floats are passed in the high bits of an FPR 4275 } else { 4276 MaxRegs = 5; // Maximum of 5 GPR arguments 4277 RegCountField = 0; // __gpr 4278 RegSaveIndex = 2; // save offset for r2 4279 RegPadding = Padding; // values are passed in the low bits of a GPR 4280 } 4281 4282 llvm::Value *RegCountPtr = 4283 CGF.Builder.CreateStructGEP(VAListAddr, RegCountField, "reg_count_ptr"); 4284 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count"); 4285 llvm::Type *IndexTy = RegCount->getType(); 4286 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs); 4287 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV, 4288 "fits_in_regs"); 4289 4290 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 4291 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 4292 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 4293 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 4294 4295 // Emit code to load the value if it was passed in registers. 4296 CGF.EmitBlock(InRegBlock); 4297 4298 // Work out the address of an argument register. 4299 llvm::Value *PaddedSizeV = llvm::ConstantInt::get(IndexTy, PaddedSize); 4300 llvm::Value *ScaledRegCount = 4301 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count"); 4302 llvm::Value *RegBase = 4303 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize + RegPadding); 4304 llvm::Value *RegOffset = 4305 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset"); 4306 llvm::Value *RegSaveAreaPtr = 4307 CGF.Builder.CreateStructGEP(VAListAddr, 3, "reg_save_area_ptr"); 4308 llvm::Value *RegSaveArea = 4309 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area"); 4310 llvm::Value *RawRegAddr = 4311 CGF.Builder.CreateGEP(RegSaveArea, RegOffset, "raw_reg_addr"); 4312 llvm::Value *RegAddr = 4313 CGF.Builder.CreateBitCast(RawRegAddr, APTy, "reg_addr"); 4314 4315 // Update the register count 4316 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1); 4317 llvm::Value *NewRegCount = 4318 CGF.Builder.CreateAdd(RegCount, One, "reg_count"); 4319 CGF.Builder.CreateStore(NewRegCount, RegCountPtr); 4320 CGF.EmitBranch(ContBlock); 4321 4322 // Emit code to load the value if it was passed in memory. 4323 CGF.EmitBlock(InMemBlock); 4324 4325 // Work out the address of a stack argument. 4326 llvm::Value *OverflowArgAreaPtr = 4327 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_ptr"); 4328 llvm::Value *OverflowArgArea = 4329 CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"); 4330 llvm::Value *PaddingV = llvm::ConstantInt::get(IndexTy, Padding); 4331 llvm::Value *RawMemAddr = 4332 CGF.Builder.CreateGEP(OverflowArgArea, PaddingV, "raw_mem_addr"); 4333 llvm::Value *MemAddr = 4334 CGF.Builder.CreateBitCast(RawMemAddr, APTy, "mem_addr"); 4335 4336 // Update overflow_arg_area_ptr pointer 4337 llvm::Value *NewOverflowArgArea = 4338 CGF.Builder.CreateGEP(OverflowArgArea, PaddedSizeV, "overflow_arg_area"); 4339 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr); 4340 CGF.EmitBranch(ContBlock); 4341 4342 // Return the appropriate result. 4343 CGF.EmitBlock(ContBlock); 4344 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(APTy, 2, "va_arg.addr"); 4345 ResAddr->addIncoming(RegAddr, InRegBlock); 4346 ResAddr->addIncoming(MemAddr, InMemBlock); 4347 4348 if (IsIndirect) 4349 return CGF.Builder.CreateLoad(ResAddr, "indirect_arg"); 4350 4351 return ResAddr; 4352} 4353 4354 4355ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const { 4356 if (RetTy->isVoidType()) 4357 return ABIArgInfo::getIgnore(); 4358 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64) 4359 return ABIArgInfo::getIndirect(0); 4360 return (isPromotableIntegerType(RetTy) ? 4361 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4362} 4363 4364ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const { 4365 // Handle the generic C++ ABI. 4366 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) 4367 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 4368 4369 // Integers and enums are extended to full register width. 4370 if (isPromotableIntegerType(Ty)) 4371 return ABIArgInfo::getExtend(); 4372 4373 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly. 4374 uint64_t Size = getContext().getTypeSize(Ty); 4375 if (Size != 8 && Size != 16 && Size != 32 && Size != 64) 4376 return ABIArgInfo::getIndirect(0); 4377 4378 // Handle small structures. 4379 if (const RecordType *RT = Ty->getAs<RecordType>()) { 4380 // Structures with flexible arrays have variable length, so really 4381 // fail the size test above. 4382 const RecordDecl *RD = RT->getDecl(); 4383 if (RD->hasFlexibleArrayMember()) 4384 return ABIArgInfo::getIndirect(0); 4385 4386 // The structure is passed as an unextended integer, a float, or a double. 4387 llvm::Type *PassTy; 4388 if (isFPArgumentType(Ty)) { 4389 assert(Size == 32 || Size == 64); 4390 if (Size == 32) 4391 PassTy = llvm::Type::getFloatTy(getVMContext()); 4392 else 4393 PassTy = llvm::Type::getDoubleTy(getVMContext()); 4394 } else 4395 PassTy = llvm::IntegerType::get(getVMContext(), Size); 4396 return ABIArgInfo::getDirect(PassTy); 4397 } 4398 4399 // Non-structure compounds are passed indirectly. 4400 if (isCompoundType(Ty)) 4401 return ABIArgInfo::getIndirect(0); 4402 4403 return ABIArgInfo::getDirect(0); 4404} 4405 4406//===----------------------------------------------------------------------===// 4407// MBlaze ABI Implementation 4408//===----------------------------------------------------------------------===// 4409 4410namespace { 4411 4412class MBlazeABIInfo : public ABIInfo { 4413public: 4414 MBlazeABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4415 4416 bool isPromotableIntegerType(QualType Ty) const; 4417 4418 ABIArgInfo classifyReturnType(QualType RetTy) const; 4419 ABIArgInfo classifyArgumentType(QualType RetTy) const; 4420 4421 virtual void computeInfo(CGFunctionInfo &FI) const { 4422 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4423 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4424 it != ie; ++it) 4425 it->info = classifyArgumentType(it->type); 4426 } 4427 4428 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4429 CodeGenFunction &CGF) const; 4430}; 4431 4432class MBlazeTargetCodeGenInfo : public TargetCodeGenInfo { 4433public: 4434 MBlazeTargetCodeGenInfo(CodeGenTypes &CGT) 4435 : TargetCodeGenInfo(new MBlazeABIInfo(CGT)) {} 4436 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4437 CodeGen::CodeGenModule &M) const; 4438}; 4439 4440} 4441 4442bool MBlazeABIInfo::isPromotableIntegerType(QualType Ty) const { 4443 // MBlaze ABI requires all 8 and 16 bit quantities to be extended. 4444 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4445 switch (BT->getKind()) { 4446 case BuiltinType::Bool: 4447 case BuiltinType::Char_S: 4448 case BuiltinType::Char_U: 4449 case BuiltinType::SChar: 4450 case BuiltinType::UChar: 4451 case BuiltinType::Short: 4452 case BuiltinType::UShort: 4453 return true; 4454 default: 4455 return false; 4456 } 4457 return false; 4458} 4459 4460llvm::Value *MBlazeABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4461 CodeGenFunction &CGF) const { 4462 // FIXME: Implement 4463 return 0; 4464} 4465 4466 4467ABIArgInfo MBlazeABIInfo::classifyReturnType(QualType RetTy) const { 4468 if (RetTy->isVoidType()) 4469 return ABIArgInfo::getIgnore(); 4470 if (isAggregateTypeForABI(RetTy)) 4471 return ABIArgInfo::getIndirect(0); 4472 4473 return (isPromotableIntegerType(RetTy) ? 4474 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4475} 4476 4477ABIArgInfo MBlazeABIInfo::classifyArgumentType(QualType Ty) const { 4478 if (isAggregateTypeForABI(Ty)) 4479 return ABIArgInfo::getIndirect(0); 4480 4481 return (isPromotableIntegerType(Ty) ? 4482 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4483} 4484 4485void MBlazeTargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4486 llvm::GlobalValue *GV, 4487 CodeGen::CodeGenModule &M) 4488 const { 4489 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4490 if (!FD) return; 4491 4492 llvm::CallingConv::ID CC = llvm::CallingConv::C; 4493 if (FD->hasAttr<MBlazeInterruptHandlerAttr>()) 4494 CC = llvm::CallingConv::MBLAZE_INTR; 4495 else if (FD->hasAttr<MBlazeSaveVolatilesAttr>()) 4496 CC = llvm::CallingConv::MBLAZE_SVOL; 4497 4498 if (CC != llvm::CallingConv::C) { 4499 // Handle 'interrupt_handler' attribute: 4500 llvm::Function *F = cast<llvm::Function>(GV); 4501 4502 // Step 1: Set ISR calling convention. 4503 F->setCallingConv(CC); 4504 4505 // Step 2: Add attributes goodness. 4506 F->addFnAttr(llvm::Attribute::NoInline); 4507 } 4508 4509 // Step 3: Emit _interrupt_handler alias. 4510 if (CC == llvm::CallingConv::MBLAZE_INTR) 4511 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 4512 "_interrupt_handler", GV, &M.getModule()); 4513} 4514 4515 4516//===----------------------------------------------------------------------===// 4517// MSP430 ABI Implementation 4518//===----------------------------------------------------------------------===// 4519 4520namespace { 4521 4522class MSP430TargetCodeGenInfo : public TargetCodeGenInfo { 4523public: 4524 MSP430TargetCodeGenInfo(CodeGenTypes &CGT) 4525 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 4526 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4527 CodeGen::CodeGenModule &M) const; 4528}; 4529 4530} 4531 4532void MSP430TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4533 llvm::GlobalValue *GV, 4534 CodeGen::CodeGenModule &M) const { 4535 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 4536 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) { 4537 // Handle 'interrupt' attribute: 4538 llvm::Function *F = cast<llvm::Function>(GV); 4539 4540 // Step 1: Set ISR calling convention. 4541 F->setCallingConv(llvm::CallingConv::MSP430_INTR); 4542 4543 // Step 2: Add attributes goodness. 4544 F->addFnAttr(llvm::Attribute::NoInline); 4545 4546 // Step 3: Emit ISR vector alias. 4547 unsigned Num = attr->getNumber() / 2; 4548 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 4549 "__isr_" + Twine(Num), 4550 GV, &M.getModule()); 4551 } 4552 } 4553} 4554 4555//===----------------------------------------------------------------------===// 4556// MIPS ABI Implementation. This works for both little-endian and 4557// big-endian variants. 4558//===----------------------------------------------------------------------===// 4559 4560namespace { 4561class MipsABIInfo : public ABIInfo { 4562 bool IsO32; 4563 unsigned MinABIStackAlignInBytes, StackAlignInBytes; 4564 void CoerceToIntArgs(uint64_t TySize, 4565 SmallVector<llvm::Type*, 8> &ArgList) const; 4566 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const; 4567 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const; 4568 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const; 4569public: 4570 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) : 4571 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8), 4572 StackAlignInBytes(IsO32 ? 8 : 16) {} 4573 4574 ABIArgInfo classifyReturnType(QualType RetTy) const; 4575 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const; 4576 virtual void computeInfo(CGFunctionInfo &FI) const; 4577 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4578 CodeGenFunction &CGF) const; 4579}; 4580 4581class MIPSTargetCodeGenInfo : public TargetCodeGenInfo { 4582 unsigned SizeOfUnwindException; 4583public: 4584 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32) 4585 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)), 4586 SizeOfUnwindException(IsO32 ? 24 : 32) {} 4587 4588 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 4589 return 29; 4590 } 4591 4592 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4593 CodeGen::CodeGenModule &CGM) const { 4594 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4595 if (!FD) return; 4596 llvm::Function *Fn = cast<llvm::Function>(GV); 4597 if (FD->hasAttr<Mips16Attr>()) { 4598 Fn->addFnAttr("mips16"); 4599 } 4600 else if (FD->hasAttr<NoMips16Attr>()) { 4601 Fn->addFnAttr("nomips16"); 4602 } 4603 } 4604 4605 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4606 llvm::Value *Address) const; 4607 4608 unsigned getSizeOfUnwindException() const { 4609 return SizeOfUnwindException; 4610 } 4611}; 4612} 4613 4614void MipsABIInfo::CoerceToIntArgs(uint64_t TySize, 4615 SmallVector<llvm::Type*, 8> &ArgList) const { 4616 llvm::IntegerType *IntTy = 4617 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 4618 4619 // Add (TySize / MinABIStackAlignInBytes) args of IntTy. 4620 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N) 4621 ArgList.push_back(IntTy); 4622 4623 // If necessary, add one more integer type to ArgList. 4624 unsigned R = TySize % (MinABIStackAlignInBytes * 8); 4625 4626 if (R) 4627 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R)); 4628} 4629 4630// In N32/64, an aligned double precision floating point field is passed in 4631// a register. 4632llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const { 4633 SmallVector<llvm::Type*, 8> ArgList, IntArgList; 4634 4635 if (IsO32) { 4636 CoerceToIntArgs(TySize, ArgList); 4637 return llvm::StructType::get(getVMContext(), ArgList); 4638 } 4639 4640 if (Ty->isComplexType()) 4641 return CGT.ConvertType(Ty); 4642 4643 const RecordType *RT = Ty->getAs<RecordType>(); 4644 4645 // Unions/vectors are passed in integer registers. 4646 if (!RT || !RT->isStructureOrClassType()) { 4647 CoerceToIntArgs(TySize, ArgList); 4648 return llvm::StructType::get(getVMContext(), ArgList); 4649 } 4650 4651 const RecordDecl *RD = RT->getDecl(); 4652 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 4653 assert(!(TySize % 8) && "Size of structure must be multiple of 8."); 4654 4655 uint64_t LastOffset = 0; 4656 unsigned idx = 0; 4657 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64); 4658 4659 // Iterate over fields in the struct/class and check if there are any aligned 4660 // double fields. 4661 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 4662 i != e; ++i, ++idx) { 4663 const QualType Ty = i->getType(); 4664 const BuiltinType *BT = Ty->getAs<BuiltinType>(); 4665 4666 if (!BT || BT->getKind() != BuiltinType::Double) 4667 continue; 4668 4669 uint64_t Offset = Layout.getFieldOffset(idx); 4670 if (Offset % 64) // Ignore doubles that are not aligned. 4671 continue; 4672 4673 // Add ((Offset - LastOffset) / 64) args of type i64. 4674 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j) 4675 ArgList.push_back(I64); 4676 4677 // Add double type. 4678 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext())); 4679 LastOffset = Offset + 64; 4680 } 4681 4682 CoerceToIntArgs(TySize - LastOffset, IntArgList); 4683 ArgList.append(IntArgList.begin(), IntArgList.end()); 4684 4685 return llvm::StructType::get(getVMContext(), ArgList); 4686} 4687 4688llvm::Type *MipsABIInfo::getPaddingType(uint64_t Align, uint64_t Offset) const { 4689 assert((Offset % MinABIStackAlignInBytes) == 0); 4690 4691 if ((Align - 1) & Offset) 4692 return llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 4693 4694 return 0; 4695} 4696 4697ABIArgInfo 4698MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const { 4699 uint64_t OrigOffset = Offset; 4700 uint64_t TySize = getContext().getTypeSize(Ty); 4701 uint64_t Align = getContext().getTypeAlign(Ty) / 8; 4702 4703 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes), 4704 (uint64_t)StackAlignInBytes); 4705 Offset = llvm::RoundUpToAlignment(Offset, Align); 4706 Offset += llvm::RoundUpToAlignment(TySize, Align * 8) / 8; 4707 4708 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) { 4709 // Ignore empty aggregates. 4710 if (TySize == 0) 4711 return ABIArgInfo::getIgnore(); 4712 4713 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) { 4714 Offset = OrigOffset + MinABIStackAlignInBytes; 4715 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 4716 } 4717 4718 // If we have reached here, aggregates are passed directly by coercing to 4719 // another structure type. Padding is inserted if the offset of the 4720 // aggregate is unaligned. 4721 return ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0, 4722 getPaddingType(Align, OrigOffset)); 4723 } 4724 4725 // Treat an enum type as its underlying type. 4726 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4727 Ty = EnumTy->getDecl()->getIntegerType(); 4728 4729 if (Ty->isPromotableIntegerType()) 4730 return ABIArgInfo::getExtend(); 4731 4732 return ABIArgInfo::getDirect(0, 0, 4733 IsO32 ? 0 : getPaddingType(Align, OrigOffset)); 4734} 4735 4736llvm::Type* 4737MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const { 4738 const RecordType *RT = RetTy->getAs<RecordType>(); 4739 SmallVector<llvm::Type*, 8> RTList; 4740 4741 if (RT && RT->isStructureOrClassType()) { 4742 const RecordDecl *RD = RT->getDecl(); 4743 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 4744 unsigned FieldCnt = Layout.getFieldCount(); 4745 4746 // N32/64 returns struct/classes in floating point registers if the 4747 // following conditions are met: 4748 // 1. The size of the struct/class is no larger than 128-bit. 4749 // 2. The struct/class has one or two fields all of which are floating 4750 // point types. 4751 // 3. The offset of the first field is zero (this follows what gcc does). 4752 // 4753 // Any other composite results are returned in integer registers. 4754 // 4755 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) { 4756 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end(); 4757 for (; b != e; ++b) { 4758 const BuiltinType *BT = b->getType()->getAs<BuiltinType>(); 4759 4760 if (!BT || !BT->isFloatingPoint()) 4761 break; 4762 4763 RTList.push_back(CGT.ConvertType(b->getType())); 4764 } 4765 4766 if (b == e) 4767 return llvm::StructType::get(getVMContext(), RTList, 4768 RD->hasAttr<PackedAttr>()); 4769 4770 RTList.clear(); 4771 } 4772 } 4773 4774 CoerceToIntArgs(Size, RTList); 4775 return llvm::StructType::get(getVMContext(), RTList); 4776} 4777 4778ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const { 4779 uint64_t Size = getContext().getTypeSize(RetTy); 4780 4781 if (RetTy->isVoidType() || Size == 0) 4782 return ABIArgInfo::getIgnore(); 4783 4784 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) { 4785 if (isRecordReturnIndirect(RetTy, CGT)) 4786 return ABIArgInfo::getIndirect(0); 4787 4788 if (Size <= 128) { 4789 if (RetTy->isAnyComplexType()) 4790 return ABIArgInfo::getDirect(); 4791 4792 // O32 returns integer vectors in registers. 4793 if (IsO32 && RetTy->isVectorType() && !RetTy->hasFloatingRepresentation()) 4794 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 4795 4796 if (!IsO32) 4797 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 4798 } 4799 4800 return ABIArgInfo::getIndirect(0); 4801 } 4802 4803 // Treat an enum type as its underlying type. 4804 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 4805 RetTy = EnumTy->getDecl()->getIntegerType(); 4806 4807 return (RetTy->isPromotableIntegerType() ? 4808 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4809} 4810 4811void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const { 4812 ABIArgInfo &RetInfo = FI.getReturnInfo(); 4813 RetInfo = classifyReturnType(FI.getReturnType()); 4814 4815 // Check if a pointer to an aggregate is passed as a hidden argument. 4816 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0; 4817 4818 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4819 it != ie; ++it) 4820 it->info = classifyArgumentType(it->type, Offset); 4821} 4822 4823llvm::Value* MipsABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4824 CodeGenFunction &CGF) const { 4825 llvm::Type *BP = CGF.Int8PtrTy; 4826 llvm::Type *BPP = CGF.Int8PtrPtrTy; 4827 4828 CGBuilderTy &Builder = CGF.Builder; 4829 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 4830 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 4831 int64_t TypeAlign = getContext().getTypeAlign(Ty) / 8; 4832 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 4833 llvm::Value *AddrTyped; 4834 unsigned PtrWidth = getTarget().getPointerWidth(0); 4835 llvm::IntegerType *IntTy = (PtrWidth == 32) ? CGF.Int32Ty : CGF.Int64Ty; 4836 4837 if (TypeAlign > MinABIStackAlignInBytes) { 4838 llvm::Value *AddrAsInt = CGF.Builder.CreatePtrToInt(Addr, IntTy); 4839 llvm::Value *Inc = llvm::ConstantInt::get(IntTy, TypeAlign - 1); 4840 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign); 4841 llvm::Value *Add = CGF.Builder.CreateAdd(AddrAsInt, Inc); 4842 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask); 4843 AddrTyped = CGF.Builder.CreateIntToPtr(And, PTy); 4844 } 4845 else 4846 AddrTyped = Builder.CreateBitCast(Addr, PTy); 4847 4848 llvm::Value *AlignedAddr = Builder.CreateBitCast(AddrTyped, BP); 4849 TypeAlign = std::max((unsigned)TypeAlign, MinABIStackAlignInBytes); 4850 uint64_t Offset = 4851 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, TypeAlign); 4852 llvm::Value *NextAddr = 4853 Builder.CreateGEP(AlignedAddr, llvm::ConstantInt::get(IntTy, Offset), 4854 "ap.next"); 4855 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 4856 4857 return AddrTyped; 4858} 4859 4860bool 4861MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4862 llvm::Value *Address) const { 4863 // This information comes from gcc's implementation, which seems to 4864 // as canonical as it gets. 4865 4866 // Everything on MIPS is 4 bytes. Double-precision FP registers 4867 // are aliased to pairs of single-precision FP registers. 4868 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 4869 4870 // 0-31 are the general purpose registers, $0 - $31. 4871 // 32-63 are the floating-point registers, $f0 - $f31. 4872 // 64 and 65 are the multiply/divide registers, $hi and $lo. 4873 // 66 is the (notional, I think) register for signal-handler return. 4874 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65); 4875 4876 // 67-74 are the floating-point status registers, $fcc0 - $fcc7. 4877 // They are one bit wide and ignored here. 4878 4879 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31. 4880 // (coprocessor 1 is the FP unit) 4881 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31. 4882 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31. 4883 // 176-181 are the DSP accumulator registers. 4884 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181); 4885 return false; 4886} 4887 4888//===----------------------------------------------------------------------===// 4889// TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults. 4890// Currently subclassed only to implement custom OpenCL C function attribute 4891// handling. 4892//===----------------------------------------------------------------------===// 4893 4894namespace { 4895 4896class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo { 4897public: 4898 TCETargetCodeGenInfo(CodeGenTypes &CGT) 4899 : DefaultTargetCodeGenInfo(CGT) {} 4900 4901 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4902 CodeGen::CodeGenModule &M) const; 4903}; 4904 4905void TCETargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4906 llvm::GlobalValue *GV, 4907 CodeGen::CodeGenModule &M) const { 4908 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4909 if (!FD) return; 4910 4911 llvm::Function *F = cast<llvm::Function>(GV); 4912 4913 if (M.getLangOpts().OpenCL) { 4914 if (FD->hasAttr<OpenCLKernelAttr>()) { 4915 // OpenCL C Kernel functions are not subject to inlining 4916 F->addFnAttr(llvm::Attribute::NoInline); 4917 4918 if (FD->hasAttr<ReqdWorkGroupSizeAttr>()) { 4919 4920 // Convert the reqd_work_group_size() attributes to metadata. 4921 llvm::LLVMContext &Context = F->getContext(); 4922 llvm::NamedMDNode *OpenCLMetadata = 4923 M.getModule().getOrInsertNamedMetadata("opencl.kernel_wg_size_info"); 4924 4925 SmallVector<llvm::Value*, 5> Operands; 4926 Operands.push_back(F); 4927 4928 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4929 llvm::APInt(32, 4930 FD->getAttr<ReqdWorkGroupSizeAttr>()->getXDim()))); 4931 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4932 llvm::APInt(32, 4933 FD->getAttr<ReqdWorkGroupSizeAttr>()->getYDim()))); 4934 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4935 llvm::APInt(32, 4936 FD->getAttr<ReqdWorkGroupSizeAttr>()->getZDim()))); 4937 4938 // Add a boolean constant operand for "required" (true) or "hint" (false) 4939 // for implementing the work_group_size_hint attr later. Currently 4940 // always true as the hint is not yet implemented. 4941 Operands.push_back(llvm::ConstantInt::getTrue(Context)); 4942 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands)); 4943 } 4944 } 4945 } 4946} 4947 4948} 4949 4950//===----------------------------------------------------------------------===// 4951// Hexagon ABI Implementation 4952//===----------------------------------------------------------------------===// 4953 4954namespace { 4955 4956class HexagonABIInfo : public ABIInfo { 4957 4958 4959public: 4960 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4961 4962private: 4963 4964 ABIArgInfo classifyReturnType(QualType RetTy) const; 4965 ABIArgInfo classifyArgumentType(QualType RetTy) const; 4966 4967 virtual void computeInfo(CGFunctionInfo &FI) const; 4968 4969 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4970 CodeGenFunction &CGF) const; 4971}; 4972 4973class HexagonTargetCodeGenInfo : public TargetCodeGenInfo { 4974public: 4975 HexagonTargetCodeGenInfo(CodeGenTypes &CGT) 4976 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} 4977 4978 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 4979 return 29; 4980 } 4981}; 4982 4983} 4984 4985void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const { 4986 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4987 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4988 it != ie; ++it) 4989 it->info = classifyArgumentType(it->type); 4990} 4991 4992ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { 4993 if (!isAggregateTypeForABI(Ty)) { 4994 // Treat an enum type as its underlying type. 4995 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4996 Ty = EnumTy->getDecl()->getIntegerType(); 4997 4998 return (Ty->isPromotableIntegerType() ? 4999 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 5000 } 5001 5002 // Ignore empty records. 5003 if (isEmptyRecord(getContext(), Ty, true)) 5004 return ABIArgInfo::getIgnore(); 5005 5006 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, CGT)) 5007 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 5008 5009 uint64_t Size = getContext().getTypeSize(Ty); 5010 if (Size > 64) 5011 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 5012 // Pass in the smallest viable integer type. 5013 else if (Size > 32) 5014 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 5015 else if (Size > 16) 5016 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 5017 else if (Size > 8) 5018 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 5019 else 5020 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 5021} 5022 5023ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const { 5024 if (RetTy->isVoidType()) 5025 return ABIArgInfo::getIgnore(); 5026 5027 // Large vector types should be returned via memory. 5028 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64) 5029 return ABIArgInfo::getIndirect(0); 5030 5031 if (!isAggregateTypeForABI(RetTy)) { 5032 // Treat an enum type as its underlying type. 5033 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 5034 RetTy = EnumTy->getDecl()->getIntegerType(); 5035 5036 return (RetTy->isPromotableIntegerType() ? 5037 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 5038 } 5039 5040 // Structures with either a non-trivial destructor or a non-trivial 5041 // copy constructor are always indirect. 5042 if (isRecordReturnIndirect(RetTy, CGT)) 5043 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 5044 5045 if (isEmptyRecord(getContext(), RetTy, true)) 5046 return ABIArgInfo::getIgnore(); 5047 5048 // Aggregates <= 8 bytes are returned in r0; other aggregates 5049 // are returned indirectly. 5050 uint64_t Size = getContext().getTypeSize(RetTy); 5051 if (Size <= 64) { 5052 // Return in the smallest viable integer type. 5053 if (Size <= 8) 5054 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 5055 if (Size <= 16) 5056 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 5057 if (Size <= 32) 5058 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 5059 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 5060 } 5061 5062 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 5063} 5064 5065llvm::Value *HexagonABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5066 CodeGenFunction &CGF) const { 5067 // FIXME: Need to handle alignment 5068 llvm::Type *BPP = CGF.Int8PtrPtrTy; 5069 5070 CGBuilderTy &Builder = CGF.Builder; 5071 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 5072 "ap"); 5073 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 5074 llvm::Type *PTy = 5075 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 5076 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 5077 5078 uint64_t Offset = 5079 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 4); 5080 llvm::Value *NextAddr = 5081 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 5082 "ap.next"); 5083 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 5084 5085 return AddrTyped; 5086} 5087 5088 5089const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() { 5090 if (TheTargetCodeGenInfo) 5091 return *TheTargetCodeGenInfo; 5092 5093 const llvm::Triple &Triple = getTarget().getTriple(); 5094 switch (Triple.getArch()) { 5095 default: 5096 return *(TheTargetCodeGenInfo = new DefaultTargetCodeGenInfo(Types)); 5097 5098 case llvm::Triple::le32: 5099 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types)); 5100 case llvm::Triple::mips: 5101 case llvm::Triple::mipsel: 5102 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, true)); 5103 5104 case llvm::Triple::mips64: 5105 case llvm::Triple::mips64el: 5106 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false)); 5107 5108 case llvm::Triple::aarch64: 5109 return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types)); 5110 5111 case llvm::Triple::arm: 5112 case llvm::Triple::thumb: 5113 { 5114 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS; 5115 if (strcmp(getTarget().getABI(), "apcs-gnu") == 0) 5116 Kind = ARMABIInfo::APCS; 5117 else if (CodeGenOpts.FloatABI == "hard" || 5118 (CodeGenOpts.FloatABI != "soft" && 5119 Triple.getEnvironment() == llvm::Triple::GNUEABIHF)) 5120 Kind = ARMABIInfo::AAPCS_VFP; 5121 5122 switch (Triple.getOS()) { 5123 case llvm::Triple::NaCl: 5124 return *(TheTargetCodeGenInfo = 5125 new NaClARMTargetCodeGenInfo(Types, Kind)); 5126 default: 5127 return *(TheTargetCodeGenInfo = 5128 new ARMTargetCodeGenInfo(Types, Kind)); 5129 } 5130 } 5131 5132 case llvm::Triple::ppc: 5133 return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types)); 5134 case llvm::Triple::ppc64: 5135 if (Triple.isOSBinFormatELF()) 5136 return *(TheTargetCodeGenInfo = new PPC64_SVR4_TargetCodeGenInfo(Types)); 5137 else 5138 return *(TheTargetCodeGenInfo = new PPC64TargetCodeGenInfo(Types)); 5139 5140 case llvm::Triple::nvptx: 5141 case llvm::Triple::nvptx64: 5142 return *(TheTargetCodeGenInfo = new NVPTXTargetCodeGenInfo(Types)); 5143 5144 case llvm::Triple::mblaze: 5145 return *(TheTargetCodeGenInfo = new MBlazeTargetCodeGenInfo(Types)); 5146 5147 case llvm::Triple::msp430: 5148 return *(TheTargetCodeGenInfo = new MSP430TargetCodeGenInfo(Types)); 5149 5150 case llvm::Triple::systemz: 5151 return *(TheTargetCodeGenInfo = new SystemZTargetCodeGenInfo(Types)); 5152 5153 case llvm::Triple::tce: 5154 return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types)); 5155 5156 case llvm::Triple::x86: { 5157 if (Triple.isOSDarwin()) 5158 return *(TheTargetCodeGenInfo = 5159 new X86_32TargetCodeGenInfo(Types, true, true, false, 5160 CodeGenOpts.NumRegisterParameters)); 5161 5162 switch (Triple.getOS()) { 5163 case llvm::Triple::Cygwin: 5164 case llvm::Triple::MinGW32: 5165 case llvm::Triple::AuroraUX: 5166 case llvm::Triple::DragonFly: 5167 case llvm::Triple::FreeBSD: 5168 case llvm::Triple::OpenBSD: 5169 case llvm::Triple::Bitrig: 5170 return *(TheTargetCodeGenInfo = 5171 new X86_32TargetCodeGenInfo(Types, false, true, false, 5172 CodeGenOpts.NumRegisterParameters)); 5173 5174 case llvm::Triple::Win32: 5175 return *(TheTargetCodeGenInfo = 5176 new X86_32TargetCodeGenInfo(Types, false, true, true, 5177 CodeGenOpts.NumRegisterParameters)); 5178 5179 default: 5180 return *(TheTargetCodeGenInfo = 5181 new X86_32TargetCodeGenInfo(Types, false, false, false, 5182 CodeGenOpts.NumRegisterParameters)); 5183 } 5184 } 5185 5186 case llvm::Triple::x86_64: { 5187 bool HasAVX = strcmp(getTarget().getABI(), "avx") == 0; 5188 5189 switch (Triple.getOS()) { 5190 case llvm::Triple::Win32: 5191 case llvm::Triple::MinGW32: 5192 case llvm::Triple::Cygwin: 5193 return *(TheTargetCodeGenInfo = new WinX86_64TargetCodeGenInfo(Types)); 5194 case llvm::Triple::NaCl: 5195 return *(TheTargetCodeGenInfo = new NaClX86_64TargetCodeGenInfo(Types, 5196 HasAVX)); 5197 default: 5198 return *(TheTargetCodeGenInfo = new X86_64TargetCodeGenInfo(Types, 5199 HasAVX)); 5200 } 5201 } 5202 case llvm::Triple::hexagon: 5203 return *(TheTargetCodeGenInfo = new HexagonTargetCodeGenInfo(Types)); 5204 } 5205} 5206