X86InstrInfo.h revision 202375
1193323Sed//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the X86 implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#ifndef X86INSTRUCTIONINFO_H 15193323Sed#define X86INSTRUCTIONINFO_H 16193323Sed 17193323Sed#include "llvm/Target/TargetInstrInfo.h" 18193323Sed#include "X86.h" 19193323Sed#include "X86RegisterInfo.h" 20193323Sed#include "llvm/ADT/DenseMap.h" 21193323Sed#include "llvm/Target/TargetRegisterInfo.h" 22193323Sed 23193323Sednamespace llvm { 24193323Sed class X86RegisterInfo; 25193323Sed class X86TargetMachine; 26193323Sed 27193323Sednamespace X86 { 28193323Sed // X86 specific condition code. These correspond to X86_*_COND in 29193323Sed // X86InstrInfo.td. They must be kept in synch. 30193323Sed enum CondCode { 31193323Sed COND_A = 0, 32193323Sed COND_AE = 1, 33193323Sed COND_B = 2, 34193323Sed COND_BE = 3, 35193323Sed COND_E = 4, 36193323Sed COND_G = 5, 37193323Sed COND_GE = 6, 38193323Sed COND_L = 7, 39193323Sed COND_LE = 8, 40193323Sed COND_NE = 9, 41193323Sed COND_NO = 10, 42193323Sed COND_NP = 11, 43193323Sed COND_NS = 12, 44193323Sed COND_O = 13, 45193323Sed COND_P = 14, 46193323Sed COND_S = 15, 47193323Sed 48193323Sed // Artificial condition codes. These are used by AnalyzeBranch 49193323Sed // to indicate a block terminated with two conditional branches to 50193323Sed // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51193323Sed // which can't be represented on x86 with a single condition. These 52193323Sed // are never used in MachineInstrs. 53193323Sed COND_NE_OR_P, 54193323Sed COND_NP_OR_E, 55193323Sed 56193323Sed COND_INVALID 57193323Sed }; 58193323Sed 59193323Sed // Turn condition code into conditional branch opcode. 60193323Sed unsigned GetCondBranchFromCond(CondCode CC); 61193323Sed 62193323Sed /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63193323Sed /// e.g. turning COND_E to COND_NE. 64193323Sed CondCode GetOppositeBranchCondition(X86::CondCode CC); 65193323Sed 66193323Sed} 67193323Sed 68193323Sed/// X86II - This namespace holds all of the target specific flags that 69193323Sed/// instruction info tracks. 70193323Sed/// 71193323Sednamespace X86II { 72198090Srdivacky /// Target Operand Flag enum. 73198090Srdivacky enum TOF { 74193323Sed //===------------------------------------------------------------------===// 75195098Sed // X86 Specific MachineOperand flags. 76195098Sed 77198090Srdivacky MO_NO_FLAG, 78195098Sed 79195098Sed /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 80195098Sed /// relocation of: 81195098Sed /// SYMBOL_LABEL + [. - PICBASELABEL] 82198090Srdivacky MO_GOT_ABSOLUTE_ADDRESS, 83195098Sed 84195098Sed /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 85195098Sed /// immediate should get the value of the symbol minus the PIC base label: 86195098Sed /// SYMBOL_LABEL - PICBASELABEL 87198090Srdivacky MO_PIC_BASE_OFFSET, 88195098Sed 89195098Sed /// MO_GOT - On a symbol operand this indicates that the immediate is the 90195098Sed /// offset to the GOT entry for the symbol name from the base of the GOT. 91195098Sed /// 92195098Sed /// See the X86-64 ELF ABI supplement for more details. 93195098Sed /// SYMBOL_LABEL @GOT 94198090Srdivacky MO_GOT, 95195098Sed 96195098Sed /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 97195098Sed /// the offset to the location of the symbol name from the base of the GOT. 98195098Sed /// 99195098Sed /// See the X86-64 ELF ABI supplement for more details. 100195098Sed /// SYMBOL_LABEL @GOTOFF 101198090Srdivacky MO_GOTOFF, 102195098Sed 103195098Sed /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 104195098Sed /// offset to the GOT entry for the symbol name from the current code 105195098Sed /// location. 106195098Sed /// 107195098Sed /// See the X86-64 ELF ABI supplement for more details. 108195098Sed /// SYMBOL_LABEL @GOTPCREL 109198090Srdivacky MO_GOTPCREL, 110195098Sed 111195098Sed /// MO_PLT - On a symbol operand this indicates that the immediate is 112195098Sed /// offset to the PLT entry of symbol name from the current code location. 113195098Sed /// 114195098Sed /// See the X86-64 ELF ABI supplement for more details. 115195098Sed /// SYMBOL_LABEL @PLT 116198090Srdivacky MO_PLT, 117195098Sed 118195098Sed /// MO_TLSGD - On a symbol operand this indicates that the immediate is 119195098Sed /// some TLS offset. 120195098Sed /// 121195098Sed /// See 'ELF Handling for Thread-Local Storage' for more details. 122195098Sed /// SYMBOL_LABEL @TLSGD 123198090Srdivacky MO_TLSGD, 124195098Sed 125195098Sed /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 126195098Sed /// some TLS offset. 127195098Sed /// 128195098Sed /// See 'ELF Handling for Thread-Local Storage' for more details. 129195098Sed /// SYMBOL_LABEL @GOTTPOFF 130198090Srdivacky MO_GOTTPOFF, 131195098Sed 132195098Sed /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 133195098Sed /// some TLS offset. 134195098Sed /// 135195098Sed /// See 'ELF Handling for Thread-Local Storage' for more details. 136195098Sed /// SYMBOL_LABEL @INDNTPOFF 137198090Srdivacky MO_INDNTPOFF, 138195098Sed 139195098Sed /// MO_TPOFF - On a symbol operand this indicates that the immediate is 140195098Sed /// some TLS offset. 141195098Sed /// 142195098Sed /// See 'ELF Handling for Thread-Local Storage' for more details. 143195098Sed /// SYMBOL_LABEL @TPOFF 144198090Srdivacky MO_TPOFF, 145195098Sed 146195098Sed /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 147195098Sed /// some TLS offset. 148195098Sed /// 149195098Sed /// See 'ELF Handling for Thread-Local Storage' for more details. 150195098Sed /// SYMBOL_LABEL @NTPOFF 151198090Srdivacky MO_NTPOFF, 152195098Sed 153198090Srdivacky /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 154198090Srdivacky /// reference is actually to the "__imp_FOO" symbol. This is used for 155198090Srdivacky /// dllimport linkage on windows. 156198090Srdivacky MO_DLLIMPORT, 157198090Srdivacky 158198090Srdivacky /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 159198090Srdivacky /// reference is actually to the "FOO$stub" symbol. This is used for calls 160198090Srdivacky /// and jumps to external functions on Tiger and before. 161198090Srdivacky MO_DARWIN_STUB, 162198090Srdivacky 163198090Srdivacky /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 164198090Srdivacky /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 165198090Srdivacky /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 166198090Srdivacky MO_DARWIN_NONLAZY, 167198090Srdivacky 168198090Srdivacky /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 169198090Srdivacky /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 170198090Srdivacky /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 171198090Srdivacky MO_DARWIN_NONLAZY_PIC_BASE, 172198090Srdivacky 173198090Srdivacky /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 174198090Srdivacky /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 175198090Srdivacky /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 176198090Srdivacky /// stub. 177198090Srdivacky MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE 178198090Srdivacky }; 179198090Srdivacky} 180198090Srdivacky 181198090Srdivacky/// isGlobalStubReference - Return true if the specified TargetFlag operand is 182198090Srdivacky/// a reference to a stub for a global, not the global itself. 183198090Srdivackyinline static bool isGlobalStubReference(unsigned char TargetFlag) { 184198090Srdivacky switch (TargetFlag) { 185198090Srdivacky case X86II::MO_DLLIMPORT: // dllimport stub. 186198090Srdivacky case X86II::MO_GOTPCREL: // rip-relative GOT reference. 187198090Srdivacky case X86II::MO_GOT: // normal GOT reference. 188198090Srdivacky case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 189198090Srdivacky case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 190198090Srdivacky case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 191198090Srdivacky return true; 192198090Srdivacky default: 193198090Srdivacky return false; 194198090Srdivacky } 195198090Srdivacky} 196198090Srdivacky 197198090Srdivacky/// isGlobalRelativeToPICBase - Return true if the specified global value 198198090Srdivacky/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 199198090Srdivacky/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 200198090Srdivackyinline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 201198090Srdivacky switch (TargetFlag) { 202198090Srdivacky case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 203198090Srdivacky case X86II::MO_GOT: // isPICStyleGOT: other global. 204198090Srdivacky case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 205198090Srdivacky case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 206198090Srdivacky case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 207198090Srdivacky return true; 208198090Srdivacky default: 209198090Srdivacky return false; 210198090Srdivacky } 211198090Srdivacky} 212198090Srdivacky 213198090Srdivacky/// X86II - This namespace holds all of the target specific flags that 214198090Srdivacky/// instruction info tracks. 215198090Srdivacky/// 216198090Srdivackynamespace X86II { 217198090Srdivacky enum { 218195098Sed //===------------------------------------------------------------------===// 219195098Sed // Instruction encodings. These are the standard/most common forms for X86 220193323Sed // instructions. 221193323Sed // 222193323Sed 223193323Sed // PseudoFrm - This represents an instruction that is a pseudo instruction 224193323Sed // or one that has not been implemented yet. It is illegal to code generate 225193323Sed // it, but tolerated for intermediate implementation stages. 226193323Sed Pseudo = 0, 227193323Sed 228193323Sed /// Raw - This form is for instructions that don't have any operands, so 229193323Sed /// they are just a fixed opcode value, like 'leave'. 230193323Sed RawFrm = 1, 231193323Sed 232193323Sed /// AddRegFrm - This form is used for instructions like 'push r32' that have 233193323Sed /// their one register operand added to their opcode. 234193323Sed AddRegFrm = 2, 235193323Sed 236193323Sed /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 237193323Sed /// to specify a destination, which in this case is a register. 238193323Sed /// 239193323Sed MRMDestReg = 3, 240193323Sed 241193323Sed /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 242193323Sed /// to specify a destination, which in this case is memory. 243193323Sed /// 244193323Sed MRMDestMem = 4, 245193323Sed 246193323Sed /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 247193323Sed /// to specify a source, which in this case is a register. 248193323Sed /// 249193323Sed MRMSrcReg = 5, 250193323Sed 251193323Sed /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 252193323Sed /// to specify a source, which in this case is memory. 253193323Sed /// 254193323Sed MRMSrcMem = 6, 255193323Sed 256193323Sed /// MRM[0-7][rm] - These forms are used to represent instructions that use 257193323Sed /// a Mod/RM byte, and use the middle field to hold extended opcode 258193323Sed /// information. In the intel manual these are represented as /0, /1, ... 259193323Sed /// 260193323Sed 261193323Sed // First, instructions that operate on a register r/m operand... 262193323Sed MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 263193323Sed MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 264193323Sed 265193323Sed // Next, instructions that operate on a memory r/m operand... 266193323Sed MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 267193323Sed MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 268193323Sed 269193323Sed // MRMInitReg - This form is used for instructions whose source and 270193323Sed // destinations are the same register. 271193323Sed MRMInitReg = 32, 272193323Sed 273193323Sed FormMask = 63, 274193323Sed 275193323Sed //===------------------------------------------------------------------===// 276193323Sed // Actual flags... 277193323Sed 278193323Sed // OpSize - Set if this instruction requires an operand size prefix (0x66), 279193323Sed // which most often indicates that the instruction operates on 16 bit data 280193323Sed // instead of 32 bit data. 281193323Sed OpSize = 1 << 6, 282193323Sed 283193323Sed // AsSize - Set if this instruction requires an operand size prefix (0x67), 284193323Sed // which most often indicates that the instruction address 16 bit address 285193323Sed // instead of 32 bit address (or 32 bit address in 64 bit mode). 286193323Sed AdSize = 1 << 7, 287193323Sed 288193323Sed //===------------------------------------------------------------------===// 289193323Sed // Op0Mask - There are several prefix bytes that are used to form two byte 290193323Sed // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 291193323Sed // used to obtain the setting of this field. If no bits in this field is 292193323Sed // set, there is no prefix byte for obtaining a multibyte opcode. 293193323Sed // 294193323Sed Op0Shift = 8, 295193323Sed Op0Mask = 0xF << Op0Shift, 296193323Sed 297193323Sed // TB - TwoByte - Set if this instruction has a two byte opcode, which 298193323Sed // starts with a 0x0F byte before the real opcode. 299193323Sed TB = 1 << Op0Shift, 300193323Sed 301193323Sed // REP - The 0xF3 prefix byte indicating repetition of the following 302193323Sed // instruction. 303193323Sed REP = 2 << Op0Shift, 304193323Sed 305193323Sed // D8-DF - These escape opcodes are used by the floating point unit. These 306193323Sed // values must remain sequential. 307193323Sed D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 308193323Sed DA = 5 << Op0Shift, DB = 6 << Op0Shift, 309193323Sed DC = 7 << Op0Shift, DD = 8 << Op0Shift, 310193323Sed DE = 9 << Op0Shift, DF = 10 << Op0Shift, 311193323Sed 312193323Sed // XS, XD - These prefix codes are for single and double precision scalar 313193323Sed // floating point operations performed in the SSE registers. 314193323Sed XD = 11 << Op0Shift, XS = 12 << Op0Shift, 315193323Sed 316193323Sed // T8, TA - Prefix after the 0x0F prefix. 317193323Sed T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 318198090Srdivacky 319198090Srdivacky // TF - Prefix before and after 0x0F 320198090Srdivacky TF = 15 << Op0Shift, 321193323Sed 322193323Sed //===------------------------------------------------------------------===// 323193323Sed // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 324193323Sed // They are used to specify GPRs and SSE registers, 64-bit operand size, 325193323Sed // etc. We only cares about REX.W and REX.R bits and only the former is 326193323Sed // statically determined. 327193323Sed // 328193323Sed REXShift = 12, 329193323Sed REX_W = 1 << REXShift, 330193323Sed 331193323Sed //===------------------------------------------------------------------===// 332193323Sed // This three-bit field describes the size of an immediate operand. Zero is 333193323Sed // unused so that we can tell if we forgot to set a value. 334193323Sed ImmShift = 13, 335193323Sed ImmMask = 7 << ImmShift, 336193323Sed Imm8 = 1 << ImmShift, 337193323Sed Imm16 = 2 << ImmShift, 338193323Sed Imm32 = 3 << ImmShift, 339193323Sed Imm64 = 4 << ImmShift, 340193323Sed 341193323Sed //===------------------------------------------------------------------===// 342193323Sed // FP Instruction Classification... Zero is non-fp instruction. 343193323Sed 344193323Sed // FPTypeMask - Mask for all of the FP types... 345193323Sed FPTypeShift = 16, 346193323Sed FPTypeMask = 7 << FPTypeShift, 347193323Sed 348193323Sed // NotFP - The default, set for instructions that do not use FP registers. 349193323Sed NotFP = 0 << FPTypeShift, 350193323Sed 351193323Sed // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 352193323Sed ZeroArgFP = 1 << FPTypeShift, 353193323Sed 354193323Sed // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 355193323Sed OneArgFP = 2 << FPTypeShift, 356193323Sed 357193323Sed // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 358193323Sed // result back to ST(0). For example, fcos, fsqrt, etc. 359193323Sed // 360193323Sed OneArgFPRW = 3 << FPTypeShift, 361193323Sed 362193323Sed // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 363193323Sed // explicit argument, storing the result to either ST(0) or the implicit 364193323Sed // argument. For example: fadd, fsub, fmul, etc... 365193323Sed TwoArgFP = 4 << FPTypeShift, 366193323Sed 367193323Sed // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 368193323Sed // explicit argument, but have no destination. Example: fucom, fucomi, ... 369193323Sed CompareFP = 5 << FPTypeShift, 370193323Sed 371193323Sed // CondMovFP - "2 operand" floating point conditional move instructions. 372193323Sed CondMovFP = 6 << FPTypeShift, 373193323Sed 374193323Sed // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 375193323Sed SpecialFP = 7 << FPTypeShift, 376193323Sed 377193323Sed // Lock prefix 378193323Sed LOCKShift = 19, 379193323Sed LOCK = 1 << LOCKShift, 380193323Sed 381193323Sed // Segment override prefixes. Currently we just need ability to address 382193323Sed // stuff in gs and fs segments. 383193323Sed SegOvrShift = 20, 384193323Sed SegOvrMask = 3 << SegOvrShift, 385193323Sed FS = 1 << SegOvrShift, 386193323Sed GS = 2 << SegOvrShift, 387193323Sed 388193323Sed // Bits 22 -> 23 are unused 389193323Sed OpcodeShift = 24, 390193323Sed OpcodeMask = 0xFF << OpcodeShift 391193323Sed }; 392193323Sed} 393193323Sed 394193323Sedconst int X86AddrNumOperands = 5; 395193323Sed 396193323Sedinline static bool isScale(const MachineOperand &MO) { 397193323Sed return MO.isImm() && 398193323Sed (MO.getImm() == 1 || MO.getImm() == 2 || 399193323Sed MO.getImm() == 4 || MO.getImm() == 8); 400193323Sed} 401193323Sed 402193323Sedinline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 403193323Sed if (MI->getOperand(Op).isFI()) return true; 404193323Sed return Op+4 <= MI->getNumOperands() && 405193323Sed MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 406193323Sed MI->getOperand(Op+2).isReg() && 407193323Sed (MI->getOperand(Op+3).isImm() || 408193323Sed MI->getOperand(Op+3).isGlobal() || 409193323Sed MI->getOperand(Op+3).isCPI() || 410193323Sed MI->getOperand(Op+3).isJTI()); 411193323Sed} 412193323Sed 413193323Sedinline static bool isMem(const MachineInstr *MI, unsigned Op) { 414193323Sed if (MI->getOperand(Op).isFI()) return true; 415193323Sed return Op+5 <= MI->getNumOperands() && 416193323Sed MI->getOperand(Op+4).isReg() && 417193323Sed isLeaMem(MI, Op); 418193323Sed} 419193323Sed 420193323Sedclass X86InstrInfo : public TargetInstrInfoImpl { 421193323Sed X86TargetMachine &TM; 422193323Sed const X86RegisterInfo RI; 423193323Sed 424193323Sed /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 425193323Sed /// RegOp2MemOpTable2 - Load / store folding opcode maps. 426193323Sed /// 427198090Srdivacky DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 428198090Srdivacky DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 429198090Srdivacky DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 430198090Srdivacky DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 431193323Sed 432193323Sed /// MemOp2RegOpTable - Load / store unfolding opcode map. 433193323Sed /// 434193323Sed DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 435193323Sed 436193323Sedpublic: 437193323Sed explicit X86InstrInfo(X86TargetMachine &tm); 438193323Sed 439193323Sed /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 440193323Sed /// such, whenever a client has an instance of instruction info, it should 441193323Sed /// always be able to get register info as well (through this method). 442193323Sed /// 443193323Sed virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 444193323Sed 445193323Sed /// Return true if the instruction is a register to register move and return 446193323Sed /// the source and dest operands and their sub-register indices by reference. 447193323Sed virtual bool isMoveInstr(const MachineInstr &MI, 448193323Sed unsigned &SrcReg, unsigned &DstReg, 449193323Sed unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 450193323Sed 451202375Srdivacky /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 452202375Srdivacky /// extension instruction. That is, it's like a copy where it's legal for the 453202375Srdivacky /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 454202375Srdivacky /// true, then it's expected the pre-extension value is available as a subreg 455202375Srdivacky /// of the result register. This also returns the sub-register index in 456202375Srdivacky /// SubIdx. 457202375Srdivacky virtual bool isCoalescableExtInstr(const MachineInstr &MI, 458202375Srdivacky unsigned &SrcReg, unsigned &DstReg, 459202375Srdivacky unsigned &SubIdx) const; 460202375Srdivacky 461193323Sed unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 462199481Srdivacky /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 463199481Srdivacky /// stack locations as well. This uses a heuristic so it isn't 464199481Srdivacky /// reliable for correctness. 465199481Srdivacky unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 466199481Srdivacky int &FrameIndex) const; 467199481Srdivacky 468199481Srdivacky /// hasLoadFromStackSlot - If the specified machine instruction has 469199481Srdivacky /// a load from a stack slot, return true along with the FrameIndex 470200581Srdivacky /// of the loaded stack slot and the machine mem operand containing 471200581Srdivacky /// the reference. If not, return false. Unlike 472199481Srdivacky /// isLoadFromStackSlot, this returns true for any instructions that 473199481Srdivacky /// loads from the stack. This is a hint only and may not catch all 474199481Srdivacky /// cases. 475200581Srdivacky bool hasLoadFromStackSlot(const MachineInstr *MI, 476200581Srdivacky const MachineMemOperand *&MMO, 477200581Srdivacky int &FrameIndex) const; 478199481Srdivacky 479193323Sed unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 480199481Srdivacky /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 481199481Srdivacky /// stack locations as well. This uses a heuristic so it isn't 482199481Srdivacky /// reliable for correctness. 483199481Srdivacky unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 484199481Srdivacky int &FrameIndex) const; 485193323Sed 486199481Srdivacky /// hasStoreToStackSlot - If the specified machine instruction has a 487199481Srdivacky /// store to a stack slot, return true along with the FrameIndex of 488200581Srdivacky /// the loaded stack slot and the machine mem operand containing the 489200581Srdivacky /// reference. If not, return false. Unlike isStoreToStackSlot, 490200581Srdivacky /// this returns true for any instructions that loads from the 491200581Srdivacky /// stack. This is a hint only and may not catch all cases. 492200581Srdivacky bool hasStoreToStackSlot(const MachineInstr *MI, 493200581Srdivacky const MachineMemOperand *&MMO, 494200581Srdivacky int &FrameIndex) const; 495199481Srdivacky 496198090Srdivacky bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 497198090Srdivacky AliasAnalysis *AA) const; 498193323Sed void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 499198090Srdivacky unsigned DestReg, unsigned SubIdx, 500199481Srdivacky const MachineInstr *Orig, 501199481Srdivacky const TargetRegisterInfo *TRI) const; 502193323Sed 503193323Sed /// convertToThreeAddress - This method must be implemented by targets that 504193323Sed /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 505193323Sed /// may be able to convert a two-address instruction into a true 506193323Sed /// three-address instruction on demand. This allows the X86 target (for 507193323Sed /// example) to convert ADD and SHL instructions into LEA instructions if they 508193323Sed /// would require register copies due to two-addressness. 509193323Sed /// 510193323Sed /// This method returns a null pointer if the transformation cannot be 511193323Sed /// performed, otherwise it returns the new instruction. 512193323Sed /// 513193323Sed virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 514193323Sed MachineBasicBlock::iterator &MBBI, 515193323Sed LiveVariables *LV) const; 516193323Sed 517193323Sed /// commuteInstruction - We have a few instructions that must be hacked on to 518193323Sed /// commute them. 519193323Sed /// 520193323Sed virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 521193323Sed 522193323Sed // Branch analysis. 523193323Sed virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 524193323Sed virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 525193323Sed MachineBasicBlock *&FBB, 526193323Sed SmallVectorImpl<MachineOperand> &Cond, 527193323Sed bool AllowModify) const; 528193323Sed virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 529193323Sed virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 530193323Sed MachineBasicBlock *FBB, 531193323Sed const SmallVectorImpl<MachineOperand> &Cond) const; 532193323Sed virtual bool copyRegToReg(MachineBasicBlock &MBB, 533193323Sed MachineBasicBlock::iterator MI, 534193323Sed unsigned DestReg, unsigned SrcReg, 535193323Sed const TargetRegisterClass *DestRC, 536193323Sed const TargetRegisterClass *SrcRC) const; 537193323Sed virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 538193323Sed MachineBasicBlock::iterator MI, 539193323Sed unsigned SrcReg, bool isKill, int FrameIndex, 540193323Sed const TargetRegisterClass *RC) const; 541193323Sed 542193323Sed virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 543193323Sed SmallVectorImpl<MachineOperand> &Addr, 544193323Sed const TargetRegisterClass *RC, 545198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 546198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 547193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const; 548193323Sed 549193323Sed virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 550193323Sed MachineBasicBlock::iterator MI, 551193323Sed unsigned DestReg, int FrameIndex, 552193323Sed const TargetRegisterClass *RC) const; 553193323Sed 554193323Sed virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 555193323Sed SmallVectorImpl<MachineOperand> &Addr, 556193323Sed const TargetRegisterClass *RC, 557198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 558198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 559193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const; 560193323Sed 561193323Sed virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 562193323Sed MachineBasicBlock::iterator MI, 563193323Sed const std::vector<CalleeSavedInfo> &CSI) const; 564193323Sed 565193323Sed virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 566193323Sed MachineBasicBlock::iterator MI, 567193323Sed const std::vector<CalleeSavedInfo> &CSI) const; 568193323Sed 569193323Sed /// foldMemoryOperand - If this target supports it, fold a load or store of 570193323Sed /// the specified stack slot into the specified machine instruction for the 571193323Sed /// specified operand(s). If this is possible, the target should perform the 572193323Sed /// folding and return true, otherwise it should return false. If it folds 573193323Sed /// the instruction, it is likely that the MachineInstruction the iterator 574193323Sed /// references has been changed. 575193323Sed virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 576193323Sed MachineInstr* MI, 577193323Sed const SmallVectorImpl<unsigned> &Ops, 578193323Sed int FrameIndex) const; 579193323Sed 580193323Sed /// foldMemoryOperand - Same as the previous version except it allows folding 581193323Sed /// of any load and store from / to any address, not just from a specific 582193323Sed /// stack slot. 583193323Sed virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 584193323Sed MachineInstr* MI, 585193323Sed const SmallVectorImpl<unsigned> &Ops, 586193323Sed MachineInstr* LoadMI) const; 587193323Sed 588193323Sed /// canFoldMemoryOperand - Returns true if the specified load / store is 589193323Sed /// folding is possible. 590193323Sed virtual bool canFoldMemoryOperand(const MachineInstr*, 591193323Sed const SmallVectorImpl<unsigned> &) const; 592193323Sed 593193323Sed /// unfoldMemoryOperand - Separate a single instruction which folded a load or 594193323Sed /// a store or a load and a store into two or more instruction. If this is 595193323Sed /// possible, returns true as well as the new instructions by reference. 596193323Sed virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 597193323Sed unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 598193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const; 599193323Sed 600193323Sed virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 601193323Sed SmallVectorImpl<SDNode*> &NewNodes) const; 602193323Sed 603193323Sed /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 604193323Sed /// instruction after load / store are unfolded from an instruction of the 605193323Sed /// specified opcode. It returns zero if the specified unfolding is not 606198892Srdivacky /// possible. If LoadRegIndex is non-null, it is filled in with the operand 607198892Srdivacky /// index of the operand which will hold the register holding the loaded 608198892Srdivacky /// value. 609193323Sed virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 610198892Srdivacky bool UnfoldLoad, bool UnfoldStore, 611198892Srdivacky unsigned *LoadRegIndex = 0) const; 612193323Sed 613193323Sed virtual 614193323Sed bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 615193323Sed 616193323Sed /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 617193323Sed /// instruction that defines the specified register class. 618193323Sed bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 619193323Sed 620193323Sed // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 621193323Sed // specified machine instruction. 622193323Sed // 623193323Sed unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 624193323Sed return TID->TSFlags >> X86II::OpcodeShift; 625193323Sed } 626193323Sed unsigned char getBaseOpcodeFor(unsigned Opcode) const { 627193323Sed return getBaseOpcodeFor(&get(Opcode)); 628193323Sed } 629193323Sed 630193323Sed static bool isX86_64NonExtLowByteReg(unsigned reg) { 631193323Sed return (reg == X86::SPL || reg == X86::BPL || 632193323Sed reg == X86::SIL || reg == X86::DIL); 633193323Sed } 634193323Sed 635193323Sed static unsigned sizeOfImm(const TargetInstrDesc *Desc); 636193323Sed static bool isX86_64ExtendedReg(const MachineOperand &MO); 637193323Sed static unsigned determineREX(const MachineInstr &MI); 638193323Sed 639193323Sed /// GetInstSize - Returns the size of the specified MachineInstr. 640193323Sed /// 641193323Sed virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 642193323Sed 643193323Sed /// getGlobalBaseReg - Return a virtual register initialized with the 644193323Sed /// the global base register value. Output instructions required to 645193323Sed /// initialize the register in the function entry block, if necessary. 646193323Sed /// 647193323Sed unsigned getGlobalBaseReg(MachineFunction *MF) const; 648193323Sed 649193323Sedprivate: 650200581Srdivacky MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 651200581Srdivacky MachineFunction::iterator &MFI, 652200581Srdivacky MachineBasicBlock::iterator &MBBI, 653200581Srdivacky LiveVariables *LV) const; 654200581Srdivacky 655193323Sed MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 656198090Srdivacky MachineInstr* MI, 657198090Srdivacky unsigned OpNum, 658198090Srdivacky const SmallVectorImpl<MachineOperand> &MOs, 659198090Srdivacky unsigned Size, unsigned Alignment) const; 660199481Srdivacky 661199481Srdivacky /// isFrameOperand - Return true and the FrameIndex if the specified 662199481Srdivacky /// operand and follow operands form a reference to the stack frame. 663199481Srdivacky bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 664199481Srdivacky int &FrameIndex) const; 665193323Sed}; 666193323Sed 667193323Sed} // End llvm namespace 668193323Sed 669193323Sed#endif 670