1234353Sdim//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the X86 implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#ifndef X86INSTRUCTIONINFO_H 15193323Sed#define X86INSTRUCTIONINFO_H 16193323Sed 17193323Sed#include "X86.h" 18193323Sed#include "X86RegisterInfo.h" 19193323Sed#include "llvm/ADT/DenseMap.h" 20234353Sdim#include "llvm/Target/TargetInstrInfo.h" 21193323Sed 22224145Sdim#define GET_INSTRINFO_HEADER 23224145Sdim#include "X86GenInstrInfo.inc" 24224145Sdim 25193323Sednamespace llvm { 26193323Sed class X86RegisterInfo; 27193323Sed class X86TargetMachine; 28193323Sed 29193323Sednamespace X86 { 30193323Sed // X86 specific condition code. These correspond to X86_*_COND in 31193323Sed // X86InstrInfo.td. They must be kept in synch. 32193323Sed enum CondCode { 33193323Sed COND_A = 0, 34193323Sed COND_AE = 1, 35193323Sed COND_B = 2, 36193323Sed COND_BE = 3, 37193323Sed COND_E = 4, 38193323Sed COND_G = 5, 39193323Sed COND_GE = 6, 40193323Sed COND_L = 7, 41193323Sed COND_LE = 8, 42193323Sed COND_NE = 9, 43193323Sed COND_NO = 10, 44193323Sed COND_NP = 11, 45193323Sed COND_NS = 12, 46193323Sed COND_O = 13, 47193323Sed COND_P = 14, 48193323Sed COND_S = 15, 49193323Sed 50193323Sed // Artificial condition codes. These are used by AnalyzeBranch 51193323Sed // to indicate a block terminated with two conditional branches to 52193323Sed // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 53193323Sed // which can't be represented on x86 with a single condition. These 54193323Sed // are never used in MachineInstrs. 55193323Sed COND_NE_OR_P, 56193323Sed COND_NP_OR_E, 57193323Sed 58193323Sed COND_INVALID 59193323Sed }; 60221345Sdim 61193323Sed // Turn condition code into conditional branch opcode. 62193323Sed unsigned GetCondBranchFromCond(CondCode CC); 63221345Sdim 64243830Sdim // Turn CMov opcode into condition code. 65243830Sdim CondCode getCondFromCMovOpc(unsigned Opc); 66243830Sdim 67193323Sed /// GetOppositeBranchCondition - Return the inverse of the specified cond, 68193323Sed /// e.g. turning COND_E to COND_NE. 69193323Sed CondCode GetOppositeBranchCondition(X86::CondCode CC); 70226633Sdim} // end namespace X86; 71193323Sed 72221345Sdim 73198090Srdivacky/// isGlobalStubReference - Return true if the specified TargetFlag operand is 74198090Srdivacky/// a reference to a stub for a global, not the global itself. 75198090Srdivackyinline static bool isGlobalStubReference(unsigned char TargetFlag) { 76198090Srdivacky switch (TargetFlag) { 77198090Srdivacky case X86II::MO_DLLIMPORT: // dllimport stub. 78198090Srdivacky case X86II::MO_GOTPCREL: // rip-relative GOT reference. 79198090Srdivacky case X86II::MO_GOT: // normal GOT reference. 80198090Srdivacky case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 81198090Srdivacky case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 82198090Srdivacky case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 83198090Srdivacky return true; 84198090Srdivacky default: 85198090Srdivacky return false; 86198090Srdivacky } 87198090Srdivacky} 88198090Srdivacky 89198090Srdivacky/// isGlobalRelativeToPICBase - Return true if the specified global value 90198090Srdivacky/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 91198090Srdivacky/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 92198090Srdivackyinline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 93198090Srdivacky switch (TargetFlag) { 94198090Srdivacky case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 95198090Srdivacky case X86II::MO_GOT: // isPICStyleGOT: other global. 96198090Srdivacky case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 97198090Srdivacky case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 98198090Srdivacky case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 99210299Sed case X86II::MO_TLVP: // ??? Pretty sure.. 100198090Srdivacky return true; 101198090Srdivacky default: 102198090Srdivacky return false; 103198090Srdivacky } 104198090Srdivacky} 105221345Sdim 106193323Sedinline static bool isScale(const MachineOperand &MO) { 107193323Sed return MO.isImm() && 108193323Sed (MO.getImm() == 1 || MO.getImm() == 2 || 109193323Sed MO.getImm() == 4 || MO.getImm() == 8); 110193323Sed} 111193323Sed 112193323Sedinline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 113193323Sed if (MI->getOperand(Op).isFI()) return true; 114193323Sed return Op+4 <= MI->getNumOperands() && 115193323Sed MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 116193323Sed MI->getOperand(Op+2).isReg() && 117193323Sed (MI->getOperand(Op+3).isImm() || 118193323Sed MI->getOperand(Op+3).isGlobal() || 119193323Sed MI->getOperand(Op+3).isCPI() || 120193323Sed MI->getOperand(Op+3).isJTI()); 121193323Sed} 122193323Sed 123193323Sedinline static bool isMem(const MachineInstr *MI, unsigned Op) { 124193323Sed if (MI->getOperand(Op).isFI()) return true; 125193323Sed return Op+5 <= MI->getNumOperands() && 126193323Sed MI->getOperand(Op+4).isReg() && 127193323Sed isLeaMem(MI, Op); 128193323Sed} 129193323Sed 130224145Sdimclass X86InstrInfo : public X86GenInstrInfo { 131193323Sed X86TargetMachine &TM; 132193323Sed const X86RegisterInfo RI; 133221345Sdim 134239462Sdim /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 135239462Sdim /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps. 136193323Sed /// 137226633Sdim typedef DenseMap<unsigned, 138226633Sdim std::pair<unsigned, unsigned> > RegOp2MemOpTableType; 139226633Sdim RegOp2MemOpTableType RegOp2MemOpTable2Addr; 140226633Sdim RegOp2MemOpTableType RegOp2MemOpTable0; 141226633Sdim RegOp2MemOpTableType RegOp2MemOpTable1; 142226633Sdim RegOp2MemOpTableType RegOp2MemOpTable2; 143239462Sdim RegOp2MemOpTableType RegOp2MemOpTable3; 144221345Sdim 145193323Sed /// MemOp2RegOpTable - Load / store unfolding opcode map. 146193323Sed /// 147226633Sdim typedef DenseMap<unsigned, 148226633Sdim std::pair<unsigned, unsigned> > MemOp2RegOpTableType; 149226633Sdim MemOp2RegOpTableType MemOp2RegOpTable; 150206083Srdivacky 151239462Sdim static void AddTableEntry(RegOp2MemOpTableType &R2MTable, 152239462Sdim MemOp2RegOpTableType &M2RTable, 153239462Sdim unsigned RegOp, unsigned MemOp, unsigned Flags); 154226633Sdim 155263508Sdim virtual void anchor(); 156263508Sdim 157193323Sedpublic: 158193323Sed explicit X86InstrInfo(X86TargetMachine &tm); 159193323Sed 160193323Sed /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 161193323Sed /// such, whenever a client has an instance of instruction info, it should 162193323Sed /// always be able to get register info as well (through this method). 163193323Sed /// 164193323Sed virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 165193323Sed 166202375Srdivacky /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 167202375Srdivacky /// extension instruction. That is, it's like a copy where it's legal for the 168202375Srdivacky /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 169202375Srdivacky /// true, then it's expected the pre-extension value is available as a subreg 170202375Srdivacky /// of the result register. This also returns the sub-register index in 171202375Srdivacky /// SubIdx. 172202375Srdivacky virtual bool isCoalescableExtInstr(const MachineInstr &MI, 173202375Srdivacky unsigned &SrcReg, unsigned &DstReg, 174202375Srdivacky unsigned &SubIdx) const; 175202375Srdivacky 176193323Sed unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 177199481Srdivacky /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 178199481Srdivacky /// stack locations as well. This uses a heuristic so it isn't 179199481Srdivacky /// reliable for correctness. 180199481Srdivacky unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 181199481Srdivacky int &FrameIndex) const; 182199481Srdivacky 183193323Sed unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 184199481Srdivacky /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 185199481Srdivacky /// stack locations as well. This uses a heuristic so it isn't 186199481Srdivacky /// reliable for correctness. 187199481Srdivacky unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 188199481Srdivacky int &FrameIndex) const; 189193323Sed 190198090Srdivacky bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 191198090Srdivacky AliasAnalysis *AA) const; 192193323Sed void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 193198090Srdivacky unsigned DestReg, unsigned SubIdx, 194199481Srdivacky const MachineInstr *Orig, 195210299Sed const TargetRegisterInfo &TRI) const; 196193323Sed 197263508Sdim /// Given an operand within a MachineInstr, insert preceding code to put it 198263508Sdim /// into the right format for a particular kind of LEA instruction. This may 199263508Sdim /// involve using an appropriate super-register instead (with an implicit use 200263508Sdim /// of the original) or creating a new virtual register and inserting COPY 201263508Sdim /// instructions to get the data into the right class. 202263508Sdim /// 203263508Sdim /// Reference parameters are set to indicate how caller should add this 204263508Sdim /// operand to the LEA instruction. 205263508Sdim bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, 206263508Sdim unsigned LEAOpcode, bool AllowSP, 207263508Sdim unsigned &NewSrc, bool &isKill, 208263508Sdim bool &isUndef, MachineOperand &ImplicitOp) const; 209263508Sdim 210193323Sed /// convertToThreeAddress - This method must be implemented by targets that 211193323Sed /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 212193323Sed /// may be able to convert a two-address instruction into a true 213193323Sed /// three-address instruction on demand. This allows the X86 target (for 214193323Sed /// example) to convert ADD and SHL instructions into LEA instructions if they 215193323Sed /// would require register copies due to two-addressness. 216193323Sed /// 217193323Sed /// This method returns a null pointer if the transformation cannot be 218193323Sed /// performed, otherwise it returns the new instruction. 219193323Sed /// 220193323Sed virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 221193323Sed MachineBasicBlock::iterator &MBBI, 222193323Sed LiveVariables *LV) const; 223193323Sed 224193323Sed /// commuteInstruction - We have a few instructions that must be hacked on to 225193323Sed /// commute them. 226193323Sed /// 227193323Sed virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 228193323Sed 229193323Sed // Branch analysis. 230193323Sed virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 231193323Sed virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 232193323Sed MachineBasicBlock *&FBB, 233193323Sed SmallVectorImpl<MachineOperand> &Cond, 234193323Sed bool AllowModify) const; 235193323Sed virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 236193323Sed virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 237193323Sed MachineBasicBlock *FBB, 238210299Sed const SmallVectorImpl<MachineOperand> &Cond, 239210299Sed DebugLoc DL) const; 240239462Sdim virtual bool canInsertSelect(const MachineBasicBlock&, 241239462Sdim const SmallVectorImpl<MachineOperand> &Cond, 242239462Sdim unsigned, unsigned, int&, int&, int&) const; 243239462Sdim virtual void insertSelect(MachineBasicBlock &MBB, 244239462Sdim MachineBasicBlock::iterator MI, DebugLoc DL, 245239462Sdim unsigned DstReg, 246239462Sdim const SmallVectorImpl<MachineOperand> &Cond, 247239462Sdim unsigned TrueReg, unsigned FalseReg) const; 248210299Sed virtual void copyPhysReg(MachineBasicBlock &MBB, 249210299Sed MachineBasicBlock::iterator MI, DebugLoc DL, 250210299Sed unsigned DestReg, unsigned SrcReg, 251210299Sed bool KillSrc) const; 252193323Sed virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 253193323Sed MachineBasicBlock::iterator MI, 254193323Sed unsigned SrcReg, bool isKill, int FrameIndex, 255208599Srdivacky const TargetRegisterClass *RC, 256208599Srdivacky const TargetRegisterInfo *TRI) const; 257193323Sed 258193323Sed virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 259193323Sed SmallVectorImpl<MachineOperand> &Addr, 260193323Sed const TargetRegisterClass *RC, 261198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 262198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 263193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const; 264193323Sed 265193323Sed virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 266193323Sed MachineBasicBlock::iterator MI, 267193323Sed unsigned DestReg, int FrameIndex, 268208599Srdivacky const TargetRegisterClass *RC, 269208599Srdivacky const TargetRegisterInfo *TRI) const; 270193323Sed 271193323Sed virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 272193323Sed SmallVectorImpl<MachineOperand> &Addr, 273193323Sed const TargetRegisterClass *RC, 274198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 275198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 276193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const; 277226633Sdim 278226633Sdim virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 279226633Sdim 280193323Sed /// foldMemoryOperand - If this target supports it, fold a load or store of 281193323Sed /// the specified stack slot into the specified machine instruction for the 282193323Sed /// specified operand(s). If this is possible, the target should perform the 283193323Sed /// folding and return true, otherwise it should return false. If it folds 284193323Sed /// the instruction, it is likely that the MachineInstruction the iterator 285193323Sed /// references has been changed. 286193323Sed virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 287193323Sed MachineInstr* MI, 288193323Sed const SmallVectorImpl<unsigned> &Ops, 289193323Sed int FrameIndex) const; 290193323Sed 291193323Sed /// foldMemoryOperand - Same as the previous version except it allows folding 292193323Sed /// of any load and store from / to any address, not just from a specific 293193323Sed /// stack slot. 294193323Sed virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 295193323Sed MachineInstr* MI, 296193323Sed const SmallVectorImpl<unsigned> &Ops, 297193323Sed MachineInstr* LoadMI) const; 298193323Sed 299193323Sed /// canFoldMemoryOperand - Returns true if the specified load / store is 300193323Sed /// folding is possible. 301193323Sed virtual bool canFoldMemoryOperand(const MachineInstr*, 302193323Sed const SmallVectorImpl<unsigned> &) const; 303193323Sed 304193323Sed /// unfoldMemoryOperand - Separate a single instruction which folded a load or 305193323Sed /// a store or a load and a store into two or more instruction. If this is 306193323Sed /// possible, returns true as well as the new instructions by reference. 307193323Sed virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 308193323Sed unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 309193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const; 310193323Sed 311193323Sed virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 312193323Sed SmallVectorImpl<SDNode*> &NewNodes) const; 313193323Sed 314193323Sed /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 315193323Sed /// instruction after load / store are unfolded from an instruction of the 316193323Sed /// specified opcode. It returns zero if the specified unfolding is not 317198892Srdivacky /// possible. If LoadRegIndex is non-null, it is filled in with the operand 318198892Srdivacky /// index of the operand which will hold the register holding the loaded 319198892Srdivacky /// value. 320193323Sed virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 321198892Srdivacky bool UnfoldLoad, bool UnfoldStore, 322198892Srdivacky unsigned *LoadRegIndex = 0) const; 323221345Sdim 324202878Srdivacky /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 325202878Srdivacky /// to determine if two loads are loading from the same base address. It 326202878Srdivacky /// should only return true if the base pointers are the same and the 327202878Srdivacky /// only differences between the two addresses are the offset. It also returns 328202878Srdivacky /// the offsets by reference. 329202878Srdivacky virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 330202878Srdivacky int64_t &Offset1, int64_t &Offset2) const; 331202878Srdivacky 332202878Srdivacky /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 333221345Sdim /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 334202878Srdivacky /// be scheduled togther. On some targets if two loads are loading from 335202878Srdivacky /// addresses in the same cache line, it's better if they are scheduled 336202878Srdivacky /// together. This function takes two integers that represent the load offsets 337202878Srdivacky /// from the common base address. It returns true if it decides it's desirable 338202878Srdivacky /// to schedule the two loads together. "NumLoads" is the number of loads that 339202878Srdivacky /// have already been scheduled after Load1. 340202878Srdivacky virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 341202878Srdivacky int64_t Offset1, int64_t Offset2, 342202878Srdivacky unsigned NumLoads) const; 343202878Srdivacky 344263508Sdim virtual bool shouldScheduleAdjacent(MachineInstr* First, 345263508Sdim MachineInstr *Second) const LLVM_OVERRIDE; 346263508Sdim 347207618Srdivacky virtual void getNoopForMachoTarget(MCInst &NopInst) const; 348207618Srdivacky 349193323Sed virtual 350193323Sed bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 351193323Sed 352193323Sed /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 353193323Sed /// instruction that defines the specified register class. 354193323Sed bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 355193323Sed 356203954Srdivacky static bool isX86_64ExtendedReg(const MachineOperand &MO) { 357203954Srdivacky if (!MO.isReg()) return false; 358226633Sdim return X86II::isX86_64ExtendedReg(MO.getReg()); 359203954Srdivacky } 360193323Sed 361193323Sed /// getGlobalBaseReg - Return a virtual register initialized with the 362193323Sed /// the global base register value. Output instructions required to 363193323Sed /// initialize the register in the function entry block, if necessary. 364193323Sed /// 365193323Sed unsigned getGlobalBaseReg(MachineFunction *MF) const; 366193323Sed 367226633Sdim std::pair<uint16_t, uint16_t> 368226633Sdim getExecutionDomain(const MachineInstr *MI) const; 369206083Srdivacky 370226633Sdim void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; 371206083Srdivacky 372234353Sdim unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 373234353Sdim const TargetRegisterInfo *TRI) const; 374263508Sdim unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 375263508Sdim const TargetRegisterInfo *TRI) const; 376234353Sdim void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 377234353Sdim const TargetRegisterInfo *TRI) const; 378234353Sdim 379218893Sdim MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 380218893Sdim MachineInstr* MI, 381218893Sdim unsigned OpNum, 382218893Sdim const SmallVectorImpl<MachineOperand> &MOs, 383218893Sdim unsigned Size, unsigned Alignment) const; 384218893Sdim 385221345Sdim bool isHighLatencyDef(int opc) const; 386221345Sdim 387218893Sdim bool hasHighOperandLatency(const InstrItineraryData *ItinData, 388218893Sdim const MachineRegisterInfo *MRI, 389218893Sdim const MachineInstr *DefMI, unsigned DefIdx, 390218893Sdim const MachineInstr *UseMI, unsigned UseIdx) const; 391221345Sdim 392239462Sdim /// analyzeCompare - For a comparison instruction, return the source registers 393239462Sdim /// in SrcReg and SrcReg2 if having two register operands, and the value it 394239462Sdim /// compares against in CmpValue. Return true if the comparison instruction 395239462Sdim /// can be analyzed. 396239462Sdim virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 397239462Sdim unsigned &SrcReg2, 398239462Sdim int &CmpMask, int &CmpValue) const; 399239462Sdim 400239462Sdim /// optimizeCompareInstr - Check if there exists an earlier instruction that 401239462Sdim /// operates on the same source operands and sets flags in the same way as 402239462Sdim /// Compare; remove Compare if possible. 403239462Sdim virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 404239462Sdim unsigned SrcReg2, int CmpMask, int CmpValue, 405239462Sdim const MachineRegisterInfo *MRI) const; 406239462Sdim 407239462Sdim /// optimizeLoadInstr - Try to remove the load by folding it to a register 408239462Sdim /// operand at the use. We fold the load instructions if and only if the 409239462Sdim /// def and use are in the same BB. We only look at one load and see 410239462Sdim /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 411239462Sdim /// defined by the load we are trying to fold. DefMI returns the machine 412239462Sdim /// instruction that defines FoldAsLoadDefReg, and the function returns 413239462Sdim /// the machine instruction generated due to folding. 414239462Sdim virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 415239462Sdim const MachineRegisterInfo *MRI, 416239462Sdim unsigned &FoldAsLoadDefReg, 417239462Sdim MachineInstr *&DefMI) const; 418239462Sdim 419193323Sedprivate: 420200581Srdivacky MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 421200581Srdivacky MachineFunction::iterator &MFI, 422200581Srdivacky MachineBasicBlock::iterator &MBBI, 423200581Srdivacky LiveVariables *LV) const; 424200581Srdivacky 425199481Srdivacky /// isFrameOperand - Return true and the FrameIndex if the specified 426199481Srdivacky /// operand and follow operands form a reference to the stack frame. 427199481Srdivacky bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 428199481Srdivacky int &FrameIndex) const; 429193323Sed}; 430193323Sed 431193323Sed} // End llvm namespace 432193323Sed 433193323Sed#endif 434