1//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 conditional move and set on condition
11// instructions.
12//
13//===----------------------------------------------------------------------===//
14
15
16// SetCC instructions.
17multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
18  let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
19      isCommutable = 1, SchedRW = [WriteALU] in {
20    def NAME#16rr
21      : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
22          !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
23          [(set GR16:$dst,
24                (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
25                IIC_CMOV16_RR>,TB,OpSize;
26    def NAME#32rr
27      : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
28          !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
29          [(set GR32:$dst,
30                (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
31                IIC_CMOV32_RR>, TB;
32    def NAME#64rr
33      :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
34          !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
35          [(set GR64:$dst,
36                (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
37                IIC_CMOV32_RR>, TB;
38  }
39
40  let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
41      SchedRW = [WriteALULd, ReadAfterLd] in {
42    def NAME#16rm
43      : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
44          !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
45          [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
46                                    CondNode, EFLAGS))], IIC_CMOV16_RM>,
47                                    TB, OpSize;
48    def NAME#32rm
49      : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
50          !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
51          [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
52                                    CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
53    def NAME#64rm
54      :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
55          !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
56          [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
57                                    CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
58  } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
59} // end multiclass
60
61
62// Conditional Moves.
63defm CMOVO  : CMOV<0x40, "cmovo" , X86_COND_O>;
64defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
65defm CMOVB  : CMOV<0x42, "cmovb" , X86_COND_B>;
66defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
67defm CMOVE  : CMOV<0x44, "cmove" , X86_COND_E>;
68defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
69defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
70defm CMOVA  : CMOV<0x47, "cmova" , X86_COND_A>;
71defm CMOVS  : CMOV<0x48, "cmovs" , X86_COND_S>;
72defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>;
73defm CMOVP  : CMOV<0x4A, "cmovp" , X86_COND_P>;
74defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>;
75defm CMOVL  : CMOV<0x4C, "cmovl" , X86_COND_L>;
76defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>;
77defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>;
78defm CMOVG  : CMOV<0x4F, "cmovg" , X86_COND_G>;
79
80
81// SetCC instructions.
82multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
83  let Uses = [EFLAGS] in {
84    def r    : I<opc, MRM0r,  (outs GR8:$dst), (ins),
85                     !strconcat(Mnemonic, "\t$dst"),
86                     [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
87                     IIC_SET_R>, TB, Sched<[WriteALU]>;
88    def m    : I<opc, MRM0m,  (outs), (ins i8mem:$dst),
89                     !strconcat(Mnemonic, "\t$dst"),
90                     [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
91                     IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
92  } // Uses = [EFLAGS]
93}
94
95defm SETO  : SETCC<0x90, "seto",  X86_COND_O>;   // is overflow bit set
96defm SETNO : SETCC<0x91, "setno", X86_COND_NO>;  // is overflow bit not set
97defm SETB  : SETCC<0x92, "setb",  X86_COND_B>;   // unsigned less than
98defm SETAE : SETCC<0x93, "setae", X86_COND_AE>;  // unsigned greater or equal
99defm SETE  : SETCC<0x94, "sete",  X86_COND_E>;   // equal to
100defm SETNE : SETCC<0x95, "setne", X86_COND_NE>;  // not equal to
101defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>;  // unsigned less than or equal
102defm SETA  : SETCC<0x97, "seta",  X86_COND_A>;   // unsigned greater than
103defm SETS  : SETCC<0x98, "sets",  X86_COND_S>;   // is signed bit set
104defm SETNS : SETCC<0x99, "setns", X86_COND_NS>;  // is not signed
105defm SETP  : SETCC<0x9A, "setp",  X86_COND_P>;   // is parity bit set
106defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>;  // is parity bit not set
107defm SETL  : SETCC<0x9C, "setl",  X86_COND_L>;   // signed less than
108defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>;  // signed greater or equal
109defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>;  // signed less than or equal
110defm SETG  : SETCC<0x9F, "setg",  X86_COND_G>;   // signed greater than
111
112