1249259Sdim//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// This file was originally auto-generated from a GPU register header file and 10249259Sdim// all the instruction definitions were originally commented out. Instructions 11249259Sdim// that are not yet supported remain commented out. 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdimclass InterpSlots { 15249259Sdimint P0 = 2; 16249259Sdimint P10 = 0; 17249259Sdimint P20 = 1; 18249259Sdim} 19249259Sdimdef INTERP : InterpSlots; 20249259Sdim 21249259Sdimdef InterpSlot : Operand<i32> { 22249259Sdim let PrintMethod = "printInterpSlot"; 23249259Sdim} 24249259Sdim 25266715Sdimdef SendMsgImm : Operand<i32>; 26266715Sdim 27263508Sdimdef isSI : Predicate<"Subtarget.getGeneration() " 28263508Sdim ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 29249259Sdim 30263508Sdimdef WAIT_FLAG : InstFlag<"printWaitFlag">; 31263508Sdim 32249259Sdimlet Predicates = [isSI] in { 33249259Sdim 34249259Sdimlet neverHasSideEffects = 1 in { 35249259Sdim 36249259Sdimlet isMoveImm = 1 in { 37249259Sdimdef S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 38249259Sdimdef S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 39249259Sdimdef S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 40249259Sdimdef S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 41249259Sdim} // End isMoveImm = 1 42249259Sdim 43249259Sdimdef S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 44249259Sdimdef S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 45249259Sdimdef S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 46249259Sdimdef S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 47249259Sdimdef S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 48249259Sdimdef S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 49249259Sdim} // End neverHasSideEffects = 1 50249259Sdim 51249259Sdim////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 52249259Sdim////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 53249259Sdim////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 54249259Sdim////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 55249259Sdim////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 56249259Sdim////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 57249259Sdim////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 58249259Sdim////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 59249259Sdim//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 60249259Sdim//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 61249259Sdimdef S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 62249259Sdim//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 63249259Sdim//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 64249259Sdim//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 65249259Sdim////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 66249259Sdim////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 67249259Sdim////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 68249259Sdim////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 69249259Sdimdef S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 70249259Sdimdef S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 71249259Sdimdef S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 72249259Sdimdef S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 73249259Sdim 74249259Sdimlet hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 75249259Sdim 76249259Sdimdef S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 77249259Sdimdef S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 78249259Sdimdef S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 79249259Sdimdef S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 80249259Sdimdef S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 81249259Sdimdef S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 82249259Sdimdef S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 83249259Sdimdef S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 84249259Sdim 85249259Sdim} // End hasSideEffects = 1 86249259Sdim 87249259Sdimdef S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 88249259Sdimdef S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 89249259Sdimdef S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 90249259Sdimdef S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 91249259Sdimdef S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 92249259Sdimdef S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 93249259Sdim//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 94249259Sdimdef S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 95249259Sdimdef S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 96249259Sdimdef S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 97249259Sdimdef S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 98249259Sdimdef S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 99249259Sdim 100249259Sdim/* 101249259SdimThis instruction is disabled for now until we can figure out how to teach 102249259Sdimthe instruction selector to correctly use the S_CMP* vs V_CMP* 103249259Sdiminstructions. 104249259Sdim 105249259SdimWhen this instruction is enabled the code generator sometimes produces this 106249259Sdiminvalid sequence: 107249259Sdim 108249259SdimSCC = S_CMPK_EQ_I32 SGPR0, imm 109249259SdimVCC = COPY SCC 110249259SdimVGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 111249259Sdim 112249259Sdimdef S_CMPK_EQ_I32 : SOPK < 113249259Sdim 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 114249259Sdim "S_CMPK_EQ_I32", 115251662Sdim [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 116249259Sdim>; 117249259Sdim*/ 118249259Sdim 119249259Sdimlet isCompare = 1 in { 120249259Sdimdef S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 121249259Sdimdef S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 122249259Sdimdef S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 123249259Sdimdef S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 124249259Sdimdef S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 125249259Sdimdef S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 126249259Sdimdef S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 127249259Sdimdef S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 128249259Sdimdef S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 129249259Sdimdef S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 130249259Sdimdef S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 131249259Sdim} // End isCompare = 1 132249259Sdim 133263508Sdimlet Defs = [SCC], isCommutable = 1 in { 134263508Sdim def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 135263508Sdim def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 136263508Sdim} 137263508Sdim 138249259Sdim//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 139249259Sdimdef S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 140249259Sdimdef S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 141249259Sdimdef S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 142249259Sdim//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 143249259Sdim//def EXP : EXP_ <0x00000000, "EXP", []>; 144249259Sdim 145249259Sdimlet isCompare = 1 in { 146249259Sdim 147249259Sdimdefm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 148263508Sdimdefm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; 149263508Sdimdefm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; 150263508Sdimdefm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; 151263508Sdimdefm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; 152263508Sdimdefm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; 153263508Sdimdefm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; 154263508Sdimdefm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; 155263508Sdimdefm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; 156249259Sdimdefm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 157249259Sdimdefm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 158249259Sdimdefm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 159249259Sdimdefm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 160263508Sdimdefm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; 161249259Sdimdefm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 162249259Sdimdefm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 163249259Sdim 164249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 165249259Sdim 166249259Sdimdefm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 167249259Sdimdefm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 168249259Sdimdefm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 169249259Sdimdefm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 170249259Sdimdefm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 171249259Sdimdefm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 172249259Sdimdefm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 173249259Sdimdefm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 174249259Sdimdefm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 175249259Sdimdefm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 176249259Sdimdefm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 177249259Sdimdefm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 178249259Sdimdefm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 179249259Sdimdefm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 180249259Sdimdefm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 181249259Sdimdefm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 182249259Sdim 183249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 184249259Sdim 185249259Sdimdefm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 186263508Sdimdefm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; 187263508Sdimdefm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; 188263508Sdimdefm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; 189263508Sdimdefm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; 190249259Sdimdefm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 191263508Sdimdefm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; 192263508Sdimdefm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; 193263508Sdimdefm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; 194249259Sdimdefm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 195249259Sdimdefm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 196249259Sdimdefm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 197249259Sdimdefm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 198263508Sdimdefm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; 199249259Sdimdefm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 200249259Sdimdefm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 201249259Sdim 202249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 203249259Sdim 204249259Sdimdefm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 205249259Sdimdefm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 206249259Sdimdefm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 207249259Sdimdefm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 208249259Sdimdefm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 209249259Sdimdefm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 210249259Sdimdefm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 211249259Sdimdefm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 212249259Sdimdefm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 213249259Sdimdefm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 214249259Sdimdefm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 215249259Sdimdefm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 216249259Sdimdefm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 217249259Sdimdefm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 218249259Sdimdefm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 219249259Sdimdefm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 220249259Sdim 221249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 222249259Sdim 223249259Sdimdefm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 224249259Sdimdefm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 225249259Sdimdefm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 226249259Sdimdefm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 227249259Sdimdefm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 228249259Sdimdefm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 229249259Sdimdefm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 230249259Sdimdefm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 231249259Sdimdefm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 232249259Sdimdefm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 233249259Sdimdefm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 234249259Sdimdefm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 235249259Sdimdefm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 236249259Sdimdefm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 237249259Sdimdefm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 238249259Sdimdefm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 239249259Sdim 240249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 241249259Sdim 242249259Sdimdefm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 243249259Sdimdefm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 244249259Sdimdefm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 245249259Sdimdefm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 246249259Sdimdefm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 247249259Sdimdefm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 248249259Sdimdefm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 249249259Sdimdefm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 250249259Sdimdefm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 251249259Sdimdefm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 252249259Sdimdefm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 253249259Sdimdefm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 254249259Sdimdefm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 255249259Sdimdefm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 256249259Sdimdefm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 257249259Sdimdefm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 258249259Sdim 259249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 260249259Sdim 261249259Sdimdefm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 262249259Sdimdefm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 263249259Sdimdefm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 264249259Sdimdefm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 265249259Sdimdefm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 266249259Sdimdefm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 267249259Sdimdefm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 268249259Sdimdefm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 269249259Sdimdefm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 270249259Sdimdefm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 271249259Sdimdefm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 272249259Sdimdefm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 273249259Sdimdefm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 274249259Sdimdefm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 275249259Sdimdefm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 276249259Sdimdefm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 277249259Sdim 278249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 279249259Sdim 280249259Sdimdefm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 281249259Sdimdefm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 282249259Sdimdefm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 283249259Sdimdefm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 284249259Sdimdefm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 285249259Sdimdefm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 286249259Sdimdefm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 287249259Sdimdefm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 288249259Sdimdefm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 289249259Sdimdefm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 290249259Sdimdefm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 291249259Sdimdefm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 292249259Sdimdefm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 293249259Sdimdefm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 294249259Sdimdefm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 295249259Sdimdefm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 296249259Sdim 297249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 298249259Sdim 299249259Sdimdefm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 300263508Sdimdefm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; 301249259Sdimdefm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 302263508Sdimdefm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; 303263508Sdimdefm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; 304249259Sdimdefm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 305263508Sdimdefm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; 306249259Sdimdefm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 307249259Sdim 308249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 309249259Sdim 310249259Sdimdefm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 311249259Sdimdefm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 312249259Sdimdefm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 313249259Sdimdefm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 314249259Sdimdefm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 315249259Sdimdefm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 316249259Sdimdefm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 317249259Sdimdefm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 318249259Sdim 319249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 320249259Sdim 321249259Sdimdefm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 322263508Sdimdefm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; 323263508Sdimdefm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; 324263508Sdimdefm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; 325263508Sdimdefm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; 326263508Sdimdefm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; 327263508Sdimdefm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; 328249259Sdimdefm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 329249259Sdim 330249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 331249259Sdim 332249259Sdimdefm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 333249259Sdimdefm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 334249259Sdimdefm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 335249259Sdimdefm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 336249259Sdimdefm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 337249259Sdimdefm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 338249259Sdimdefm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 339249259Sdimdefm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 340249259Sdim 341249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 342249259Sdim 343249259Sdimdefm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 344263508Sdimdefm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; 345263508Sdimdefm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; 346263508Sdimdefm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; 347263508Sdimdefm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; 348263508Sdimdefm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; 349263508Sdimdefm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; 350249259Sdimdefm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 351249259Sdim 352249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 353249259Sdim 354249259Sdimdefm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 355249259Sdimdefm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 356249259Sdimdefm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 357249259Sdimdefm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 358249259Sdimdefm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 359249259Sdimdefm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 360249259Sdimdefm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 361249259Sdimdefm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 362249259Sdim 363249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 364249259Sdim 365249259Sdimdefm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 366263508Sdimdefm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; 367263508Sdimdefm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; 368263508Sdimdefm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; 369263508Sdimdefm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; 370263508Sdimdefm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; 371263508Sdimdefm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; 372249259Sdimdefm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 373249259Sdim 374249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 375249259Sdim 376249259Sdimdefm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 377249259Sdimdefm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 378249259Sdimdefm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 379249259Sdimdefm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 380249259Sdimdefm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 381249259Sdimdefm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 382249259Sdimdefm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 383249259Sdimdefm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 384249259Sdim 385249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 386249259Sdim 387249259Sdimdefm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 388249259Sdim 389249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 390249259Sdimdefm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 391249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 392249259Sdim 393249259Sdimdefm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 394249259Sdim 395249259Sdimlet hasSideEffects = 1, Defs = [EXEC] in { 396249259Sdimdefm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 397249259Sdim} // End hasSideEffects = 1, Defs = [EXEC] 398249259Sdim 399249259Sdim} // End isCompare = 1 400249259Sdim 401263508Sdimdef DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 402263508Sdimdef DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 403263508Sdimdef DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 404263508Sdimdef DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 405263508Sdimdef DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 406263508Sdimdef DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 407263508Sdimdef DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 408263508Sdimdef DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 409263508Sdimdef DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 410263508Sdimdef DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 411263508Sdim 412249259Sdim//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 413249259Sdim//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 414249259Sdim//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 415263508Sdimdefm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 416249259Sdim//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 417249259Sdim//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 418249259Sdim//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 419249259Sdim//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 420263508Sdimdefm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 421263508Sdimdefm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 422263508Sdimdefm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 423263508Sdimdefm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 424263508Sdimdefm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 425263508Sdimdefm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 426263508Sdimdefm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 427251662Sdim 428263508Sdimdef BUFFER_STORE_BYTE : MUBUF_Store_Helper < 429263508Sdim 0x00000018, "BUFFER_STORE_BYTE", VReg_32 430263508Sdim>; 431263508Sdim 432263508Sdimdef BUFFER_STORE_SHORT : MUBUF_Store_Helper < 433263508Sdim 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 434263508Sdim>; 435263508Sdim 436251662Sdimdef BUFFER_STORE_DWORD : MUBUF_Store_Helper < 437263508Sdim 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 438251662Sdim>; 439251662Sdim 440251662Sdimdef BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 441263508Sdim 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 442251662Sdim>; 443263508Sdim 444263508Sdimdef BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 445263508Sdim 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 446263508Sdim>; 447249259Sdim//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 448249259Sdim//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 449249259Sdim//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 450249259Sdim//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 451249259Sdim//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 452249259Sdim//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 453249259Sdim//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 454249259Sdim//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 455249259Sdim//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 456249259Sdim//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 457249259Sdim//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 458249259Sdim//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 459249259Sdim//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 460249259Sdim//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 461249259Sdim//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 462249259Sdim//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 463249259Sdim//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 464249259Sdim//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 465249259Sdim//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 466249259Sdim//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 467249259Sdim//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 468249259Sdim//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 469249259Sdim//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 470249259Sdim//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 471249259Sdim//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 472249259Sdim//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 473249259Sdim//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 474249259Sdim//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 475249259Sdim//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 476249259Sdim//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 477249259Sdim//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 478249259Sdim//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 479249259Sdim//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 480249259Sdim//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 481249259Sdim//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 482249259Sdim//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 483249259Sdim//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 484249259Sdim//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 485249259Sdim//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 486249259Sdimdef TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 487263508Sdimdef TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 488263508Sdimdef TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 489263508Sdimdef TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 490263508Sdimdef TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 491249259Sdim 492249259Sdimlet mayLoad = 1 in { 493249259Sdim 494263508Sdim// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 495263508Sdim// SMRD instructions, because the SGPR_32 register class does not include M0 496263508Sdim// and writing to M0 from an SMRD instruction will hang the GPU. 497263508Sdimdefm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>; 498249259Sdimdefm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 499249259Sdimdefm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 500249259Sdimdefm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 501249259Sdimdefm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 502249259Sdim 503249259Sdimdefm S_BUFFER_LOAD_DWORD : SMRD_Helper < 504263508Sdim 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32 505249259Sdim>; 506249259Sdim 507249259Sdimdefm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 508249259Sdim 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 509249259Sdim>; 510249259Sdim 511249259Sdimdefm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 512249259Sdim 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 513249259Sdim>; 514249259Sdim 515249259Sdimdefm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 516249259Sdim 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 517249259Sdim>; 518249259Sdim 519249259Sdimdefm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 520249259Sdim 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 521249259Sdim>; 522249259Sdim 523249259Sdim} // mayLoad = 1 524249259Sdim 525249259Sdim//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 526249259Sdim//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 527263508Sdimdefm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 528263508Sdimdefm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 529249259Sdim//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 530249259Sdim//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 531249259Sdim//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 532249259Sdim//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 533249259Sdim//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 534249259Sdim//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 535249259Sdim//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 536249259Sdim//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 537263508Sdimdefm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 538249259Sdim//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 539249259Sdim//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 540249259Sdim//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 541249259Sdim//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 542249259Sdim//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 543249259Sdim//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 544249259Sdim//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 545249259Sdim//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 546249259Sdim//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 547249259Sdim//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 548249259Sdim//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 549249259Sdim//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 550249259Sdim//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 551249259Sdim//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 552249259Sdim//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 553249259Sdim//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 554249259Sdim//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 555263508Sdimdefm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 556249259Sdim//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 557263508Sdimdefm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 558249259Sdim//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 559263508Sdimdefm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 560263508Sdimdefm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 561249259Sdim//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 562249259Sdim//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 563263508Sdimdefm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 564249259Sdim//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 565263508Sdimdefm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 566249259Sdim//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 567263508Sdimdefm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 568263508Sdimdefm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 569249259Sdim//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 570249259Sdim//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 571249259Sdim//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 572249259Sdim//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 573249259Sdim//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 574249259Sdim//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 575249259Sdim//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 576249259Sdim//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 577249259Sdim//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 578249259Sdim//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 579249259Sdim//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 580249259Sdim//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 581249259Sdim//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 582249259Sdim//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 583249259Sdim//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 584249259Sdim//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 585249259Sdim//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 586249259Sdim//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 587249259Sdim//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 588249259Sdim//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 589249259Sdim//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 590249259Sdim//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 591249259Sdim//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 592249259Sdim//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 593249259Sdim//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 594249259Sdim//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 595249259Sdim//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 596249259Sdim//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 597249259Sdim//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 598249259Sdim//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 599249259Sdim//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 600249259Sdim//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 601249259Sdim//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 602249259Sdim//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 603249259Sdim//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 604249259Sdim//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 605249259Sdim//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 606249259Sdim//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 607249259Sdim//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 608249259Sdim//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 609249259Sdim//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 610249259Sdim//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 611249259Sdim//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 612249259Sdim//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 613249259Sdim//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 614249259Sdim//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 615249259Sdim//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 616249259Sdim//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 617249259Sdim//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 618249259Sdim//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 619249259Sdim//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 620249259Sdim//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 621249259Sdim//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 622249259Sdim//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 623249259Sdim 624249259Sdim 625249259Sdimlet neverHasSideEffects = 1, isMoveImm = 1 in { 626249259Sdimdefm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 627249259Sdim} // End neverHasSideEffects = 1, isMoveImm = 1 628249259Sdim 629249259Sdimdefm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 630263508Sdimdefm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 631263508Sdim [(set i32:$dst, (fp_to_sint f64:$src0))] 632263508Sdim>; 633263508Sdimdefm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 634263508Sdim [(set f64:$dst, (sint_to_fp i32:$src0))] 635263508Sdim>; 636249259Sdimdefm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 637251662Sdim [(set f32:$dst, (sint_to_fp i32:$src0))] 638249259Sdim>; 639251662Sdimdefm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 640251662Sdim [(set f32:$dst, (uint_to_fp i32:$src0))] 641251662Sdim>; 642263508Sdimdefm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 643263508Sdim [(set i32:$dst, (fp_to_uint f32:$src0))] 644263508Sdim>; 645249259Sdimdefm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 646251662Sdim [(set i32:$dst, (fp_to_sint f32:$src0))] 647249259Sdim>; 648249259Sdimdefm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 649249259Sdim////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 650249259Sdim//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 651249259Sdim//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 652249259Sdim//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 653249259Sdim//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 654263508Sdimdefm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 655263508Sdim [(set f32:$dst, (fround f64:$src0))] 656263508Sdim>; 657263508Sdimdefm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 658263508Sdim [(set f64:$dst, (fextend f32:$src0))] 659263508Sdim>; 660249259Sdim//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 661249259Sdim//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 662249259Sdim//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 663249259Sdim//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 664249259Sdim//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 665249259Sdim//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 666249259Sdimdefm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 667251662Sdim [(set f32:$dst, (AMDGPUfract f32:$src0))] 668249259Sdim>; 669251662Sdimdefm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 670251662Sdim [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 671251662Sdim>; 672249259Sdimdefm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 673251662Sdim [(set f32:$dst, (fceil f32:$src0))] 674249259Sdim>; 675249259Sdimdefm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 676251662Sdim [(set f32:$dst, (frint f32:$src0))] 677249259Sdim>; 678249259Sdimdefm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 679251662Sdim [(set f32:$dst, (ffloor f32:$src0))] 680249259Sdim>; 681249259Sdimdefm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 682251662Sdim [(set f32:$dst, (fexp2 f32:$src0))] 683249259Sdim>; 684249259Sdimdefm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 685249259Sdimdefm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 686251662Sdim [(set f32:$dst, (flog2 f32:$src0))] 687249259Sdim>; 688249259Sdimdefm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 689249259Sdimdefm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 690249259Sdimdefm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 691251662Sdim [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 692249259Sdim>; 693249259Sdimdefm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 694249259Sdimdefm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 695249259Sdimdefm V_RSQ_LEGACY_F32 : VOP1_32 < 696249259Sdim 0x0000002d, "V_RSQ_LEGACY_F32", 697251662Sdim [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 698249259Sdim>; 699249259Sdimdefm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 700263508Sdimdefm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 701263508Sdim [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 702263508Sdim>; 703249259Sdimdefm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 704249259Sdimdefm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 705249259Sdimdefm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 706263508Sdimdefm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 707263508Sdim [(set f32:$dst, (fsqrt f32:$src0))] 708263508Sdim>; 709263508Sdimdefm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 710263508Sdim [(set f64:$dst, (fsqrt f64:$src0))] 711263508Sdim>; 712249259Sdimdefm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 713249259Sdimdefm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 714249259Sdimdefm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 715249259Sdimdefm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 716249259Sdimdefm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 717249259Sdimdefm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 718249259Sdimdefm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 719249259Sdim//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 720249259Sdimdefm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 721249259Sdimdefm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 722249259Sdim//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 723249259Sdimdefm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 724249259Sdim//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 725249259Sdimdefm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 726249259Sdimdefm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 727249259Sdimdefm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 728249259Sdim 729249259Sdimdef V_INTERP_P1_F32 : VINTRP < 730249259Sdim 0x00000000, 731249259Sdim (outs VReg_32:$dst), 732249259Sdim (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 733249259Sdim "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 734249259Sdim []> { 735249259Sdim let DisableEncoding = "$m0"; 736249259Sdim} 737249259Sdim 738249259Sdimdef V_INTERP_P2_F32 : VINTRP < 739249259Sdim 0x00000001, 740249259Sdim (outs VReg_32:$dst), 741249259Sdim (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 742249259Sdim "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 743249259Sdim []> { 744249259Sdim 745249259Sdim let Constraints = "$src0 = $dst"; 746249259Sdim let DisableEncoding = "$src0,$m0"; 747249259Sdim 748249259Sdim} 749249259Sdim 750249259Sdimdef V_INTERP_MOV_F32 : VINTRP < 751249259Sdim 0x00000002, 752249259Sdim (outs VReg_32:$dst), 753249259Sdim (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 754249259Sdim "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 755249259Sdim []> { 756249259Sdim let DisableEncoding = "$m0"; 757249259Sdim} 758249259Sdim 759249259Sdim//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 760249259Sdim 761249259Sdimlet isTerminator = 1 in { 762249259Sdim 763249259Sdimdef S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 764249259Sdim [(IL_retflag)]> { 765249259Sdim let SIMM16 = 0; 766249259Sdim let isBarrier = 1; 767249259Sdim let hasCtrlDep = 1; 768249259Sdim} 769249259Sdim 770249259Sdimlet isBranch = 1 in { 771249259Sdimdef S_BRANCH : SOPP < 772249259Sdim 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 773249259Sdim [(br bb:$target)]> { 774249259Sdim let isBarrier = 1; 775249259Sdim} 776249259Sdim 777249259Sdimlet DisableEncoding = "$scc" in { 778249259Sdimdef S_CBRANCH_SCC0 : SOPP < 779249259Sdim 0x00000004, (ins brtarget:$target, SCCReg:$scc), 780249259Sdim "S_CBRANCH_SCC0 $target", [] 781249259Sdim>; 782249259Sdimdef S_CBRANCH_SCC1 : SOPP < 783249259Sdim 0x00000005, (ins brtarget:$target, SCCReg:$scc), 784249259Sdim "S_CBRANCH_SCC1 $target", 785249259Sdim [] 786249259Sdim>; 787249259Sdim} // End DisableEncoding = "$scc" 788249259Sdim 789249259Sdimdef S_CBRANCH_VCCZ : SOPP < 790249259Sdim 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 791249259Sdim "S_CBRANCH_VCCZ $target", 792249259Sdim [] 793249259Sdim>; 794249259Sdimdef S_CBRANCH_VCCNZ : SOPP < 795249259Sdim 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 796249259Sdim "S_CBRANCH_VCCNZ $target", 797249259Sdim [] 798249259Sdim>; 799249259Sdim 800249259Sdimlet DisableEncoding = "$exec" in { 801249259Sdimdef S_CBRANCH_EXECZ : SOPP < 802249259Sdim 0x00000008, (ins brtarget:$target, EXECReg:$exec), 803249259Sdim "S_CBRANCH_EXECZ $target", 804249259Sdim [] 805249259Sdim>; 806249259Sdimdef S_CBRANCH_EXECNZ : SOPP < 807249259Sdim 0x00000009, (ins brtarget:$target, EXECReg:$exec), 808249259Sdim "S_CBRANCH_EXECNZ $target", 809249259Sdim [] 810249259Sdim>; 811249259Sdim} // End DisableEncoding = "$exec" 812249259Sdim 813249259Sdim 814249259Sdim} // End isBranch = 1 815249259Sdim} // End isTerminator = 1 816249259Sdim 817249259Sdimlet hasSideEffects = 1 in { 818263508Sdimdef S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 819263508Sdim [(int_AMDGPU_barrier_local)] 820263508Sdim> { 821263508Sdim let SIMM16 = 0; 822263508Sdim let isBarrier = 1; 823263508Sdim let hasCtrlDep = 1; 824263508Sdim let mayLoad = 1; 825263508Sdim let mayStore = 1; 826263508Sdim} 827263508Sdim 828263508Sdimdef S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 829249259Sdim [] 830249259Sdim>; 831249259Sdim//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 832249259Sdim//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 833249259Sdim//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 834266715Sdim 835266715Sdimlet Uses = [EXEC] in { 836266715Sdim def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16", 837266715Sdim [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)] 838266715Sdim > { 839266715Sdim let DisableEncoding = "$m0"; 840266715Sdim } 841266715Sdim} // End Uses = [EXEC] 842266715Sdim 843249259Sdim//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 844249259Sdim//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 845249259Sdim//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 846249259Sdim//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 847249259Sdim//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 848249259Sdim//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 849266715Sdim} // End hasSideEffects 850249259Sdim 851249259Sdimdef V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 852249259Sdim (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 853249259Sdim "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 854249259Sdim [] 855249259Sdim>{ 856249259Sdim let DisableEncoding = "$vcc"; 857249259Sdim} 858249259Sdim 859249259Sdimdef V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 860249259Sdim (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 861249259Sdim InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 862249259Sdim "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 863251662Sdim [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 864249259Sdim>; 865249259Sdim 866249259Sdim//f32 pattern for V_CNDMASK_B32_e64 867249259Sdimdef : Pat < 868251662Sdim (f32 (select i1:$src2, f32:$src1, f32:$src0)), 869251662Sdim (V_CNDMASK_B32_e64 $src0, $src1, $src2) 870249259Sdim>; 871249259Sdim 872263508Sdimdef : Pat < 873263508Sdim (i32 (trunc i64:$val)), 874263508Sdim (EXTRACT_SUBREG $val, sub0) 875263508Sdim>; 876263508Sdim 877263508Sdim//use two V_CNDMASK_B32_e64 instructions for f64 878263508Sdimdef : Pat < 879263508Sdim (f64 (select i1:$src2, f64:$src1, f64:$src0)), 880263508Sdim (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 881263508Sdim (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), 882263508Sdim (EXTRACT_SUBREG $src1, sub0), 883263508Sdim $src2), sub0), 884263508Sdim (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), 885263508Sdim (EXTRACT_SUBREG $src1, sub1), 886263508Sdim $src2), sub1) 887263508Sdim>; 888263508Sdim 889249259Sdimdefm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 890249259Sdimdefm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 891249259Sdim 892249259Sdimlet isCommutable = 1 in { 893249259Sdimdefm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 894251662Sdim [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 895249259Sdim>; 896249259Sdim 897249259Sdimdefm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 898251662Sdim [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 899249259Sdim>; 900249259Sdimdefm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 901249259Sdim} // End isCommutable = 1 902249259Sdim 903249259Sdimdefm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 904249259Sdim 905249259Sdimlet isCommutable = 1 in { 906249259Sdim 907249259Sdimdefm V_MUL_LEGACY_F32 : VOP2_32 < 908249259Sdim 0x00000007, "V_MUL_LEGACY_F32", 909251662Sdim [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 910249259Sdim>; 911249259Sdim 912249259Sdimdefm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 913251662Sdim [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 914249259Sdim>; 915249259Sdim 916249259Sdim 917263508Sdimdefm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 918263508Sdim [(set i32:$dst, (mul I24:$src0, I24:$src1))] 919263508Sdim>; 920249259Sdim//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 921263508Sdimdefm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 922263508Sdim [(set i32:$dst, (mul U24:$src0, U24:$src1))] 923263508Sdim>; 924249259Sdim//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 925249259Sdim 926249259Sdim 927249259Sdimdefm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 928251662Sdim [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 929249259Sdim>; 930249259Sdim 931249259Sdimdefm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 932251662Sdim [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 933249259Sdim>; 934249259Sdim 935249259Sdimdefm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 936249259Sdimdefm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 937251662Sdimdefm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 938251662Sdim [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 939251662Sdim>; 940251662Sdimdefm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 941251662Sdim [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 942251662Sdim>; 943251662Sdimdefm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 944251662Sdim [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 945251662Sdim>; 946251662Sdimdefm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 947251662Sdim [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 948251662Sdim>; 949249259Sdim 950249259Sdimdefm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 951251662Sdim [(set i32:$dst, (srl i32:$src0, i32:$src1))] 952249259Sdim>; 953249259Sdimdefm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 954249259Sdim 955249259Sdimdefm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 956251662Sdim [(set i32:$dst, (sra i32:$src0, i32:$src1))] 957249259Sdim>; 958249259Sdimdefm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 959249259Sdim 960263508Sdimlet hasPostISelHook = 1 in { 961263508Sdim 962249259Sdimdefm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 963251662Sdim [(set i32:$dst, (shl i32:$src0, i32:$src1))] 964249259Sdim>; 965263508Sdim 966263508Sdim} 967249259Sdimdefm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 968249259Sdim 969249259Sdimdefm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 970251662Sdim [(set i32:$dst, (and i32:$src0, i32:$src1))] 971249259Sdim>; 972249259Sdimdefm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 973251662Sdim [(set i32:$dst, (or i32:$src0, i32:$src1))] 974249259Sdim>; 975249259Sdimdefm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 976251662Sdim [(set i32:$dst, (xor i32:$src0, i32:$src1))] 977249259Sdim>; 978249259Sdim 979249259Sdim} // End isCommutable = 1 980249259Sdim 981249259Sdimdefm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 982249259Sdimdefm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 983249259Sdimdefm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 984249259Sdimdefm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 985249259Sdim//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 986263508Sdimdefm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 987263508Sdimdefm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 988249259Sdim 989249259Sdimlet isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 990263508Sdim// No patterns so that the scalar instructions are always selected. 991263508Sdim// The scalar versions will be replaced with vector when needed later. 992266715Sdimdefm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>; 993266715Sdimdefm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>; 994266715Sdimdefm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32, 995266715Sdim "V_SUB_I32">; 996249259Sdim 997263508Sdimlet Uses = [VCC] in { // Carry-in comes from VCC 998266715Sdimdefm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>; 999266715Sdimdefm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>; 1000266715Sdimdefm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32, 1001266715Sdim "V_SUBB_U32">; 1002249259Sdim} // End Uses = [VCC] 1003249259Sdim} // End isCommutable = 1, Defs = [VCC] 1004249259Sdim 1005249259Sdimdefm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 1006249259Sdim////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 1007249259Sdim////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 1008249259Sdim////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 1009249259Sdimdefm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 1010251662Sdim [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 1011249259Sdim>; 1012249259Sdim////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 1013249259Sdim////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 1014249259Sdimdef S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 1015249259Sdimdef S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 1016249259Sdimdef S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 1017249259Sdimdef S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 1018249259Sdimdef S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 1019249259Sdimdef S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 1020249259Sdimdef S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 1021249259Sdimdef S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 1022249259Sdimdef S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 1023249259Sdimdef S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 1024249259Sdimdef S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 1025249259Sdimdef S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 1026249259Sdim////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 1027249259Sdim////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 1028249259Sdim////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 1029249259Sdim////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 1030249259Sdim//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 1031249259Sdim 1032249259Sdimlet neverHasSideEffects = 1 in { 1033249259Sdim 1034249259Sdimdef V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1035249259Sdimdef V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 1036263508Sdimdef V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1037263508Sdim [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 1038263508Sdim>; 1039263508Sdimdef V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1040263508Sdim [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 1041263508Sdim>; 1042249259Sdim 1043249259Sdim} // End neverHasSideEffects 1044249259Sdimdef V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1045249259Sdimdef V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1046249259Sdimdef V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1047249259Sdimdef V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1048249259Sdimdef V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 1049249259Sdimdef V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 1050249259Sdimdef V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 1051251662Sdimdefm : BFIPatterns <V_BFI_B32>; 1052263508Sdimdef V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1053263508Sdim [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1054263508Sdim>; 1055263508Sdimdef V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1056263508Sdim [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1057263508Sdim>; 1058249259Sdim//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1059249259Sdimdef V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1060263508Sdimdef : ROTRPattern <V_ALIGNBIT_B32>; 1061263508Sdim 1062249259Sdimdef V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1063249259Sdimdef V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1064249259Sdim////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1065249259Sdim////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1066249259Sdim////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1067249259Sdim////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1068249259Sdim////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1069249259Sdim////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1070249259Sdim////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1071249259Sdim////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1072249259Sdim////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1073249259Sdim//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1074249259Sdim//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1075249259Sdim//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1076249259Sdimdef V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1077249259Sdim////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1078249259Sdimdef V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1079249259Sdimdef V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1080263508Sdim 1081263508Sdimdef V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1082263508Sdim [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1083263508Sdim>; 1084263508Sdimdef V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1085263508Sdim [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1086263508Sdim>; 1087263508Sdimdef V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1088263508Sdim [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1089263508Sdim>; 1090263508Sdim 1091263508Sdimlet isCommutable = 1 in { 1092263508Sdim 1093249259Sdimdef V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1094249259Sdimdef V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1095249259Sdimdef V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1096249259Sdimdef V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1097263508Sdim 1098263508Sdim} // isCommutable = 1 1099263508Sdim 1100263508Sdimdef : Pat < 1101263508Sdim (fadd f64:$src0, f64:$src1), 1102263508Sdim (V_ADD_F64 $src0, $src1, (i64 0)) 1103263508Sdim>; 1104263508Sdim 1105263508Sdimdef : Pat < 1106263508Sdim (fmul f64:$src0, f64:$src1), 1107263508Sdim (V_MUL_F64 $src0, $src1, (i64 0)) 1108263508Sdim>; 1109263508Sdim 1110249259Sdimdef V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1111249259Sdim 1112249259Sdimlet isCommutable = 1 in { 1113249259Sdim 1114249259Sdimdef V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1115249259Sdimdef V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1116249259Sdimdef V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1117249259Sdimdef V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1118249259Sdim 1119249259Sdim} // isCommutable = 1 1120249259Sdim 1121249259Sdimdef : Pat < 1122251662Sdim (mul i32:$src0, i32:$src1), 1123251662Sdim (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1124249259Sdim>; 1125249259Sdim 1126249259Sdimdef : Pat < 1127251662Sdim (mulhu i32:$src0, i32:$src1), 1128251662Sdim (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1129249259Sdim>; 1130249259Sdim 1131249259Sdimdef : Pat < 1132251662Sdim (mulhs i32:$src0, i32:$src1), 1133251662Sdim (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1134249259Sdim>; 1135249259Sdim 1136249259Sdimdef V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1137249259Sdimdef V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1138249259Sdimdef V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1139249259Sdimdef V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1140249259Sdim//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1141249259Sdim//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1142249259Sdim//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1143249259Sdimdef V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1144263508Sdim 1145263508Sdimlet Defs = [SCC] in { // Carry out goes to SCC 1146263508Sdimlet isCommutable = 1 in { 1147249259Sdimdef S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1148263508Sdimdef S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", 1149263508Sdim [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 1150263508Sdim>; 1151263508Sdim} // End isCommutable = 1 1152263508Sdim 1153249259Sdimdef S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1154263508Sdimdef S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", 1155263508Sdim [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 1156263508Sdim>; 1157263508Sdim 1158263508Sdimlet Uses = [SCC] in { // Carry in comes from SCC 1159263508Sdimlet isCommutable = 1 in { 1160263508Sdimdef S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", 1161263508Sdim [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1162263508Sdim} // End isCommutable = 1 1163263508Sdim 1164263508Sdimdef S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", 1165263508Sdim [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1166263508Sdim} // End Uses = [SCC] 1167263508Sdim} // End Defs = [SCC] 1168263508Sdim 1169249259Sdimdef S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1170249259Sdimdef S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1171249259Sdimdef S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1172249259Sdimdef S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1173249259Sdim 1174249259Sdimdef S_CSELECT_B32 : SOP2 < 1175249259Sdim 0x0000000a, (outs SReg_32:$dst), 1176249259Sdim (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1177251662Sdim [] 1178249259Sdim>; 1179249259Sdim 1180249259Sdimdef S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1181249259Sdim 1182249259Sdimdef S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1183249259Sdim 1184249259Sdimdef S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1185251662Sdim [(set i64:$dst, (and i64:$src0, i64:$src1))] 1186249259Sdim>; 1187249259Sdim 1188249259Sdimdef : Pat < 1189251662Sdim (i1 (and i1:$src0, i1:$src1)), 1190251662Sdim (S_AND_B64 $src0, $src1) 1191249259Sdim>; 1192249259Sdim 1193249259Sdimdef S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1194249259Sdimdef S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1195249259Sdimdef : Pat < 1196251662Sdim (i1 (or i1:$src0, i1:$src1)), 1197251662Sdim (S_OR_B64 $src0, $src1) 1198249259Sdim>; 1199249259Sdimdef S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1200263508Sdimdef S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 1201263508Sdim [(set i1:$dst, (xor i1:$src0, i1:$src1))] 1202263508Sdim>; 1203249259Sdimdef S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1204249259Sdimdef S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1205249259Sdimdef S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1206249259Sdimdef S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1207249259Sdimdef S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1208249259Sdimdef S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1209249259Sdimdef S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1210249259Sdimdef S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1211249259Sdimdef S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1212249259Sdimdef S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1213263508Sdim 1214263508Sdim// Use added complexity so these patterns are preferred to the VALU patterns. 1215263508Sdimlet AddedComplexity = 1 in { 1216263508Sdim 1217263508Sdimdef S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 1218263508Sdim [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1219263508Sdim>; 1220263508Sdimdef S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 1221263508Sdim [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1222263508Sdim>; 1223263508Sdimdef S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 1224263508Sdim [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1225263508Sdim>; 1226263508Sdimdef S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 1227263508Sdim [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1228263508Sdim>; 1229263508Sdimdef S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 1230263508Sdim [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1231263508Sdim>; 1232263508Sdimdef S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 1233263508Sdim [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1234263508Sdim>; 1235263508Sdim 1236263508Sdim} // End AddedComplexity = 1 1237263508Sdim 1238249259Sdimdef S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1239249259Sdimdef S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1240249259Sdimdef S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1241249259Sdimdef S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1242249259Sdimdef S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1243249259Sdimdef S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1244249259Sdimdef S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1245249259Sdim//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1246249259Sdimdef S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1247249259Sdim 1248249259Sdimlet isCodeGenOnly = 1, isPseudo = 1 in { 1249249259Sdim 1250249259Sdimdef LOAD_CONST : AMDGPUShaderInst < 1251249259Sdim (outs GPRF32:$dst), 1252249259Sdim (ins i32imm:$src), 1253249259Sdim "LOAD_CONST $dst, $src", 1254249259Sdim [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1255249259Sdim>; 1256249259Sdim 1257263508Sdim// SI pseudo instructions. These are used by the CFG structurizer pass 1258249259Sdim// and should be lowered to ISA instructions prior to codegen. 1259249259Sdim 1260249259Sdimlet mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1261249259Sdim Uses = [EXEC], Defs = [EXEC] in { 1262249259Sdim 1263249259Sdimlet isBranch = 1, isTerminator = 1 in { 1264249259Sdim 1265249259Sdimdef SI_IF : InstSI < 1266249259Sdim (outs SReg_64:$dst), 1267249259Sdim (ins SReg_64:$vcc, brtarget:$target), 1268249259Sdim "SI_IF $dst, $vcc, $target", 1269251662Sdim [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1270249259Sdim>; 1271249259Sdim 1272249259Sdimdef SI_ELSE : InstSI < 1273249259Sdim (outs SReg_64:$dst), 1274249259Sdim (ins SReg_64:$src, brtarget:$target), 1275249259Sdim "SI_ELSE $dst, $src, $target", 1276251662Sdim [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1277249259Sdim 1278249259Sdim let Constraints = "$src = $dst"; 1279249259Sdim} 1280249259Sdim 1281249259Sdimdef SI_LOOP : InstSI < 1282249259Sdim (outs), 1283249259Sdim (ins SReg_64:$saved, brtarget:$target), 1284249259Sdim "SI_LOOP $saved, $target", 1285251662Sdim [(int_SI_loop i64:$saved, bb:$target)] 1286249259Sdim>; 1287249259Sdim 1288249259Sdim} // end isBranch = 1, isTerminator = 1 1289249259Sdim 1290249259Sdimdef SI_BREAK : InstSI < 1291249259Sdim (outs SReg_64:$dst), 1292249259Sdim (ins SReg_64:$src), 1293249259Sdim "SI_ELSE $dst, $src", 1294251662Sdim [(set i64:$dst, (int_SI_break i64:$src))] 1295249259Sdim>; 1296249259Sdim 1297249259Sdimdef SI_IF_BREAK : InstSI < 1298249259Sdim (outs SReg_64:$dst), 1299249259Sdim (ins SReg_64:$vcc, SReg_64:$src), 1300249259Sdim "SI_IF_BREAK $dst, $vcc, $src", 1301251662Sdim [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1302249259Sdim>; 1303249259Sdim 1304249259Sdimdef SI_ELSE_BREAK : InstSI < 1305249259Sdim (outs SReg_64:$dst), 1306249259Sdim (ins SReg_64:$src0, SReg_64:$src1), 1307249259Sdim "SI_ELSE_BREAK $dst, $src0, $src1", 1308251662Sdim [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1309249259Sdim>; 1310249259Sdim 1311249259Sdimdef SI_END_CF : InstSI < 1312249259Sdim (outs), 1313249259Sdim (ins SReg_64:$saved), 1314249259Sdim "SI_END_CF $saved", 1315251662Sdim [(int_SI_end_cf i64:$saved)] 1316249259Sdim>; 1317249259Sdim 1318249259Sdimdef SI_KILL : InstSI < 1319249259Sdim (outs), 1320249259Sdim (ins VReg_32:$src), 1321249259Sdim "SI_KIL $src", 1322251662Sdim [(int_AMDGPU_kill f32:$src)] 1323249259Sdim>; 1324249259Sdim 1325249259Sdim} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1326249259Sdim // Uses = [EXEC], Defs = [EXEC] 1327249259Sdim 1328249259Sdimlet Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1329249259Sdim 1330263508Sdim//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri64, ADDRIndirect>; 1331263508Sdim 1332263508Sdimlet UseNamedOperandTable = 1 in { 1333263508Sdim 1334263508Sdimdef SI_RegisterLoad : AMDGPUShaderInst < 1335263508Sdim (outs VReg_32:$dst, SReg_64:$temp), 1336263508Sdim (ins FRAMEri64:$addr, i32imm:$chan), 1337263508Sdim "", [] 1338263508Sdim> { 1339263508Sdim let isRegisterLoad = 1; 1340263508Sdim let mayLoad = 1; 1341263508Sdim} 1342263508Sdim 1343263508Sdimclass SIRegStore<dag outs> : AMDGPUShaderInst < 1344263508Sdim outs, 1345263508Sdim (ins VReg_32:$val, FRAMEri64:$addr, i32imm:$chan), 1346263508Sdim "", [] 1347263508Sdim> { 1348263508Sdim let isRegisterStore = 1; 1349263508Sdim let mayStore = 1; 1350263508Sdim} 1351263508Sdim 1352263508Sdimlet usesCustomInserter = 1 in { 1353263508Sdimdef SI_RegisterStorePseudo : SIRegStore<(outs)>; 1354263508Sdim} // End usesCustomInserter = 1 1355263508Sdimdef SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; 1356263508Sdim 1357263508Sdim 1358263508Sdim} // End UseNamedOperandTable = 1 1359263508Sdim 1360249259Sdimdef SI_INDIRECT_SRC : InstSI < 1361249259Sdim (outs VReg_32:$dst, SReg_64:$temp), 1362249259Sdim (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1363249259Sdim "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1364249259Sdim [] 1365249259Sdim>; 1366249259Sdim 1367249259Sdimclass SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1368249259Sdim (outs rc:$dst, SReg_64:$temp), 1369249259Sdim (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1370249259Sdim "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1371249259Sdim [] 1372249259Sdim> { 1373249259Sdim let Constraints = "$src = $dst"; 1374249259Sdim} 1375249259Sdim 1376263508Sdimdef SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>; 1377249259Sdimdef SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1378249259Sdimdef SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1379249259Sdimdef SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1380249259Sdimdef SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1381249259Sdim 1382249259Sdim} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1383249259Sdim 1384263508Sdimlet usesCustomInserter = 1 in { 1385263508Sdim 1386263508Sdim// This pseudo instruction takes a pointer as input and outputs a resource 1387263508Sdim// constant that can be used with the ADDR64 MUBUF instructions. 1388263508Sdimdef SI_ADDR64_RSRC : InstSI < 1389263508Sdim (outs SReg_128:$srsrc), 1390263508Sdim (ins SReg_64:$ptr), 1391263508Sdim "", [] 1392263508Sdim>; 1393263508Sdim 1394263508Sdimdef V_SUB_F64 : InstSI < 1395263508Sdim (outs VReg_64:$dst), 1396263508Sdim (ins VReg_64:$src0, VReg_64:$src1), 1397263508Sdim "V_SUB_F64 $dst, $src0, $src1", 1398263508Sdim [] 1399263508Sdim>; 1400263508Sdim 1401263508Sdim} // end usesCustomInserter 1402263508Sdim 1403249259Sdim} // end IsCodeGenOnly, isPseudo 1404249259Sdim 1405249259Sdimdef : Pat< 1406251662Sdim (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1407251662Sdim (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1408249259Sdim>; 1409249259Sdim 1410249259Sdimdef : Pat < 1411249259Sdim (int_AMDGPU_kilp), 1412249259Sdim (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1413249259Sdim>; 1414249259Sdim 1415249259Sdim/* int_SI_vs_load_input */ 1416249259Sdimdef : Pat< 1417263508Sdim (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1418266715Sdim (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) 1419249259Sdim>; 1420249259Sdim 1421249259Sdim/* int_SI_export */ 1422249259Sdimdef : Pat < 1423249259Sdim (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1424251662Sdim f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1425249259Sdim (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1426251662Sdim $src0, $src1, $src2, $src3) 1427249259Sdim>; 1428249259Sdim 1429263508Sdimdef : Pat < 1430263508Sdim (f64 (fsub f64:$src0, f64:$src1)), 1431263508Sdim (V_SUB_F64 $src0, $src1) 1432263508Sdim>; 1433263508Sdim 1434251662Sdim/********** ======================= **********/ 1435251662Sdim/********** Image sampling patterns **********/ 1436251662Sdim/********** ======================= **********/ 1437249259Sdim 1438263508Sdim/* SIsample for simple 1D texture lookup */ 1439249259Sdimdef : Pat < 1440263508Sdim (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), 1441263508Sdim (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1442249259Sdim>; 1443249259Sdim 1444263508Sdimclass SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1445263508Sdim (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm), 1446251662Sdim (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1447249259Sdim>; 1448249259Sdim 1449263508Sdimclass SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1450263508Sdim (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT), 1451251662Sdim (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1452249259Sdim>; 1453249259Sdim 1454263508Sdimclass SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1455263508Sdim (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY), 1456251662Sdim (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1457249259Sdim>; 1458249259Sdim 1459263508Sdimclass SampleShadowPattern<SDNode name, MIMG opcode, 1460251662Sdim ValueType vt> : Pat < 1461263508Sdim (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW), 1462251662Sdim (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1463249259Sdim>; 1464249259Sdim 1465263508Sdimclass SampleShadowArrayPattern<SDNode name, MIMG opcode, 1466251662Sdim ValueType vt> : Pat < 1467263508Sdim (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY), 1468251662Sdim (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1469249259Sdim>; 1470249259Sdim 1471263508Sdim/* SIsample* for texture lookups consuming more address parameters */ 1472263508Sdimmulticlass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1473263508Sdim MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1474263508SdimMIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1475263508Sdim def : SamplePattern <SIsample, sample, addr_type>; 1476263508Sdim def : SampleRectPattern <SIsample, sample, addr_type>; 1477263508Sdim def : SampleArrayPattern <SIsample, sample, addr_type>; 1478263508Sdim def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1479263508Sdim def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1480249259Sdim 1481263508Sdim def : SamplePattern <SIsamplel, sample_l, addr_type>; 1482263508Sdim def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1483263508Sdim def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1484263508Sdim def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1485249259Sdim 1486263508Sdim def : SamplePattern <SIsampleb, sample_b, addr_type>; 1487263508Sdim def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1488263508Sdim def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1489263508Sdim def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1490263508Sdim 1491263508Sdim def : SamplePattern <SIsampled, sample_d, addr_type>; 1492263508Sdim def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1493263508Sdim def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1494263508Sdim def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1495249259Sdim} 1496249259Sdim 1497263508Sdimdefm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1498263508Sdim IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1499263508Sdim IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1500263508Sdim IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1501263508Sdim v2i32>; 1502263508Sdimdefm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1503263508Sdim IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1504263508Sdim IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1505263508Sdim IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1506263508Sdim v4i32>; 1507263508Sdimdefm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1508263508Sdim IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1509263508Sdim IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1510263508Sdim IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1511263508Sdim v8i32>; 1512263508Sdimdefm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1513263508Sdim IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1514263508Sdim IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1515263508Sdim IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1516263508Sdim v16i32>; 1517249259Sdim 1518251662Sdim/* int_SI_imageload for texture fetches consuming varying address parameters */ 1519251662Sdimclass ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1520251662Sdim (name addr_type:$addr, v32i8:$rsrc, imm), 1521251662Sdim (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1522251662Sdim>; 1523251662Sdim 1524251662Sdimclass ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1525251662Sdim (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1526251662Sdim (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1527251662Sdim>; 1528251662Sdim 1529263508Sdimclass ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1530263508Sdim (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1531263508Sdim (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1532263508Sdim>; 1533263508Sdim 1534263508Sdimclass ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1535263508Sdim (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1536263508Sdim (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1537263508Sdim>; 1538263508Sdim 1539263508Sdimmulticlass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1540263508Sdim def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1541263508Sdim def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1542251662Sdim} 1543251662Sdim 1544263508Sdimmulticlass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1545263508Sdim def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1546263508Sdim def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1547263508Sdim} 1548251662Sdim 1549263508Sdimdefm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1550263508Sdimdefm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1551263508Sdim 1552263508Sdimdefm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1553263508Sdimdefm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1554263508Sdim 1555251662Sdim/* Image resource information */ 1556251662Sdimdef : Pat < 1557251662Sdim (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1558263508Sdim (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1559251662Sdim>; 1560251662Sdim 1561251662Sdimdef : Pat < 1562251662Sdim (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1563263508Sdim (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1564251662Sdim>; 1565251662Sdim 1566263508Sdimdef : Pat < 1567263508Sdim (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1568263508Sdim (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1569263508Sdim>; 1570263508Sdim 1571249259Sdim/********** ============================================ **********/ 1572249259Sdim/********** Extraction, Insertion, Building and Casting **********/ 1573249259Sdim/********** ============================================ **********/ 1574249259Sdim 1575249259Sdimforeach Index = 0-2 in { 1576249259Sdim def Extract_Element_v2i32_#Index : Extract_Element < 1577251662Sdim i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1578249259Sdim >; 1579249259Sdim def Insert_Element_v2i32_#Index : Insert_Element < 1580251662Sdim i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1581249259Sdim >; 1582249259Sdim 1583249259Sdim def Extract_Element_v2f32_#Index : Extract_Element < 1584251662Sdim f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1585249259Sdim >; 1586249259Sdim def Insert_Element_v2f32_#Index : Insert_Element < 1587251662Sdim f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1588249259Sdim >; 1589249259Sdim} 1590249259Sdim 1591249259Sdimforeach Index = 0-3 in { 1592249259Sdim def Extract_Element_v4i32_#Index : Extract_Element < 1593251662Sdim i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1594249259Sdim >; 1595249259Sdim def Insert_Element_v4i32_#Index : Insert_Element < 1596251662Sdim i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1597249259Sdim >; 1598249259Sdim 1599249259Sdim def Extract_Element_v4f32_#Index : Extract_Element < 1600251662Sdim f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1601249259Sdim >; 1602249259Sdim def Insert_Element_v4f32_#Index : Insert_Element < 1603251662Sdim f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1604249259Sdim >; 1605249259Sdim} 1606249259Sdim 1607249259Sdimforeach Index = 0-7 in { 1608249259Sdim def Extract_Element_v8i32_#Index : Extract_Element < 1609251662Sdim i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1610249259Sdim >; 1611249259Sdim def Insert_Element_v8i32_#Index : Insert_Element < 1612251662Sdim i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1613249259Sdim >; 1614249259Sdim 1615249259Sdim def Extract_Element_v8f32_#Index : Extract_Element < 1616251662Sdim f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1617249259Sdim >; 1618249259Sdim def Insert_Element_v8f32_#Index : Insert_Element < 1619251662Sdim f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1620249259Sdim >; 1621249259Sdim} 1622249259Sdim 1623249259Sdimforeach Index = 0-15 in { 1624249259Sdim def Extract_Element_v16i32_#Index : Extract_Element < 1625251662Sdim i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1626249259Sdim >; 1627249259Sdim def Insert_Element_v16i32_#Index : Insert_Element < 1628251662Sdim i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1629249259Sdim >; 1630249259Sdim 1631249259Sdim def Extract_Element_v16f32_#Index : Extract_Element < 1632251662Sdim f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1633249259Sdim >; 1634249259Sdim def Insert_Element_v16f32_#Index : Insert_Element < 1635251662Sdim f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1636249259Sdim >; 1637249259Sdim} 1638249259Sdim 1639249259Sdimdef : BitConvert <i32, f32, SReg_32>; 1640249259Sdimdef : BitConvert <i32, f32, VReg_32>; 1641249259Sdim 1642249259Sdimdef : BitConvert <f32, i32, SReg_32>; 1643249259Sdimdef : BitConvert <f32, i32, VReg_32>; 1644249259Sdim 1645263508Sdimdef : BitConvert <i64, f64, VReg_64>; 1646263508Sdim 1647263508Sdimdef : BitConvert <f64, i64, VReg_64>; 1648263508Sdim 1649263508Sdimdef : BitConvert <v2f32, v2i32, VReg_64>; 1650263508Sdimdef : BitConvert <v2i32, v2f32, VReg_64>; 1651263508Sdimdef : BitConvert <v2i32, i64, VReg_64>; 1652263508Sdim 1653263508Sdimdef : BitConvert <v4f32, v4i32, VReg_128>; 1654263508Sdimdef : BitConvert <v4i32, v4f32, VReg_128>; 1655263508Sdimdef : BitConvert <v4i32, i128, VReg_128>; 1656263508Sdimdef : BitConvert <i128, v4i32, VReg_128>; 1657263508Sdim 1658263508Sdimdef : BitConvert <v8i32, v32i8, SReg_256>; 1659263508Sdimdef : BitConvert <v32i8, v8i32, SReg_256>; 1660263508Sdimdef : BitConvert <v8i32, v32i8, VReg_256>; 1661263508Sdimdef : BitConvert <v32i8, v8i32, VReg_256>; 1662263508Sdim 1663249259Sdim/********** =================== **********/ 1664249259Sdim/********** Src & Dst modifiers **********/ 1665249259Sdim/********** =================== **********/ 1666249259Sdim 1667249259Sdimdef : Pat < 1668251662Sdim (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1669251662Sdim (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1670249259Sdim 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1671249259Sdim>; 1672249259Sdim 1673266715Sdim/********** ================================ **********/ 1674266715Sdim/********** Floating point absolute/negative **********/ 1675266715Sdim/********** ================================ **********/ 1676266715Sdim 1677266715Sdim// Manipulate the sign bit directly, as e.g. using the source negation modifier 1678266715Sdim// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0, 1679266715Sdim// breaking the piglit *s-floatBitsToInt-neg* tests 1680266715Sdim 1681266715Sdim// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly 1682266715Sdim// removing these patterns 1683266715Sdim 1684249259Sdimdef : Pat < 1685266715Sdim (fneg (fabs f32:$src)), 1686266715Sdim (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ 1687266715Sdim>; 1688266715Sdim 1689266715Sdimdef : Pat < 1690251662Sdim (fabs f32:$src), 1691266715Sdim (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */ 1692249259Sdim>; 1693249259Sdim 1694249259Sdimdef : Pat < 1695251662Sdim (fneg f32:$src), 1696266715Sdim (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */ 1697249259Sdim>; 1698249259Sdim 1699249259Sdim/********** ================== **********/ 1700249259Sdim/********** Immediate Patterns **********/ 1701249259Sdim/********** ================== **********/ 1702249259Sdim 1703249259Sdimdef : Pat < 1704263508Sdim (SGPRImm<(i32 imm)>:$imm), 1705263508Sdim (S_MOV_B32 imm:$imm) 1706263508Sdim>; 1707263508Sdim 1708263508Sdimdef : Pat < 1709263508Sdim (SGPRImm<(f32 fpimm)>:$imm), 1710263508Sdim (S_MOV_B32 fpimm:$imm) 1711263508Sdim>; 1712263508Sdim 1713263508Sdimdef : Pat < 1714249259Sdim (i32 imm:$imm), 1715249259Sdim (V_MOV_B32_e32 imm:$imm) 1716249259Sdim>; 1717249259Sdim 1718249259Sdimdef : Pat < 1719249259Sdim (f32 fpimm:$imm), 1720249259Sdim (V_MOV_B32_e32 fpimm:$imm) 1721249259Sdim>; 1722249259Sdim 1723249259Sdimdef : Pat < 1724249259Sdim (i1 imm:$imm), 1725249259Sdim (S_MOV_B64 imm:$imm) 1726249259Sdim>; 1727249259Sdim 1728249259Sdimdef : Pat < 1729249259Sdim (i64 InlineImm<i64>:$imm), 1730249259Sdim (S_MOV_B64 InlineImm<i64>:$imm) 1731249259Sdim>; 1732249259Sdim 1733249259Sdim// i64 immediates aren't supported in hardware, split it into two 32bit values 1734249259Sdimdef : Pat < 1735249259Sdim (i64 imm:$imm), 1736249259Sdim (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1737249259Sdim (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1738249259Sdim (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1739249259Sdim>; 1740249259Sdim 1741263508Sdimdef : Pat < 1742263508Sdim (f64 fpimm:$imm), 1743263508Sdim (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1744263508Sdim (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1745263508Sdim (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1746263508Sdim>; 1747263508Sdim 1748249259Sdim/********** ===================== **********/ 1749249259Sdim/********** Interpolation Paterns **********/ 1750249259Sdim/********** ===================== **********/ 1751249259Sdim 1752249259Sdimdef : Pat < 1753251662Sdim (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1754251662Sdim (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1755249259Sdim>; 1756249259Sdim 1757249259Sdimdef : Pat < 1758251662Sdim (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1759251662Sdim (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1760251662Sdim imm:$attr_chan, imm:$attr, i32:$params), 1761251662Sdim (EXTRACT_SUBREG $ij, sub1), 1762251662Sdim imm:$attr_chan, imm:$attr, $params) 1763249259Sdim>; 1764249259Sdim 1765249259Sdim/********** ================== **********/ 1766249259Sdim/********** Intrinsic Patterns **********/ 1767249259Sdim/********** ================== **********/ 1768249259Sdim 1769249259Sdim/* llvm.AMDGPU.pow */ 1770251662Sdimdef : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1771249259Sdim 1772249259Sdimdef : Pat < 1773251662Sdim (int_AMDGPU_div f32:$src0, f32:$src1), 1774251662Sdim (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1775249259Sdim>; 1776249259Sdim 1777249259Sdimdef : Pat< 1778251662Sdim (fdiv f32:$src0, f32:$src1), 1779251662Sdim (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1780249259Sdim>; 1781249259Sdim 1782263508Sdimdef : Pat< 1783263508Sdim (fdiv f64:$src0, f64:$src1), 1784263508Sdim (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1785263508Sdim>; 1786263508Sdim 1787249259Sdimdef : Pat < 1788251662Sdim (fcos f32:$src0), 1789251662Sdim (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1790249259Sdim>; 1791249259Sdim 1792249259Sdimdef : Pat < 1793251662Sdim (fsin f32:$src0), 1794251662Sdim (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1795249259Sdim>; 1796249259Sdim 1797249259Sdimdef : Pat < 1798251662Sdim (int_AMDGPU_cube v4f32:$src), 1799249259Sdim (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1800251662Sdim (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1801251662Sdim (EXTRACT_SUBREG $src, sub1), 1802251662Sdim (EXTRACT_SUBREG $src, sub2)), 1803251662Sdim sub0), 1804251662Sdim (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1805251662Sdim (EXTRACT_SUBREG $src, sub1), 1806251662Sdim (EXTRACT_SUBREG $src, sub2)), 1807251662Sdim sub1), 1808251662Sdim (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1809251662Sdim (EXTRACT_SUBREG $src, sub1), 1810251662Sdim (EXTRACT_SUBREG $src, sub2)), 1811251662Sdim sub2), 1812251662Sdim (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1813251662Sdim (EXTRACT_SUBREG $src, sub1), 1814251662Sdim (EXTRACT_SUBREG $src, sub2)), 1815251662Sdim sub3) 1816249259Sdim>; 1817249259Sdim 1818249259Sdimdef : Pat < 1819251662Sdim (i32 (sext i1:$src0)), 1820251662Sdim (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1821249259Sdim>; 1822249259Sdim 1823266715Sdimdef : Pat < 1824266715Sdim (i32 (zext i1:$src0)), 1825266715Sdim (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 1826266715Sdim>; 1827266715Sdim 1828249259Sdim// 1. Offset as 8bit DWORD immediate 1829249259Sdimdef : Pat < 1830263508Sdim (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), 1831251662Sdim (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1832249259Sdim>; 1833249259Sdim 1834249259Sdim// 2. Offset loaded in an 32bit SGPR 1835249259Sdimdef : Pat < 1836263508Sdim (SIload_constant i128:$sbase, imm:$offset), 1837251662Sdim (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1838249259Sdim>; 1839249259Sdim 1840249259Sdim// 3. Offset in an 32Bit VGPR 1841249259Sdimdef : Pat < 1842263508Sdim (SIload_constant i128:$sbase, i32:$voff), 1843266715Sdim (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0) 1844249259Sdim>; 1845249259Sdim 1846251662Sdim// The multiplication scales from [0,1] to the unsigned integer range 1847251662Sdimdef : Pat < 1848251662Sdim (AMDGPUurecip i32:$src0), 1849251662Sdim (V_CVT_U32_F32_e32 1850251662Sdim (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1851251662Sdim (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1852251662Sdim>; 1853251662Sdim 1854263508Sdimdef : Pat < 1855263508Sdim (int_SI_tid), 1856263508Sdim (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1857263508Sdim (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1858263508Sdim>; 1859263508Sdim 1860249259Sdim/********** ================== **********/ 1861249259Sdim/********** VOP3 Patterns **********/ 1862249259Sdim/********** ================== **********/ 1863249259Sdim 1864251662Sdimdef : Pat < 1865251662Sdim (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1866251662Sdim (V_MAD_F32 $src0, $src1, $src2) 1867251662Sdim>; 1868249259Sdim 1869263508Sdim/********** ======================= **********/ 1870263508Sdim/********** Load/Store Patterns **********/ 1871263508Sdim/********** ======================= **********/ 1872263508Sdim 1873263508Sdimclass DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 1874263508Sdim (frag i32:$src0), 1875263508Sdim (vt (inst 0, $src0, $src0, $src0, 0, 0)) 1876263508Sdim>; 1877263508Sdim 1878263508Sdimdef : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 1879263508Sdimdef : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 1880263508Sdimdef : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 1881263508Sdimdef : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 1882263508Sdimdef : DSReadPat <DS_READ_B32, i32, local_load>; 1883263508Sdimdef : Pat < 1884263508Sdim (local_load i32:$src0), 1885263508Sdim (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0)) 1886263508Sdim>; 1887263508Sdim 1888263508Sdimclass DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 1889263508Sdim (frag i32:$src1, i32:$src0), 1890263508Sdim (inst 0, $src0, $src1, $src1, 0, 0) 1891263508Sdim>; 1892263508Sdim 1893263508Sdimdef : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 1894263508Sdimdef : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 1895263508Sdimdef : DSWritePat <DS_WRITE_B32, i32, local_store>; 1896263508Sdim 1897263508Sdimdef : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 1898263508Sdim (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>; 1899263508Sdim 1900263508Sdimdef : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 1901263508Sdim (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>; 1902263508Sdim 1903249259Sdim/********** ================== **********/ 1904249259Sdim/********** SMRD Patterns **********/ 1905249259Sdim/********** ================== **********/ 1906249259Sdim 1907249259Sdimmulticlass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1908251662Sdim 1909249259Sdim // 1. Offset as 8bit DWORD immediate 1910249259Sdim def : Pat < 1911251662Sdim (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1912251662Sdim (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1913249259Sdim >; 1914249259Sdim 1915249259Sdim // 2. Offset loaded in an 32bit SGPR 1916249259Sdim def : Pat < 1917251662Sdim (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1918251662Sdim (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1919249259Sdim >; 1920249259Sdim 1921249259Sdim // 3. No offset at all 1922249259Sdim def : Pat < 1923251662Sdim (constant_load i64:$sbase), 1924251662Sdim (vt (Instr_IMM $sbase, 0)) 1925249259Sdim >; 1926249259Sdim} 1927249259Sdim 1928249259Sdimdefm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1929249259Sdimdefm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1930263508Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1931263508Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1932263508Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>; 1933263508Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1934249259Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1935263508Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1936263508Sdimdefm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1937249259Sdim 1938263508Sdim//===----------------------------------------------------------------------===// 1939263508Sdim// MUBUF Patterns 1940263508Sdim//===----------------------------------------------------------------------===// 1941263508Sdim 1942263508Sdimmulticlass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 1943263508Sdim PatFrag global_ld, PatFrag constant_ld> { 1944263508Sdim def : Pat < 1945263508Sdim (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 1946263508Sdim (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 1947263508Sdim >; 1948263508Sdim 1949263508Sdim def : Pat < 1950263508Sdim (vt (global_ld i64:$ptr)), 1951263508Sdim (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1952263508Sdim >; 1953263508Sdim 1954263508Sdim def : Pat < 1955263508Sdim (vt (global_ld (add i64:$ptr, i64:$offset))), 1956263508Sdim (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1957263508Sdim >; 1958263508Sdim 1959263508Sdim def : Pat < 1960263508Sdim (vt (constant_ld (add i64:$ptr, i64:$offset))), 1961263508Sdim (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1962263508Sdim >; 1963263508Sdim} 1964263508Sdim 1965263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 1966263508Sdim sextloadi8_global, sextloadi8_constant>; 1967263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 1968263508Sdim az_extloadi8_global, az_extloadi8_constant>; 1969263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 1970263508Sdim sextloadi16_global, sextloadi16_constant>; 1971263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 1972263508Sdim az_extloadi16_global, az_extloadi16_constant>; 1973263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 1974263508Sdim global_load, constant_load>; 1975263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1976263508Sdim global_load, constant_load>; 1977263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1978263508Sdim az_extloadi32_global, az_extloadi32_constant>; 1979263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 1980263508Sdim global_load, constant_load>; 1981263508Sdimdefm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 1982263508Sdim global_load, constant_load>; 1983263508Sdim 1984263508Sdimmulticlass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 1985263508Sdim 1986263508Sdim def : Pat < 1987263508Sdim (st vt:$value, i64:$ptr), 1988263508Sdim (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1989263508Sdim >; 1990263508Sdim 1991263508Sdim def : Pat < 1992263508Sdim (st vt:$value, (add i64:$ptr, i64:$offset)), 1993263508Sdim (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 1994263508Sdim >; 1995263508Sdim} 1996263508Sdim 1997263508Sdimdefm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 1998263508Sdimdefm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 1999263508Sdimdefm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 2000263508Sdimdefm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 2001263508Sdimdefm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 2002263508Sdimdefm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 2003263508Sdim 2004266715Sdim// BUFFER_LOAD_DWORD*, addr64=0 2005266715Sdimmulticlass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 2006266715Sdim MUBUF bothen> { 2007266715Sdim 2008266715Sdim def : Pat < 2009266715Sdim (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2010266715Sdim imm:$offset, 0, 0, imm:$glc, imm:$slc, 2011266715Sdim imm:$tfe)), 2012266715Sdim (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2013266715Sdim (as_i1imm $slc), (as_i1imm $tfe)) 2014266715Sdim >; 2015266715Sdim 2016266715Sdim def : Pat < 2017266715Sdim (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2018266715Sdim imm, 1, 0, imm:$glc, imm:$slc, 2019266715Sdim imm:$tfe)), 2020266715Sdim (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2021266715Sdim (as_i1imm $tfe)) 2022266715Sdim >; 2023266715Sdim 2024266715Sdim def : Pat < 2025266715Sdim (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2026266715Sdim imm:$offset, 0, 1, imm:$glc, imm:$slc, 2027266715Sdim imm:$tfe)), 2028266715Sdim (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2029266715Sdim (as_i1imm $slc), (as_i1imm $tfe)) 2030266715Sdim >; 2031266715Sdim 2032266715Sdim def : Pat < 2033266715Sdim (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset, 2034266715Sdim imm, 1, 1, imm:$glc, imm:$slc, 2035266715Sdim imm:$tfe)), 2036266715Sdim (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2037266715Sdim (as_i1imm $tfe)) 2038266715Sdim >; 2039266715Sdim} 2040266715Sdim 2041266715Sdimdefm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 2042266715Sdim BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 2043266715Sdimdefm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 2044266715Sdim BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 2045266715Sdimdefm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 2046266715Sdim BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 2047266715Sdim 2048263508Sdim//===----------------------------------------------------------------------===// 2049263508Sdim// MTBUF Patterns 2050263508Sdim//===----------------------------------------------------------------------===// 2051263508Sdim 2052263508Sdim// TBUFFER_STORE_FORMAT_*, addr64=0 2053263508Sdimclass MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 2054263508Sdim (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 2055263508Sdim i32:$soffset, imm:$inst_offset, imm:$dfmt, 2056263508Sdim imm:$nfmt, imm:$offen, imm:$idxen, 2057263508Sdim imm:$glc, imm:$slc, imm:$tfe), 2058263508Sdim (opcode 2059263508Sdim $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 2060263508Sdim (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 2061263508Sdim (as_i1imm $slc), (as_i1imm $tfe), $soffset) 2062263508Sdim>; 2063263508Sdim 2064263508Sdimdef : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 2065263508Sdimdef : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 2066263508Sdimdef : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 2067263508Sdimdef : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 2068263508Sdim 2069249259Sdim/********** ====================== **********/ 2070249259Sdim/********** Indirect adressing **********/ 2071249259Sdim/********** ====================== **********/ 2072249259Sdim 2073251662Sdimmulticlass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 2074251662Sdim 2075249259Sdim // 1. Extract with offset 2076249259Sdim def : Pat< 2077263508Sdim (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 2078251662Sdim (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 2079249259Sdim >; 2080249259Sdim 2081249259Sdim // 2. Extract without offset 2082249259Sdim def : Pat< 2083263508Sdim (vector_extract vt:$vec, i32:$idx), 2084251662Sdim (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 2085249259Sdim >; 2086249259Sdim 2087249259Sdim // 3. Insert with offset 2088249259Sdim def : Pat< 2089263508Sdim (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), 2090251662Sdim (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 2091249259Sdim >; 2092249259Sdim 2093249259Sdim // 4. Insert without offset 2094249259Sdim def : Pat< 2095263508Sdim (vector_insert vt:$vec, f32:$val, i32:$idx), 2096251662Sdim (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 2097249259Sdim >; 2098249259Sdim} 2099249259Sdim 2100251662Sdimdefm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 2101251662Sdimdefm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 2102251662Sdimdefm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 2103251662Sdimdefm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 2104249259Sdim 2105249259Sdim/********** =============== **********/ 2106249259Sdim/********** Conditions **********/ 2107249259Sdim/********** =============== **********/ 2108249259Sdim 2109249259Sdimdef : Pat< 2110249259Sdim (i1 (setcc f32:$src0, f32:$src1, SETO)), 2111251662Sdim (V_CMP_O_F32_e64 $src0, $src1) 2112249259Sdim>; 2113249259Sdim 2114249259Sdimdef : Pat< 2115249259Sdim (i1 (setcc f32:$src0, f32:$src1, SETUO)), 2116251662Sdim (V_CMP_U_F32_e64 $src0, $src1) 2117249259Sdim>; 2118249259Sdim 2119263508Sdim//===----------------------------------------------------------------------===// 2120263508Sdim// Miscellaneous Patterns 2121263508Sdim//===----------------------------------------------------------------------===// 2122263508Sdim 2123263508Sdimdef : Pat < 2124263508Sdim (i64 (trunc i128:$x)), 2125263508Sdim (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2126263508Sdim (i32 (EXTRACT_SUBREG $x, sub0)), sub0), 2127263508Sdim (i32 (EXTRACT_SUBREG $x, sub1)), sub1) 2128263508Sdim>; 2129263508Sdim 2130263508Sdimdef : Pat < 2131263508Sdim (i32 (trunc i64:$a)), 2132263508Sdim (EXTRACT_SUBREG $a, sub0) 2133263508Sdim>; 2134263508Sdim 2135266715Sdimdef : Pat < 2136266715Sdim (i1 (trunc i32:$a)), 2137266715Sdim (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1) 2138266715Sdim>; 2139266715Sdim 2140263508Sdim// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector 2141263508Sdim// case, the sgpr-copies pass will fix this to use the vector version. 2142263508Sdimdef : Pat < 2143263508Sdim (i32 (addc i32:$src0, i32:$src1)), 2144263508Sdim (S_ADD_I32 $src0, $src1) 2145263508Sdim>; 2146263508Sdim 2147263508Sdimdef : Pat < 2148263508Sdim (or i64:$a, i64:$b), 2149263508Sdim (INSERT_SUBREG 2150263508Sdim (INSERT_SUBREG (IMPLICIT_DEF), 2151263508Sdim (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0), 2152263508Sdim (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1) 2153263508Sdim>; 2154263508Sdim 2155251662Sdim//============================================================================// 2156251662Sdim// Miscellaneous Optimization Patterns 2157251662Sdim//============================================================================// 2158251662Sdim 2159251662Sdimdef : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2160251662Sdim 2161249259Sdim} // End isSI predicate 2162