1249259Sdim//===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim/// \file 9249259Sdim//===----------------------------------------------------------------------===// 10249259Sdim 11249259Sdim#ifndef R600DEFINES_H_ 12249259Sdim#define R600DEFINES_H_ 13249259Sdim 14249259Sdim#include "llvm/MC/MCRegisterInfo.h" 15249259Sdim 16249259Sdim// Operand Flags 17249259Sdim#define MO_FLAG_CLAMP (1 << 0) 18249259Sdim#define MO_FLAG_NEG (1 << 1) 19249259Sdim#define MO_FLAG_ABS (1 << 2) 20249259Sdim#define MO_FLAG_MASK (1 << 3) 21249259Sdim#define MO_FLAG_PUSH (1 << 4) 22249259Sdim#define MO_FLAG_NOT_LAST (1 << 5) 23249259Sdim#define MO_FLAG_LAST (1 << 6) 24249259Sdim#define NUM_MO_FLAGS 7 25249259Sdim 26249259Sdim/// \brief Helper for getting the operand index for the instruction flags 27249259Sdim/// operand. 28249259Sdim#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3) 29249259Sdim 30249259Sdimnamespace R600_InstFlag { 31249259Sdim enum TIF { 32249259Sdim TRANS_ONLY = (1 << 0), 33249259Sdim TEX = (1 << 1), 34249259Sdim REDUCTION = (1 << 2), 35249259Sdim FC = (1 << 3), 36249259Sdim TRIG = (1 << 4), 37249259Sdim OP3 = (1 << 5), 38249259Sdim VECTOR = (1 << 6), 39249259Sdim //FlagOperand bits 7, 8 40249259Sdim NATIVE_OPERANDS = (1 << 9), 41249259Sdim OP1 = (1 << 10), 42251662Sdim OP2 = (1 << 11), 43251662Sdim VTX_INST = (1 << 12), 44263508Sdim TEX_INST = (1 << 13), 45263508Sdim ALU_INST = (1 << 14), 46263508Sdim LDS_1A = (1 << 15), 47263508Sdim LDS_1A1D = (1 << 16), 48263508Sdim IS_EXPORT = (1 << 17), 49263508Sdim LDS_1A2D = (1 << 18) 50249259Sdim }; 51249259Sdim} 52249259Sdim 53249259Sdim#define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS) 54249259Sdim 55249259Sdim/// \brief Defines for extracting register infomation from register encoding 56249259Sdim#define HW_REG_MASK 0x1ff 57249259Sdim#define HW_CHAN_SHIFT 9 58249259Sdim 59249259Sdim#define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT) 60249259Sdim#define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK) 61249259Sdim 62251662Sdim#define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST) 63251662Sdim#define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST) 64251662Sdim 65263508Sdimnamespace OpName { 66263508Sdim 67263508Sdim enum VecOps { 68263508Sdim UPDATE_EXEC_MASK_X, 69263508Sdim UPDATE_PREDICATE_X, 70263508Sdim WRITE_X, 71263508Sdim OMOD_X, 72263508Sdim DST_REL_X, 73263508Sdim CLAMP_X, 74263508Sdim SRC0_X, 75263508Sdim SRC0_NEG_X, 76263508Sdim SRC0_REL_X, 77263508Sdim SRC0_ABS_X, 78263508Sdim SRC0_SEL_X, 79263508Sdim SRC1_X, 80263508Sdim SRC1_NEG_X, 81263508Sdim SRC1_REL_X, 82263508Sdim SRC1_ABS_X, 83263508Sdim SRC1_SEL_X, 84263508Sdim PRED_SEL_X, 85263508Sdim UPDATE_EXEC_MASK_Y, 86263508Sdim UPDATE_PREDICATE_Y, 87263508Sdim WRITE_Y, 88263508Sdim OMOD_Y, 89263508Sdim DST_REL_Y, 90263508Sdim CLAMP_Y, 91263508Sdim SRC0_Y, 92263508Sdim SRC0_NEG_Y, 93263508Sdim SRC0_REL_Y, 94263508Sdim SRC0_ABS_Y, 95263508Sdim SRC0_SEL_Y, 96263508Sdim SRC1_Y, 97263508Sdim SRC1_NEG_Y, 98263508Sdim SRC1_REL_Y, 99263508Sdim SRC1_ABS_Y, 100263508Sdim SRC1_SEL_Y, 101263508Sdim PRED_SEL_Y, 102263508Sdim UPDATE_EXEC_MASK_Z, 103263508Sdim UPDATE_PREDICATE_Z, 104263508Sdim WRITE_Z, 105263508Sdim OMOD_Z, 106263508Sdim DST_REL_Z, 107263508Sdim CLAMP_Z, 108263508Sdim SRC0_Z, 109263508Sdim SRC0_NEG_Z, 110263508Sdim SRC0_REL_Z, 111263508Sdim SRC0_ABS_Z, 112263508Sdim SRC0_SEL_Z, 113263508Sdim SRC1_Z, 114263508Sdim SRC1_NEG_Z, 115263508Sdim SRC1_REL_Z, 116263508Sdim SRC1_ABS_Z, 117263508Sdim SRC1_SEL_Z, 118263508Sdim PRED_SEL_Z, 119263508Sdim UPDATE_EXEC_MASK_W, 120263508Sdim UPDATE_PREDICATE_W, 121263508Sdim WRITE_W, 122263508Sdim OMOD_W, 123263508Sdim DST_REL_W, 124263508Sdim CLAMP_W, 125263508Sdim SRC0_W, 126263508Sdim SRC0_NEG_W, 127263508Sdim SRC0_REL_W, 128263508Sdim SRC0_ABS_W, 129263508Sdim SRC0_SEL_W, 130263508Sdim SRC1_W, 131263508Sdim SRC1_NEG_W, 132263508Sdim SRC1_REL_W, 133263508Sdim SRC1_ABS_W, 134263508Sdim SRC1_SEL_W, 135263508Sdim PRED_SEL_W, 136263508Sdim IMM_0, 137263508Sdim IMM_1, 138263508Sdim VEC_COUNT 139249259Sdim }; 140249259Sdim 141249259Sdim} 142249259Sdim 143251662Sdim//===----------------------------------------------------------------------===// 144251662Sdim// Config register definitions 145251662Sdim//===----------------------------------------------------------------------===// 146251662Sdim 147251662Sdim#define R_02880C_DB_SHADER_CONTROL 0x02880C 148251662Sdim#define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6) 149251662Sdim 150251662Sdim// These fields are the same for all shader types and families. 151251662Sdim#define S_NUM_GPRS(x) (((x) & 0xFF) << 0) 152251662Sdim#define S_STACK_SIZE(x) (((x) & 0xFF) << 8) 153251662Sdim//===----------------------------------------------------------------------===// 154251662Sdim// R600, R700 Registers 155251662Sdim//===----------------------------------------------------------------------===// 156251662Sdim 157251662Sdim#define R_028850_SQ_PGM_RESOURCES_PS 0x028850 158251662Sdim#define R_028868_SQ_PGM_RESOURCES_VS 0x028868 159251662Sdim 160251662Sdim//===----------------------------------------------------------------------===// 161251662Sdim// Evergreen, Northern Islands Registers 162251662Sdim//===----------------------------------------------------------------------===// 163251662Sdim 164251662Sdim#define R_028844_SQ_PGM_RESOURCES_PS 0x028844 165251662Sdim#define R_028860_SQ_PGM_RESOURCES_VS 0x028860 166251662Sdim#define R_028878_SQ_PGM_RESOURCES_GS 0x028878 167251662Sdim#define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4 168251662Sdim 169263508Sdim#define R_0288E8_SQ_LDS_ALLOC 0x0288E8 170263508Sdim 171249259Sdim#endif // R600DEFINES_H_ 172