1249259Sdim//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief TargetRegisterInfo interface that is implemented by all hw codegen 12249259Sdim/// targets. 13249259Sdim// 14249259Sdim//===----------------------------------------------------------------------===// 15249259Sdim 16249259Sdim#ifndef AMDGPUREGISTERINFO_H 17249259Sdim#define AMDGPUREGISTERINFO_H 18249259Sdim 19249259Sdim#include "llvm/ADT/BitVector.h" 20249259Sdim#include "llvm/Target/TargetRegisterInfo.h" 21249259Sdim 22249259Sdim#define GET_REGINFO_HEADER 23249259Sdim#define GET_REGINFO_ENUM 24249259Sdim#include "AMDGPUGenRegisterInfo.inc" 25249259Sdim 26249259Sdimnamespace llvm { 27249259Sdim 28249259Sdimclass AMDGPUTargetMachine; 29249259Sdimclass TargetInstrInfo; 30249259Sdim 31249259Sdimstruct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { 32249259Sdim TargetMachine &TM; 33249259Sdim static const uint16_t CalleeSavedReg; 34249259Sdim 35263508Sdim AMDGPURegisterInfo(TargetMachine &tm); 36249259Sdim 37249259Sdim virtual BitVector getReservedRegs(const MachineFunction &MF) const { 38249259Sdim assert(!"Unimplemented"); return BitVector(); 39249259Sdim } 40249259Sdim 41249259Sdim /// \param RC is an AMDIL reg class. 42249259Sdim /// 43249259Sdim /// \returns The ISA reg class that is equivalent to \p RC. 44249259Sdim virtual const TargetRegisterClass * getISARegClass( 45249259Sdim const TargetRegisterClass * RC) const { 46249259Sdim assert(!"Unimplemented"); return NULL; 47249259Sdim } 48249259Sdim 49249259Sdim virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const { 50249259Sdim assert(!"Unimplemented"); return NULL; 51249259Sdim } 52249259Sdim 53263508Sdim virtual unsigned getHWRegIndex(unsigned Reg) const { 54263508Sdim assert(!"Unimplemented"); return 0; 55263508Sdim } 56263508Sdim 57263508Sdim /// \returns the sub reg enum value for the given \p Channel 58263508Sdim /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) 59263508Sdim unsigned getSubRegFromChannel(unsigned Channel) const; 60263508Sdim 61249259Sdim const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const; 62249259Sdim void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 63249259Sdim unsigned FIOperandNum, 64249259Sdim RegScavenger *RS) const; 65249259Sdim unsigned getFrameRegister(const MachineFunction &MF) const; 66249259Sdim 67249259Sdim unsigned getIndirectSubReg(unsigned IndirectIndex) const; 68249259Sdim 69249259Sdim}; 70249259Sdim 71249259Sdim} // End namespace llvm 72249259Sdim 73249259Sdim#endif // AMDIDSAREGISTERINFO_H 74