AMDGPUInstructions.td revision 256281
1//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains instruction defs that are common to all hw codegen 11// targets. 12// 13//===----------------------------------------------------------------------===// 14 15class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction { 16 field bit isRegisterLoad = 0; 17 field bit isRegisterStore = 0; 18 19 let Namespace = "AMDGPU"; 20 let OutOperandList = outs; 21 let InOperandList = ins; 22 let AsmString = asm; 23 let Pattern = pattern; 24 let Itinerary = NullALU; 25 26 let TSFlags{63} = isRegisterLoad; 27 let TSFlags{62} = isRegisterStore; 28} 29 30class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern> 31 : AMDGPUInst<outs, ins, asm, pattern> { 32 33 field bits<32> Inst = 0xffffffff; 34 35} 36 37def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>; 38 39def COND_EQ : PatLeaf < 40 (cond), 41 [{switch(N->get()){{default: return false; 42 case ISD::SETOEQ: case ISD::SETUEQ: 43 case ISD::SETEQ: return true;}}}] 44>; 45 46def COND_NE : PatLeaf < 47 (cond), 48 [{switch(N->get()){{default: return false; 49 case ISD::SETONE: case ISD::SETUNE: 50 case ISD::SETNE: return true;}}}] 51>; 52def COND_GT : PatLeaf < 53 (cond), 54 [{switch(N->get()){{default: return false; 55 case ISD::SETOGT: case ISD::SETUGT: 56 case ISD::SETGT: return true;}}}] 57>; 58 59def COND_GE : PatLeaf < 60 (cond), 61 [{switch(N->get()){{default: return false; 62 case ISD::SETOGE: case ISD::SETUGE: 63 case ISD::SETGE: return true;}}}] 64>; 65 66def COND_LT : PatLeaf < 67 (cond), 68 [{switch(N->get()){{default: return false; 69 case ISD::SETOLT: case ISD::SETULT: 70 case ISD::SETLT: return true;}}}] 71>; 72 73def COND_LE : PatLeaf < 74 (cond), 75 [{switch(N->get()){{default: return false; 76 case ISD::SETOLE: case ISD::SETULE: 77 case ISD::SETLE: return true;}}}] 78>; 79 80def COND_NULL : PatLeaf < 81 (cond), 82 [{return false;}] 83>; 84 85//===----------------------------------------------------------------------===// 86// Load/Store Pattern Fragments 87//===----------------------------------------------------------------------===// 88 89def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{ 90 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 91}]>; 92 93class Constants { 94int TWO_PI = 0x40c90fdb; 95int PI = 0x40490fdb; 96int TWO_PI_INV = 0x3e22f983; 97int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding 98} 99def CONST : Constants; 100 101def FP_ZERO : PatLeaf < 102 (fpimm), 103 [{return N->getValueAPF().isZero();}] 104>; 105 106def FP_ONE : PatLeaf < 107 (fpimm), 108 [{return N->isExactlyValue(1.0);}] 109>; 110 111let isCodeGenOnly = 1, isPseudo = 1 in { 112 113let usesCustomInserter = 1 in { 114 115class CLAMP <RegisterClass rc> : AMDGPUShaderInst < 116 (outs rc:$dst), 117 (ins rc:$src0), 118 "CLAMP $dst, $src0", 119 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))] 120>; 121 122class FABS <RegisterClass rc> : AMDGPUShaderInst < 123 (outs rc:$dst), 124 (ins rc:$src0), 125 "FABS $dst, $src0", 126 [(set f32:$dst, (fabs f32:$src0))] 127>; 128 129class FNEG <RegisterClass rc> : AMDGPUShaderInst < 130 (outs rc:$dst), 131 (ins rc:$src0), 132 "FNEG $dst, $src0", 133 [(set f32:$dst, (fneg f32:$src0))] 134>; 135 136} // usesCustomInserter = 1 137 138multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, 139 ComplexPattern addrPat> { 140 def RegisterLoad : AMDGPUShaderInst < 141 (outs dstClass:$dst), 142 (ins addrClass:$addr, i32imm:$chan), 143 "RegisterLoad $dst, $addr", 144 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))] 145 > { 146 let isRegisterLoad = 1; 147 } 148 149 def RegisterStore : AMDGPUShaderInst < 150 (outs), 151 (ins dstClass:$val, addrClass:$addr, i32imm:$chan), 152 "RegisterStore $val, $addr", 153 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))] 154 > { 155 let isRegisterStore = 1; 156 } 157} 158 159} // End isCodeGenOnly = 1, isPseudo = 1 160 161/* Generic helper patterns for intrinsics */ 162/* -------------------------------------- */ 163 164class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul> 165 : Pat < 166 (fpow f32:$src0, f32:$src1), 167 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0))) 168>; 169 170/* Other helper patterns */ 171/* --------------------- */ 172 173/* Extract element pattern */ 174class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx, 175 SubRegIndex sub_reg> 176 : Pat< 177 (sub_type (vector_extract vec_type:$src, sub_idx)), 178 (EXTRACT_SUBREG $src, sub_reg) 179>; 180 181/* Insert element pattern */ 182class Insert_Element <ValueType elem_type, ValueType vec_type, 183 int sub_idx, SubRegIndex sub_reg> 184 : Pat < 185 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx), 186 (INSERT_SUBREG $vec, $elem, sub_reg) 187>; 188 189// Vector Build pattern 190class Vector1_Build <ValueType vecType, ValueType elemType, 191 RegisterClass rc> : Pat < 192 (vecType (build_vector elemType:$src)), 193 (vecType (COPY_TO_REGCLASS $src, rc)) 194>; 195 196class Vector2_Build <ValueType vecType, ValueType elemType> : Pat < 197 (vecType (build_vector elemType:$sub0, elemType:$sub1)), 198 (INSERT_SUBREG (INSERT_SUBREG 199 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1) 200>; 201 202class Vector4_Build <ValueType vecType, ValueType elemType> : Pat < 203 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)), 204 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 205 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3) 206>; 207 208class Vector8_Build <ValueType vecType, ValueType elemType> : Pat < 209 (vecType (build_vector elemType:$sub0, elemType:$sub1, 210 elemType:$sub2, elemType:$sub3, 211 elemType:$sub4, elemType:$sub5, 212 elemType:$sub6, elemType:$sub7)), 213 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 214 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 215 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1), 216 $sub2, sub2), $sub3, sub3), 217 $sub4, sub4), $sub5, sub5), 218 $sub6, sub6), $sub7, sub7) 219>; 220 221class Vector16_Build <ValueType vecType, ValueType elemType> : Pat < 222 (vecType (build_vector elemType:$sub0, elemType:$sub1, 223 elemType:$sub2, elemType:$sub3, 224 elemType:$sub4, elemType:$sub5, 225 elemType:$sub6, elemType:$sub7, 226 elemType:$sub8, elemType:$sub9, 227 elemType:$sub10, elemType:$sub11, 228 elemType:$sub12, elemType:$sub13, 229 elemType:$sub14, elemType:$sub15)), 230 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 231 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 232 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 233 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 234 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1), 235 $sub2, sub2), $sub3, sub3), 236 $sub4, sub4), $sub5, sub5), 237 $sub6, sub6), $sub7, sub7), 238 $sub8, sub8), $sub9, sub9), 239 $sub10, sub10), $sub11, sub11), 240 $sub12, sub12), $sub13, sub13), 241 $sub14, sub14), $sub15, sub15) 242>; 243 244// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer 245// can handle COPY instructions. 246// bitconvert pattern 247class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat < 248 (dt (bitconvert (st rc:$src0))), 249 (dt rc:$src0) 250>; 251 252// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer 253// can handle COPY instructions. 254class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat < 255 (vt (AMDGPUdwordaddr (vt rc:$addr))), 256 (vt rc:$addr) 257>; 258 259// BFI_INT patterns 260 261multiclass BFIPatterns <Instruction BFI_INT> { 262 263 // Definition from ISA doc: 264 // (y & x) | (z & ~x) 265 def : Pat < 266 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), 267 (BFI_INT $x, $y, $z) 268 >; 269 270 // SHA-256 Ch function 271 // z ^ (x & (y ^ z)) 272 def : Pat < 273 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), 274 (BFI_INT $x, $y, $z) 275 >; 276 277} 278 279// SHA-256 Ma patterns 280 281// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y 282class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat < 283 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))), 284 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y) 285>; 286 287// Bitfield extract patterns 288 289def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>; 290def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}], 291 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>; 292 293class BFEPattern <Instruction BFE> : Pat < 294 (and (srl i32:$x, legalshift32:$y), bfemask:$z), 295 (BFE $x, $y, $z) 296>; 297 298include "R600Instructions.td" 299 300include "SIInstrInfo.td" 301 302