PPCTargetMachine.cpp revision 256281 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCTargetMachine.h"
15#include "PPC.h"
16#include "llvm/CodeGen/Passes.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/PassManager.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/Target/TargetOptions.h"
23using namespace llvm;
24
25static cl::
26opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                        cl::desc("Disable CTR loops for PPC"));
28
29extern "C" void LLVMInitializePowerPCTarget() {
30  // Register the targets
31  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33}
34
35PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
36                                   StringRef CPU, StringRef FS,
37                                   const TargetOptions &Options,
38                                   Reloc::Model RM, CodeModel::Model CM,
39                                   CodeGenOpt::Level OL,
40                                   bool is64Bit)
41  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42    Subtarget(TT, CPU, FS, is64Bit),
43    DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
44    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
45    TLInfo(*this), TSInfo(*this),
46    InstrItins(Subtarget.getInstrItineraryData()) {
47
48  // The binutils for the BG/P are too old for CFI.
49  if (Subtarget.isBGP())
50    setMCUseCFI(false);
51}
52
53void PPC32TargetMachine::anchor() { }
54
55PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
56                                       StringRef CPU, StringRef FS,
57                                       const TargetOptions &Options,
58                                       Reloc::Model RM, CodeModel::Model CM,
59                                       CodeGenOpt::Level OL)
60  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
61}
62
63void PPC64TargetMachine::anchor() { }
64
65PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
66                                       StringRef CPU,  StringRef FS,
67                                       const TargetOptions &Options,
68                                       Reloc::Model RM, CodeModel::Model CM,
69                                       CodeGenOpt::Level OL)
70  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
71}
72
73
74//===----------------------------------------------------------------------===//
75// Pass Pipeline Configuration
76//===----------------------------------------------------------------------===//
77
78namespace {
79/// PPC Code Generator Pass Configuration Options.
80class PPCPassConfig : public TargetPassConfig {
81public:
82  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
83    : TargetPassConfig(TM, PM) {}
84
85  PPCTargetMachine &getPPCTargetMachine() const {
86    return getTM<PPCTargetMachine>();
87  }
88
89  const PPCSubtarget &getPPCSubtarget() const {
90    return *getPPCTargetMachine().getSubtargetImpl();
91  }
92
93  virtual bool addPreRegAlloc();
94  virtual bool addILPOpts();
95  virtual bool addInstSelector();
96  virtual bool addPreSched2();
97  virtual bool addPreEmitPass();
98};
99} // namespace
100
101TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
102  return new PPCPassConfig(this, PM);
103}
104
105bool PPCPassConfig::addPreRegAlloc() {
106  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
107    addPass(createPPCCTRLoops());
108
109  return false;
110}
111
112bool PPCPassConfig::addILPOpts() {
113  if (getPPCSubtarget().hasISEL()) {
114    addPass(&EarlyIfConverterID);
115    return true;
116  }
117
118  return false;
119}
120
121bool PPCPassConfig::addInstSelector() {
122  // Install an instruction selector.
123  addPass(createPPCISelDag(getPPCTargetMachine()));
124  return false;
125}
126
127bool PPCPassConfig::addPreSched2() {
128  if (getOptLevel() != CodeGenOpt::None)
129    addPass(&IfConverterID);
130
131  return true;
132}
133
134bool PPCPassConfig::addPreEmitPass() {
135  if (getOptLevel() != CodeGenOpt::None)
136    addPass(createPPCEarlyReturnPass());
137  // Must run branch selection immediately preceding the asm printer.
138  addPass(createPPCBranchSelectionPass());
139  return false;
140}
141
142bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
143                                      JITCodeEmitter &JCE) {
144  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
145  // writing?
146  Subtarget.SetJITMode();
147
148  // Machine code emitter pass for PowerPC.
149  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
150
151  return false;
152}
153
154void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
155  // Add first the target-independent BasicTTI pass, then our PPC pass. This
156  // allows the PPC pass to delegate to the target independent layer when
157  // appropriate.
158  PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
159  PM.add(createPPCTargetTransformInfoPass(this));
160}
161
162