PPCTargetMachine.cpp revision 234982 
1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCTargetMachine.h"
15#include "PPC.h"
16#include "llvm/PassManager.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Target/TargetOptions.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22using namespace llvm;
23
24extern "C" void LLVMInitializePowerPCTarget() {
25  // Register the targets
26  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
27  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
28}
29
30PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
31                                   StringRef CPU, StringRef FS,
32                                   const TargetOptions &Options,
33                                   Reloc::Model RM, CodeModel::Model CM,
34                                   CodeGenOpt::Level OL,
35                                   bool is64Bit)
36  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
37    Subtarget(TT, CPU, FS, is64Bit),
38    DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
39    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
40    TLInfo(*this), TSInfo(*this),
41    InstrItins(Subtarget.getInstrItineraryData()) {
42
43  // The binutils for the BG/P are too old for CFI.
44  if (Subtarget.isBGP())
45    setMCUseCFI(false);
46}
47
48void PPC32TargetMachine::anchor() { }
49
50PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
51                                       StringRef CPU, StringRef FS,
52                                       const TargetOptions &Options,
53                                       Reloc::Model RM, CodeModel::Model CM,
54                                       CodeGenOpt::Level OL)
55  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
56}
57
58void PPC64TargetMachine::anchor() { }
59
60PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
61                                       StringRef CPU,  StringRef FS,
62                                       const TargetOptions &Options,
63                                       Reloc::Model RM, CodeModel::Model CM,
64                                       CodeGenOpt::Level OL)
65  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
66}
67
68
69//===----------------------------------------------------------------------===//
70// Pass Pipeline Configuration
71//===----------------------------------------------------------------------===//
72
73namespace {
74/// PPC Code Generator Pass Configuration Options.
75class PPCPassConfig : public TargetPassConfig {
76public:
77  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
78    : TargetPassConfig(TM, PM) {}
79
80  PPCTargetMachine &getPPCTargetMachine() const {
81    return getTM<PPCTargetMachine>();
82  }
83
84  virtual bool addInstSelector();
85  virtual bool addPreEmitPass();
86};
87} // namespace
88
89TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
90  TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
91
92  // Override this for PowerPC.  Tail merging happily breaks up instruction issue
93  // groups, which typically degrades performance.
94  PassConfig->setEnableTailMerge(false);
95
96  return PassConfig;
97}
98
99bool PPCPassConfig::addInstSelector() {
100  // Install an instruction selector.
101  PM->add(createPPCISelDag(getPPCTargetMachine()));
102  return false;
103}
104
105bool PPCPassConfig::addPreEmitPass() {
106  // Must run branch selection immediately preceding the asm printer.
107  PM->add(createPPCBranchSelectionPass());
108  return false;
109}
110
111bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
112                                      JITCodeEmitter &JCE) {
113  // FIXME: This should be moved to TargetJITInfo!!
114  if (Subtarget.isPPC64())
115    // Temporary workaround for the inability of PPC64 JIT to handle jump
116    // tables.
117    Options.DisableJumpTables = true;
118
119  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
120  // writing?
121  Subtarget.SetJITMode();
122
123  // Machine code emitter pass for PowerPC.
124  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
125
126  return false;
127}
128