1234353Sdim//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===// 2234353Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7234353Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the itinerary class data for the G4+ (7450) processor. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14207618Srdivackydef IU3 : FuncUnit; // integer unit 3 (7450 simple) 15207618Srdivackydef IU4 : FuncUnit; // integer unit 4 (7450 simple) 16207618Srdivacky 17207618Srdivackydef G4PlusItineraries : ProcessorItineraries< 18218893Sdim [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [ 19239462Sdim InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 20193323Sed InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 21193323Sed InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 22193323Sed InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>, 23193323Sed InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>, 24193323Sed InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>, 25193323Sed InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>, 26193323Sed InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>, 27193323Sed InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>, 28193323Sed InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>, 29193323Sed InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 30193323Sed InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 31193323Sed InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 32193323Sed InstrItinData<BrB , [InstrStage<1, [BPU]>]>, 33193323Sed InstrItinData<BrCR , [InstrStage<2, [IU2]>]>, 34193323Sed InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>, 35193323Sed InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, 36193323Sed InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, 37193323Sed InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, 38234353Sdim InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, 39243830Sdim InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>, 40234353Sdim InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, 41243830Sdim InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>, 42193323Sed InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, 43193323Sed InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, 44243830Sdim InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>, 45243830Sdim InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>, 46193323Sed InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>, 47193323Sed InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>, 48193323Sed InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>, 49243830Sdim InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>, 50193323Sed InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>, 51193323Sed InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, 52193323Sed InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>, 53193323Sed InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, 54193323Sed InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, 55193323Sed InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>, 56243830Sdim InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>, 57193323Sed InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>, 58193323Sed InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>, 59193323Sed InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, 60193323Sed InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, 61193323Sed InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>, 62193323Sed InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>, 63193323Sed InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>, 64193323Sed InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, 65193323Sed InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, 66193323Sed InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, 67193323Sed InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>, 68193323Sed InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>, 69193323Sed InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>, 70193323Sed InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>, 71193323Sed InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, 72193323Sed InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, 73193323Sed InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>, 74243830Sdim InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>, 75193323Sed InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>, 76193323Sed InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>, 77193323Sed InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>, 78193323Sed InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>, 79193323Sed InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>, 80193323Sed InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, 81193323Sed InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, 82193323Sed InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, 83193323Sed InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>, 84193323Sed InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>, 85193323Sed InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>, 86193323Sed InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>, 87193323Sed InstrItinData<VecVSR , [InstrStage<2, [VPU]>]> 88193323Sed]>; 89