PPCRegisterInfo.td revision 223017
1193323Sed//===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13208599Srdivackylet Namespace = "PPC" in { 14208599Srdivackydef sub_lt : SubRegIndex; 15208599Srdivackydef sub_gt : SubRegIndex; 16208599Srdivackydef sub_eq : SubRegIndex; 17208599Srdivackydef sub_un : SubRegIndex; 18208599Srdivackydef sub_32 : SubRegIndex; 19208599Srdivacky} 20208599Srdivacky 21208599Srdivacky 22193323Sedclass PPCReg<string n> : Register<n> { 23193323Sed let Namespace = "PPC"; 24193323Sed} 25193323Sed 26193323Sed// We identify all our registers with a 5-bit ID, for consistency's sake. 27193323Sed 28193323Sed// GPR - One of the 32 32-bit general-purpose registers 29193323Sedclass GPR<bits<5> num, string n> : PPCReg<n> { 30193323Sed field bits<5> Num = num; 31193323Sed} 32193323Sed 33193323Sed// GP8 - One of the 32 64-bit general-purpose registers 34193323Sedclass GP8<GPR SubReg, string n> : PPCReg<n> { 35193323Sed field bits<5> Num = SubReg.Num; 36193323Sed let SubRegs = [SubReg]; 37208599Srdivacky let SubRegIndices = [sub_32]; 38193323Sed} 39193323Sed 40193323Sed// SPR - One of the 32-bit special-purpose registers 41193323Sedclass SPR<bits<10> num, string n> : PPCReg<n> { 42193323Sed field bits<10> Num = num; 43193323Sed} 44193323Sed 45193323Sed// FPR - One of the 32 64-bit floating-point registers 46193323Sedclass FPR<bits<5> num, string n> : PPCReg<n> { 47193323Sed field bits<5> Num = num; 48193323Sed} 49193323Sed 50193323Sed// VR - One of the 32 128-bit vector registers 51193323Sedclass VR<bits<5> num, string n> : PPCReg<n> { 52193323Sed field bits<5> Num = num; 53193323Sed} 54193323Sed 55193323Sed// CR - One of the 8 4-bit condition registers 56195340Sedclass CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 57193323Sed field bits<3> Num = num; 58195340Sed let SubRegs = subregs; 59193323Sed} 60193323Sed 61193323Sed// CRBIT - One of the 32 1-bit condition register fields 62193323Sedclass CRBIT<bits<5> num, string n> : PPCReg<n> { 63193323Sed field bits<5> Num = num; 64193323Sed} 65193323Sed 66193323Sed 67193323Sed// General-purpose registers 68223017Sdimdef R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>; 69223017Sdimdef R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>; 70223017Sdimdef R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>; 71223017Sdimdef R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>; 72223017Sdimdef R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>; 73223017Sdimdef R5 : GPR< 5, "r5">, DwarfRegNum<[-2, 5]>; 74223017Sdimdef R6 : GPR< 6, "r6">, DwarfRegNum<[-2, 6]>; 75223017Sdimdef R7 : GPR< 7, "r7">, DwarfRegNum<[-2, 7]>; 76223017Sdimdef R8 : GPR< 8, "r8">, DwarfRegNum<[-2, 8]>; 77223017Sdimdef R9 : GPR< 9, "r9">, DwarfRegNum<[-2, 9]>; 78223017Sdimdef R10 : GPR<10, "r10">, DwarfRegNum<[-2, 10]>; 79223017Sdimdef R11 : GPR<11, "r11">, DwarfRegNum<[-2, 11]>; 80223017Sdimdef R12 : GPR<12, "r12">, DwarfRegNum<[-2, 12]>; 81223017Sdimdef R13 : GPR<13, "r13">, DwarfRegNum<[-2, 13]>; 82223017Sdimdef R14 : GPR<14, "r14">, DwarfRegNum<[-2, 14]>; 83223017Sdimdef R15 : GPR<15, "r15">, DwarfRegNum<[-2, 15]>; 84223017Sdimdef R16 : GPR<16, "r16">, DwarfRegNum<[-2, 16]>; 85223017Sdimdef R17 : GPR<17, "r17">, DwarfRegNum<[-2, 17]>; 86223017Sdimdef R18 : GPR<18, "r18">, DwarfRegNum<[-2, 18]>; 87223017Sdimdef R19 : GPR<19, "r19">, DwarfRegNum<[-2, 19]>; 88223017Sdimdef R20 : GPR<20, "r20">, DwarfRegNum<[-2, 20]>; 89223017Sdimdef R21 : GPR<21, "r21">, DwarfRegNum<[-2, 21]>; 90223017Sdimdef R22 : GPR<22, "r22">, DwarfRegNum<[-2, 22]>; 91223017Sdimdef R23 : GPR<23, "r23">, DwarfRegNum<[-2, 23]>; 92223017Sdimdef R24 : GPR<24, "r24">, DwarfRegNum<[-2, 24]>; 93223017Sdimdef R25 : GPR<25, "r25">, DwarfRegNum<[-2, 25]>; 94223017Sdimdef R26 : GPR<26, "r26">, DwarfRegNum<[-2, 26]>; 95223017Sdimdef R27 : GPR<27, "r27">, DwarfRegNum<[-2, 27]>; 96223017Sdimdef R28 : GPR<28, "r28">, DwarfRegNum<[-2, 28]>; 97223017Sdimdef R29 : GPR<29, "r29">, DwarfRegNum<[-2, 29]>; 98223017Sdimdef R30 : GPR<30, "r30">, DwarfRegNum<[-2, 30]>; 99223017Sdimdef R31 : GPR<31, "r31">, DwarfRegNum<[-2, 31]>; 100193323Sed 101193323Sed// 64-bit General-purpose registers 102223017Sdimdef X0 : GP8< R0, "r0">, DwarfRegNum<[0, -2]>; 103223017Sdimdef X1 : GP8< R1, "r1">, DwarfRegNum<[1, -2]>; 104223017Sdimdef X2 : GP8< R2, "r2">, DwarfRegNum<[2, -2]>; 105223017Sdimdef X3 : GP8< R3, "r3">, DwarfRegNum<[3, -2]>; 106223017Sdimdef X4 : GP8< R4, "r4">, DwarfRegNum<[4, -2]>; 107223017Sdimdef X5 : GP8< R5, "r5">, DwarfRegNum<[5, -2]>; 108223017Sdimdef X6 : GP8< R6, "r6">, DwarfRegNum<[6, -2]>; 109223017Sdimdef X7 : GP8< R7, "r7">, DwarfRegNum<[7, -2]>; 110223017Sdimdef X8 : GP8< R8, "r8">, DwarfRegNum<[8, -2]>; 111223017Sdimdef X9 : GP8< R9, "r9">, DwarfRegNum<[9, -2]>; 112223017Sdimdef X10 : GP8<R10, "r10">, DwarfRegNum<[10, -2]>; 113223017Sdimdef X11 : GP8<R11, "r11">, DwarfRegNum<[11, -2]>; 114223017Sdimdef X12 : GP8<R12, "r12">, DwarfRegNum<[12, -2]>; 115223017Sdimdef X13 : GP8<R13, "r13">, DwarfRegNum<[13, -2]>; 116223017Sdimdef X14 : GP8<R14, "r14">, DwarfRegNum<[14, -2]>; 117223017Sdimdef X15 : GP8<R15, "r15">, DwarfRegNum<[15, -2]>; 118223017Sdimdef X16 : GP8<R16, "r16">, DwarfRegNum<[16, -2]>; 119223017Sdimdef X17 : GP8<R17, "r17">, DwarfRegNum<[17, -2]>; 120223017Sdimdef X18 : GP8<R18, "r18">, DwarfRegNum<[18, -2]>; 121223017Sdimdef X19 : GP8<R19, "r19">, DwarfRegNum<[19, -2]>; 122223017Sdimdef X20 : GP8<R20, "r20">, DwarfRegNum<[20, -2]>; 123223017Sdimdef X21 : GP8<R21, "r21">, DwarfRegNum<[21, -2]>; 124223017Sdimdef X22 : GP8<R22, "r22">, DwarfRegNum<[22, -2]>; 125223017Sdimdef X23 : GP8<R23, "r23">, DwarfRegNum<[23, -2]>; 126223017Sdimdef X24 : GP8<R24, "r24">, DwarfRegNum<[24, -2]>; 127223017Sdimdef X25 : GP8<R25, "r25">, DwarfRegNum<[25, -2]>; 128223017Sdimdef X26 : GP8<R26, "r26">, DwarfRegNum<[26, -2]>; 129223017Sdimdef X27 : GP8<R27, "r27">, DwarfRegNum<[27, -2]>; 130223017Sdimdef X28 : GP8<R28, "r28">, DwarfRegNum<[28, -2]>; 131223017Sdimdef X29 : GP8<R29, "r29">, DwarfRegNum<[29, -2]>; 132223017Sdimdef X30 : GP8<R30, "r30">, DwarfRegNum<[30, -2]>; 133223017Sdimdef X31 : GP8<R31, "r31">, DwarfRegNum<[31, -2]>; 134193323Sed 135193323Sed// Floating-point registers 136223017Sdimdef F0 : FPR< 0, "f0">, DwarfRegNum<[32, 32]>; 137223017Sdimdef F1 : FPR< 1, "f1">, DwarfRegNum<[33, 33]>; 138223017Sdimdef F2 : FPR< 2, "f2">, DwarfRegNum<[34, 34]>; 139223017Sdimdef F3 : FPR< 3, "f3">, DwarfRegNum<[35, 35]>; 140223017Sdimdef F4 : FPR< 4, "f4">, DwarfRegNum<[36, 36]>; 141223017Sdimdef F5 : FPR< 5, "f5">, DwarfRegNum<[37, 37]>; 142223017Sdimdef F6 : FPR< 6, "f6">, DwarfRegNum<[38, 38]>; 143223017Sdimdef F7 : FPR< 7, "f7">, DwarfRegNum<[39, 39]>; 144223017Sdimdef F8 : FPR< 8, "f8">, DwarfRegNum<[40, 40]>; 145223017Sdimdef F9 : FPR< 9, "f9">, DwarfRegNum<[41, 41]>; 146223017Sdimdef F10 : FPR<10, "f10">, DwarfRegNum<[42, 42]>; 147223017Sdimdef F11 : FPR<11, "f11">, DwarfRegNum<[43, 43]>; 148223017Sdimdef F12 : FPR<12, "f12">, DwarfRegNum<[44, 44]>; 149223017Sdimdef F13 : FPR<13, "f13">, DwarfRegNum<[45, 45]>; 150223017Sdimdef F14 : FPR<14, "f14">, DwarfRegNum<[46, 46]>; 151223017Sdimdef F15 : FPR<15, "f15">, DwarfRegNum<[47, 47]>; 152223017Sdimdef F16 : FPR<16, "f16">, DwarfRegNum<[48, 48]>; 153223017Sdimdef F17 : FPR<17, "f17">, DwarfRegNum<[49, 49]>; 154223017Sdimdef F18 : FPR<18, "f18">, DwarfRegNum<[50, 50]>; 155223017Sdimdef F19 : FPR<19, "f19">, DwarfRegNum<[51, 51]>; 156223017Sdimdef F20 : FPR<20, "f20">, DwarfRegNum<[52, 52]>; 157223017Sdimdef F21 : FPR<21, "f21">, DwarfRegNum<[53, 53]>; 158223017Sdimdef F22 : FPR<22, "f22">, DwarfRegNum<[54, 54]>; 159223017Sdimdef F23 : FPR<23, "f23">, DwarfRegNum<[55, 55]>; 160223017Sdimdef F24 : FPR<24, "f24">, DwarfRegNum<[56, 56]>; 161223017Sdimdef F25 : FPR<25, "f25">, DwarfRegNum<[57, 57]>; 162223017Sdimdef F26 : FPR<26, "f26">, DwarfRegNum<[58, 58]>; 163223017Sdimdef F27 : FPR<27, "f27">, DwarfRegNum<[59, 59]>; 164223017Sdimdef F28 : FPR<28, "f28">, DwarfRegNum<[60, 60]>; 165223017Sdimdef F29 : FPR<29, "f29">, DwarfRegNum<[61, 61]>; 166223017Sdimdef F30 : FPR<30, "f30">, DwarfRegNum<[62, 62]>; 167223017Sdimdef F31 : FPR<31, "f31">, DwarfRegNum<[63, 63]>; 168193323Sed 169193323Sed// Vector registers 170223017Sdimdef V0 : VR< 0, "v0">, DwarfRegNum<[77, 77]>; 171223017Sdimdef V1 : VR< 1, "v1">, DwarfRegNum<[78, 78]>; 172223017Sdimdef V2 : VR< 2, "v2">, DwarfRegNum<[79, 79]>; 173223017Sdimdef V3 : VR< 3, "v3">, DwarfRegNum<[80, 80]>; 174223017Sdimdef V4 : VR< 4, "v4">, DwarfRegNum<[81, 81]>; 175223017Sdimdef V5 : VR< 5, "v5">, DwarfRegNum<[82, 82]>; 176223017Sdimdef V6 : VR< 6, "v6">, DwarfRegNum<[83, 83]>; 177223017Sdimdef V7 : VR< 7, "v7">, DwarfRegNum<[84, 84]>; 178223017Sdimdef V8 : VR< 8, "v8">, DwarfRegNum<[85, 85]>; 179223017Sdimdef V9 : VR< 9, "v9">, DwarfRegNum<[86, 86]>; 180223017Sdimdef V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>; 181223017Sdimdef V11 : VR<11, "v11">, DwarfRegNum<[88, 88]>; 182223017Sdimdef V12 : VR<12, "v12">, DwarfRegNum<[89, 89]>; 183223017Sdimdef V13 : VR<13, "v13">, DwarfRegNum<[90, 90]>; 184223017Sdimdef V14 : VR<14, "v14">, DwarfRegNum<[91, 91]>; 185223017Sdimdef V15 : VR<15, "v15">, DwarfRegNum<[92, 92]>; 186223017Sdimdef V16 : VR<16, "v16">, DwarfRegNum<[93, 93]>; 187223017Sdimdef V17 : VR<17, "v17">, DwarfRegNum<[94, 94]>; 188223017Sdimdef V18 : VR<18, "v18">, DwarfRegNum<[95, 95]>; 189223017Sdimdef V19 : VR<19, "v19">, DwarfRegNum<[96, 96]>; 190223017Sdimdef V20 : VR<20, "v20">, DwarfRegNum<[97, 97]>; 191223017Sdimdef V21 : VR<21, "v21">, DwarfRegNum<[98, 98]>; 192223017Sdimdef V22 : VR<22, "v22">, DwarfRegNum<[99, 99]>; 193223017Sdimdef V23 : VR<23, "v23">, DwarfRegNum<[100, 100]>; 194223017Sdimdef V24 : VR<24, "v24">, DwarfRegNum<[101, 101]>; 195223017Sdimdef V25 : VR<25, "v25">, DwarfRegNum<[102, 102]>; 196223017Sdimdef V26 : VR<26, "v26">, DwarfRegNum<[103, 103]>; 197223017Sdimdef V27 : VR<27, "v27">, DwarfRegNum<[104, 104]>; 198223017Sdimdef V28 : VR<28, "v28">, DwarfRegNum<[105, 105]>; 199223017Sdimdef V29 : VR<29, "v29">, DwarfRegNum<[106, 106]>; 200223017Sdimdef V30 : VR<30, "v30">, DwarfRegNum<[107, 107]>; 201223017Sdimdef V31 : VR<31, "v31">, DwarfRegNum<[108, 108]>; 202193323Sed 203193323Sed// Condition register bits 204223017Sdimdef CR0LT : CRBIT< 0, "0">; 205223017Sdimdef CR0GT : CRBIT< 1, "1">; 206223017Sdimdef CR0EQ : CRBIT< 2, "2">; 207223017Sdimdef CR0UN : CRBIT< 3, "3">; 208223017Sdimdef CR1LT : CRBIT< 4, "4">; 209223017Sdimdef CR1GT : CRBIT< 5, "5">; 210223017Sdimdef CR1EQ : CRBIT< 6, "6">; 211223017Sdimdef CR1UN : CRBIT< 7, "7">; 212223017Sdimdef CR2LT : CRBIT< 8, "8">; 213223017Sdimdef CR2GT : CRBIT< 9, "9">; 214223017Sdimdef CR2EQ : CRBIT<10, "10">; 215223017Sdimdef CR2UN : CRBIT<11, "11">; 216223017Sdimdef CR3LT : CRBIT<12, "12">; 217223017Sdimdef CR3GT : CRBIT<13, "13">; 218223017Sdimdef CR3EQ : CRBIT<14, "14">; 219223017Sdimdef CR3UN : CRBIT<15, "15">; 220223017Sdimdef CR4LT : CRBIT<16, "16">; 221223017Sdimdef CR4GT : CRBIT<17, "17">; 222223017Sdimdef CR4EQ : CRBIT<18, "18">; 223223017Sdimdef CR4UN : CRBIT<19, "19">; 224223017Sdimdef CR5LT : CRBIT<20, "20">; 225223017Sdimdef CR5GT : CRBIT<21, "21">; 226223017Sdimdef CR5EQ : CRBIT<22, "22">; 227223017Sdimdef CR5UN : CRBIT<23, "23">; 228223017Sdimdef CR6LT : CRBIT<24, "24">; 229223017Sdimdef CR6GT : CRBIT<25, "25">; 230223017Sdimdef CR6EQ : CRBIT<26, "26">; 231223017Sdimdef CR6UN : CRBIT<27, "27">; 232223017Sdimdef CR7LT : CRBIT<28, "28">; 233223017Sdimdef CR7GT : CRBIT<29, "29">; 234223017Sdimdef CR7EQ : CRBIT<30, "30">; 235223017Sdimdef CR7UN : CRBIT<31, "31">; 236193323Sed 237195340Sed// Condition registers 238208599Srdivackylet SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 239223017Sdimdef CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 240223017Sdimdef CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 241223017Sdimdef CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 242223017Sdimdef CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 243223017Sdimdef CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 244223017Sdimdef CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 245223017Sdimdef CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 246223017Sdimdef CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 247208599Srdivacky} 248195340Sed 249193323Sed// Link register 250223017Sdimdef LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 251193323Sed//let Aliases = [LR] in 252223017Sdimdef LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 253193323Sed 254193323Sed// Count register 255223017Sdimdef CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 256223017Sdimdef CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 257193323Sed 258193323Sed// VRsave register 259223017Sdimdef VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>; 260193323Sed 261198090Srdivacky// Carry bit. In the architecture this is really bit 0 of the XER register 262198090Srdivacky// (which really is SPR register 1); this is the only bit interesting to a 263198090Srdivacky// compiler. 264223017Sdimdef CARRY: SPR<1, "ca">; 265198090Srdivacky 266193323Sed// FP rounding mode: bits 30 and 31 of the FP status and control register 267193323Sed// This is not allocated as a normal register; it appears only in 268193323Sed// Uses and Defs. The ABI says it needs to be preserved by a function, 269193323Sed// but this is not achieved by saving and restoring it as with 270193323Sed// most registers, it has to be done in code; to make this work all the 271193323Sed// return and call instructions are described as Uses of RM, so instructions 272193323Sed// that do nothing but change RM will not get deleted. 273193323Sed// Also, in the architecture it is not really a SPR; 512 is arbitrary. 274223017Sdimdef RM: SPR<512, "**ROUNDING MODE**">; 275193323Sed 276193323Sed/// Register classes 277193323Sed// Allocate volatiles first 278193323Sed// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 279193323Seddef GPRC : RegisterClass<"PPC", [i32], 32, 280193323Sed [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, 281193323Sed R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, 282223017Sdim R16, R15, R14, R13, R31, R0, R1, LR]>; 283223017Sdim 284193323Seddef G8RC : RegisterClass<"PPC", [i64], 64, 285193323Sed [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, 286193323Sed X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17, 287223017Sdim X16, X15, X14, X31, X13, X0, X1, LR8]>; 288193323Sed 289195340Sed// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 290195340Sed// ABI the size of the Floating-point register save area is determined by the 291195340Sed// allocated non-volatile register with the lowest register number, as FP 292195340Sed// register N is spilled to offset 8 * (32 - N) below the back chain word of the 293195340Sed// previous stack frame. By allocating non-volatiles in reverse order we make 294195340Sed// sure that the Floating-point register save area is always as small as 295195340Sed// possible because there aren't any unused spill slots. 296193323Seddef F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7, 297195340Sed F8, F9, F10, F11, F12, F13, F31, F30, F29, F28, F27, F26, F25, F24, F23, 298195340Sed F22, F21, F20, F19, F18, F17, F16, F15, F14]>; 299193323Seddef F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, 300195340Sed F8, F9, F10, F11, F12, F13, F31, F30, F29, F28, F27, F26, F25, F24, F23, 301195340Sed F22, F21, F20, F19, F18, F17, F16, F15, F14]>; 302193323Sed 303193323Seddef VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 304193323Sed [V2, V3, V4, V5, V0, V1, 305195340Sed V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 306195340Sed V29, V28, V27, V26, V25, V24, V23, V22, V21, V20]>; 307193323Sed 308193323Seddef CRBITRC : RegisterClass<"PPC", [i32], 32, 309193323Sed [CR0LT, CR0GT, CR0EQ, CR0UN, 310193323Sed CR1LT, CR1GT, CR1EQ, CR1UN, 311193323Sed CR2LT, CR2GT, CR2EQ, CR2UN, 312193323Sed CR3LT, CR3GT, CR3EQ, CR3UN, 313193323Sed CR4LT, CR4GT, CR4EQ, CR4UN, 314193323Sed CR5LT, CR5GT, CR5EQ, CR5UN, 315193323Sed CR6LT, CR6GT, CR6EQ, CR6UN, 316193323Sed CR7LT, CR7GT, CR7EQ, CR7UN 317193323Sed ]> 318193323Sed{ 319193323Sed let CopyCost = -1; 320193323Sed} 321193323Sed 322195340Seddef CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 323195340Sed CR3, CR4]> 324195340Sed{ 325208599Srdivacky let SubRegClasses = [(CRBITRC sub_lt, sub_gt, sub_eq, sub_un)]; 326195340Sed} 327193323Sed 328193323Seddef CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>; 329193323Seddef CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>; 330195340Seddef VRSAVERC : RegisterClass<"PPC", [i32], 32, [VRSAVE]>; 331198090Srdivackydef CARRYRC : RegisterClass<"PPC", [i32], 32, [CARRY]> { 332198090Srdivacky let CopyCost = -1; 333198090Srdivacky} 334