PPCRegisterInfo.td revision 195340
1//===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13class PPCReg<string n> : Register<n> { 14 let Namespace = "PPC"; 15} 16 17// We identify all our registers with a 5-bit ID, for consistency's sake. 18 19// GPR - One of the 32 32-bit general-purpose registers 20class GPR<bits<5> num, string n> : PPCReg<n> { 21 field bits<5> Num = num; 22} 23 24// GP8 - One of the 32 64-bit general-purpose registers 25class GP8<GPR SubReg, string n> : PPCReg<n> { 26 field bits<5> Num = SubReg.Num; 27 let SubRegs = [SubReg]; 28} 29 30// SPR - One of the 32-bit special-purpose registers 31class SPR<bits<10> num, string n> : PPCReg<n> { 32 field bits<10> Num = num; 33} 34 35// FPR - One of the 32 64-bit floating-point registers 36class FPR<bits<5> num, string n> : PPCReg<n> { 37 field bits<5> Num = num; 38} 39 40// VR - One of the 32 128-bit vector registers 41class VR<bits<5> num, string n> : PPCReg<n> { 42 field bits<5> Num = num; 43} 44 45// CR - One of the 8 4-bit condition registers 46class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 47 field bits<3> Num = num; 48 let SubRegs = subregs; 49} 50 51// CRBIT - One of the 32 1-bit condition register fields 52class CRBIT<bits<5> num, string n> : PPCReg<n> { 53 field bits<5> Num = num; 54} 55 56 57// General-purpose registers 58def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>; 59def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>; 60def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>; 61def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>; 62def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>; 63def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>; 64def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>; 65def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>; 66def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>; 67def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>; 68def R10 : GPR<10, "r10">, DwarfRegNum<[10]>; 69def R11 : GPR<11, "r11">, DwarfRegNum<[11]>; 70def R12 : GPR<12, "r12">, DwarfRegNum<[12]>; 71def R13 : GPR<13, "r13">, DwarfRegNum<[13]>; 72def R14 : GPR<14, "r14">, DwarfRegNum<[14]>; 73def R15 : GPR<15, "r15">, DwarfRegNum<[15]>; 74def R16 : GPR<16, "r16">, DwarfRegNum<[16]>; 75def R17 : GPR<17, "r17">, DwarfRegNum<[17]>; 76def R18 : GPR<18, "r18">, DwarfRegNum<[18]>; 77def R19 : GPR<19, "r19">, DwarfRegNum<[19]>; 78def R20 : GPR<20, "r20">, DwarfRegNum<[20]>; 79def R21 : GPR<21, "r21">, DwarfRegNum<[21]>; 80def R22 : GPR<22, "r22">, DwarfRegNum<[22]>; 81def R23 : GPR<23, "r23">, DwarfRegNum<[23]>; 82def R24 : GPR<24, "r24">, DwarfRegNum<[24]>; 83def R25 : GPR<25, "r25">, DwarfRegNum<[25]>; 84def R26 : GPR<26, "r26">, DwarfRegNum<[26]>; 85def R27 : GPR<27, "r27">, DwarfRegNum<[27]>; 86def R28 : GPR<28, "r28">, DwarfRegNum<[28]>; 87def R29 : GPR<29, "r29">, DwarfRegNum<[29]>; 88def R30 : GPR<30, "r30">, DwarfRegNum<[30]>; 89def R31 : GPR<31, "r31">, DwarfRegNum<[31]>; 90 91// 64-bit General-purpose registers 92def X0 : GP8< R0, "r0">, DwarfRegNum<[0]>; 93def X1 : GP8< R1, "r1">, DwarfRegNum<[1]>; 94def X2 : GP8< R2, "r2">, DwarfRegNum<[2]>; 95def X3 : GP8< R3, "r3">, DwarfRegNum<[3]>; 96def X4 : GP8< R4, "r4">, DwarfRegNum<[4]>; 97def X5 : GP8< R5, "r5">, DwarfRegNum<[5]>; 98def X6 : GP8< R6, "r6">, DwarfRegNum<[6]>; 99def X7 : GP8< R7, "r7">, DwarfRegNum<[7]>; 100def X8 : GP8< R8, "r8">, DwarfRegNum<[8]>; 101def X9 : GP8< R9, "r9">, DwarfRegNum<[9]>; 102def X10 : GP8<R10, "r10">, DwarfRegNum<[10]>; 103def X11 : GP8<R11, "r11">, DwarfRegNum<[11]>; 104def X12 : GP8<R12, "r12">, DwarfRegNum<[12]>; 105def X13 : GP8<R13, "r13">, DwarfRegNum<[13]>; 106def X14 : GP8<R14, "r14">, DwarfRegNum<[14]>; 107def X15 : GP8<R15, "r15">, DwarfRegNum<[15]>; 108def X16 : GP8<R16, "r16">, DwarfRegNum<[16]>; 109def X17 : GP8<R17, "r17">, DwarfRegNum<[17]>; 110def X18 : GP8<R18, "r18">, DwarfRegNum<[18]>; 111def X19 : GP8<R19, "r19">, DwarfRegNum<[19]>; 112def X20 : GP8<R20, "r20">, DwarfRegNum<[20]>; 113def X21 : GP8<R21, "r21">, DwarfRegNum<[21]>; 114def X22 : GP8<R22, "r22">, DwarfRegNum<[22]>; 115def X23 : GP8<R23, "r23">, DwarfRegNum<[23]>; 116def X24 : GP8<R24, "r24">, DwarfRegNum<[24]>; 117def X25 : GP8<R25, "r25">, DwarfRegNum<[25]>; 118def X26 : GP8<R26, "r26">, DwarfRegNum<[26]>; 119def X27 : GP8<R27, "r27">, DwarfRegNum<[27]>; 120def X28 : GP8<R28, "r28">, DwarfRegNum<[28]>; 121def X29 : GP8<R29, "r29">, DwarfRegNum<[29]>; 122def X30 : GP8<R30, "r30">, DwarfRegNum<[30]>; 123def X31 : GP8<R31, "r31">, DwarfRegNum<[31]>; 124 125// Floating-point registers 126def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 127def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 128def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 129def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 130def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 131def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 132def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 133def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 134def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 135def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 136def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 137def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 138def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 139def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 140def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 141def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 142def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 143def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 144def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 145def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 146def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 147def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 148def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 149def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 150def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 151def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 152def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 153def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 154def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 155def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 156def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 157def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 158 159// Vector registers 160def V0 : VR< 0, "v0">, DwarfRegNum<[77]>; 161def V1 : VR< 1, "v1">, DwarfRegNum<[78]>; 162def V2 : VR< 2, "v2">, DwarfRegNum<[79]>; 163def V3 : VR< 3, "v3">, DwarfRegNum<[80]>; 164def V4 : VR< 4, "v4">, DwarfRegNum<[81]>; 165def V5 : VR< 5, "v5">, DwarfRegNum<[82]>; 166def V6 : VR< 6, "v6">, DwarfRegNum<[83]>; 167def V7 : VR< 7, "v7">, DwarfRegNum<[84]>; 168def V8 : VR< 8, "v8">, DwarfRegNum<[85]>; 169def V9 : VR< 9, "v9">, DwarfRegNum<[86]>; 170def V10 : VR<10, "v10">, DwarfRegNum<[87]>; 171def V11 : VR<11, "v11">, DwarfRegNum<[88]>; 172def V12 : VR<12, "v12">, DwarfRegNum<[89]>; 173def V13 : VR<13, "v13">, DwarfRegNum<[90]>; 174def V14 : VR<14, "v14">, DwarfRegNum<[91]>; 175def V15 : VR<15, "v15">, DwarfRegNum<[92]>; 176def V16 : VR<16, "v16">, DwarfRegNum<[93]>; 177def V17 : VR<17, "v17">, DwarfRegNum<[94]>; 178def V18 : VR<18, "v18">, DwarfRegNum<[95]>; 179def V19 : VR<19, "v19">, DwarfRegNum<[96]>; 180def V20 : VR<20, "v20">, DwarfRegNum<[97]>; 181def V21 : VR<21, "v21">, DwarfRegNum<[98]>; 182def V22 : VR<22, "v22">, DwarfRegNum<[99]>; 183def V23 : VR<23, "v23">, DwarfRegNum<[100]>; 184def V24 : VR<24, "v24">, DwarfRegNum<[101]>; 185def V25 : VR<25, "v25">, DwarfRegNum<[102]>; 186def V26 : VR<26, "v26">, DwarfRegNum<[103]>; 187def V27 : VR<27, "v27">, DwarfRegNum<[104]>; 188def V28 : VR<28, "v28">, DwarfRegNum<[105]>; 189def V29 : VR<29, "v29">, DwarfRegNum<[106]>; 190def V30 : VR<30, "v30">, DwarfRegNum<[107]>; 191def V31 : VR<31, "v31">, DwarfRegNum<[108]>; 192 193// Condition register bits 194def CR0LT : CRBIT< 0, "0">, DwarfRegNum<[0]>; 195def CR0GT : CRBIT< 1, "1">, DwarfRegNum<[0]>; 196def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<[0]>; 197def CR0UN : CRBIT< 3, "3">, DwarfRegNum<[0]>; 198def CR1LT : CRBIT< 4, "4">, DwarfRegNum<[0]>; 199def CR1GT : CRBIT< 5, "5">, DwarfRegNum<[0]>; 200def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<[0]>; 201def CR1UN : CRBIT< 7, "7">, DwarfRegNum<[0]>; 202def CR2LT : CRBIT< 8, "8">, DwarfRegNum<[0]>; 203def CR2GT : CRBIT< 9, "9">, DwarfRegNum<[0]>; 204def CR2EQ : CRBIT<10, "10">, DwarfRegNum<[0]>; 205def CR2UN : CRBIT<11, "11">, DwarfRegNum<[0]>; 206def CR3LT : CRBIT<12, "12">, DwarfRegNum<[0]>; 207def CR3GT : CRBIT<13, "13">, DwarfRegNum<[0]>; 208def CR3EQ : CRBIT<14, "14">, DwarfRegNum<[0]>; 209def CR3UN : CRBIT<15, "15">, DwarfRegNum<[0]>; 210def CR4LT : CRBIT<16, "16">, DwarfRegNum<[0]>; 211def CR4GT : CRBIT<17, "17">, DwarfRegNum<[0]>; 212def CR4EQ : CRBIT<18, "18">, DwarfRegNum<[0]>; 213def CR4UN : CRBIT<19, "19">, DwarfRegNum<[0]>; 214def CR5LT : CRBIT<20, "20">, DwarfRegNum<[0]>; 215def CR5GT : CRBIT<21, "21">, DwarfRegNum<[0]>; 216def CR5EQ : CRBIT<22, "22">, DwarfRegNum<[0]>; 217def CR5UN : CRBIT<23, "23">, DwarfRegNum<[0]>; 218def CR6LT : CRBIT<24, "24">, DwarfRegNum<[0]>; 219def CR6GT : CRBIT<25, "25">, DwarfRegNum<[0]>; 220def CR6EQ : CRBIT<26, "26">, DwarfRegNum<[0]>; 221def CR6UN : CRBIT<27, "27">, DwarfRegNum<[0]>; 222def CR7LT : CRBIT<28, "28">, DwarfRegNum<[0]>; 223def CR7GT : CRBIT<29, "29">, DwarfRegNum<[0]>; 224def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>; 225def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>; 226 227// Condition registers 228def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>; 229def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>; 230def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>; 231def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71]>; 232def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>; 233def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>; 234def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>; 235def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>; 236 237def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], 238 [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>; 239def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], 240 [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>; 241def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], 242 [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>; 243def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], 244 [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>; 245 246// Link register 247def LR : SPR<8, "lr">, DwarfRegNum<[65]>; 248//let Aliases = [LR] in 249def LR8 : SPR<8, "lr">, DwarfRegNum<[65]>; 250 251// Count register 252def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>; 253def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>; 254 255// VRsave register 256def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>; 257 258// FP rounding mode: bits 30 and 31 of the FP status and control register 259// This is not allocated as a normal register; it appears only in 260// Uses and Defs. The ABI says it needs to be preserved by a function, 261// but this is not achieved by saving and restoring it as with 262// most registers, it has to be done in code; to make this work all the 263// return and call instructions are described as Uses of RM, so instructions 264// that do nothing but change RM will not get deleted. 265// Also, in the architecture it is not really a SPR; 512 is arbitrary. 266def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>; 267 268/// Register classes 269// Allocate volatiles first 270// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 271def GPRC : RegisterClass<"PPC", [i32], 32, 272 [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, 273 R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, 274 R16, R15, R14, R13, R31, R0, R1, LR]> 275{ 276 let MethodProtos = [{ 277 iterator allocation_order_begin(const MachineFunction &MF) const; 278 iterator allocation_order_end(const MachineFunction &MF) const; 279 }]; 280 let MethodBodies = [{ 281 GPRCClass::iterator 282 GPRCClass::allocation_order_begin(const MachineFunction &MF) const { 283 // In Linux, r2 is reserved for the OS. 284 if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin()) 285 return begin()+1; 286 287 return begin(); 288 } 289 GPRCClass::iterator 290 GPRCClass::allocation_order_end(const MachineFunction &MF) const { 291 // On PPC64, r13 is the thread pointer. Never allocate this register. 292 // Note that this is overconservative, as it also prevents allocation of 293 // R31 when the FP is not needed. 294 // When using the SVR4 ABI, r13 is reserved for the Small Data Area 295 // pointer. 296 const PPCSubtarget &Subtarget 297 = MF.getTarget().getSubtarget<PPCSubtarget>(); 298 299 if (Subtarget.isPPC64() || Subtarget.isSVR4ABI()) 300 return end()-5; // don't allocate R13, R31, R0, R1, LR 301 302 if (needsFP(MF)) 303 return end()-4; // don't allocate R31, R0, R1, LR 304 else 305 return end()-3; // don't allocate R0, R1, LR 306 } 307 }]; 308} 309def G8RC : RegisterClass<"PPC", [i64], 64, 310 [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, 311 X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17, 312 X16, X15, X14, X31, X13, X0, X1, LR8]> 313{ 314 let MethodProtos = [{ 315 iterator allocation_order_begin(const MachineFunction &MF) const; 316 iterator allocation_order_end(const MachineFunction &MF) const; 317 }]; 318 let MethodBodies = [{ 319 G8RCClass::iterator 320 G8RCClass::allocation_order_begin(const MachineFunction &MF) const { 321 return begin(); 322 } 323 G8RCClass::iterator 324 G8RCClass::allocation_order_end(const MachineFunction &MF) const { 325 if (needsFP(MF)) 326 return end()-5; 327 else 328 return end()-4; 329 } 330 }]; 331} 332 333// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 334// ABI the size of the Floating-point register save area is determined by the 335// allocated non-volatile register with the lowest register number, as FP 336// register N is spilled to offset 8 * (32 - N) below the back chain word of the 337// previous stack frame. By allocating non-volatiles in reverse order we make 338// sure that the Floating-point register save area is always as small as 339// possible because there aren't any unused spill slots. 340def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7, 341 F8, F9, F10, F11, F12, F13, F31, F30, F29, F28, F27, F26, F25, F24, F23, 342 F22, F21, F20, F19, F18, F17, F16, F15, F14]>; 343def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, 344 F8, F9, F10, F11, F12, F13, F31, F30, F29, F28, F27, F26, F25, F24, F23, 345 F22, F21, F20, F19, F18, F17, F16, F15, F14]>; 346 347def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 348 [V2, V3, V4, V5, V0, V1, 349 V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 350 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20]>; 351 352def CRBITRC : RegisterClass<"PPC", [i32], 32, 353 [CR0LT, CR0GT, CR0EQ, CR0UN, 354 CR1LT, CR1GT, CR1EQ, CR1UN, 355 CR2LT, CR2GT, CR2EQ, CR2UN, 356 CR3LT, CR3GT, CR3EQ, CR3UN, 357 CR4LT, CR4GT, CR4EQ, CR4UN, 358 CR5LT, CR5GT, CR5EQ, CR5UN, 359 CR6LT, CR6GT, CR6EQ, CR6UN, 360 CR7LT, CR7GT, CR7EQ, CR7UN 361 ]> 362{ 363 let CopyCost = -1; 364} 365 366def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 367 CR3, CR4]> 368{ 369 let SubRegClassList = [CRBITRC, CRBITRC, CRBITRC, CRBITRC]; 370} 371 372def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>; 373def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>; 374def VRSAVERC : RegisterClass<"PPC", [i32], 32, [VRSAVE]>; 375 376