PPCInstrInfo.td revision 205407
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutFlag]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInFlag, SDNPOutFlag]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInFlag, SDNPOutFlag]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInFlag, SDNPOutFlag]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInFlag]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 95 96// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 97// amounts. These nodes are generated by the multi-precision shift code. 98def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 99def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 100def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 101 102def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 103def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 104 [SDNPHasChain, SDNPMayStore]>; 105 106// These are target-independent nodes, but have target-specific formats. 107def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 108 [SDNPHasChain, SDNPOutFlag]>; 109def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 111 112def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 113def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 115 SDNPVariadic]>; 116def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 118 SDNPVariadic]>; 119def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>; 120def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 122def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 123 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 124def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 125 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 126def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 128def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 129 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 130 SDNPVariadic]>; 131 132def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 133 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 134 SDNPVariadic]>; 135 136def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; 138 139def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 140 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; 141 142def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 143def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 144 145def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 146 [SDNPHasChain, SDNPOptInFlag]>; 147 148def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 149 [SDNPHasChain, SDNPMayLoad]>; 150def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 151 [SDNPHasChain, SDNPMayStore]>; 152 153// Instructions to support atomic operations 154def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 155 [SDNPHasChain, SDNPMayLoad]>; 156def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 157 [SDNPHasChain, SDNPMayStore]>; 158 159// Instructions to support dynamic alloca. 160def SDTDynOp : SDTypeProfile<1, 2, []>; 161def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 162 163//===----------------------------------------------------------------------===// 164// PowerPC specific transformation functions and pattern fragments. 165// 166 167def SHL32 : SDNodeXForm<imm, [{ 168 // Transformation function: 31 - imm 169 return getI32Imm(31 - N->getZExtValue()); 170}]>; 171 172def SRL32 : SDNodeXForm<imm, [{ 173 // Transformation function: 32 - imm 174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 175}]>; 176 177def LO16 : SDNodeXForm<imm, [{ 178 // Transformation function: get the low 16 bits. 179 return getI32Imm((unsigned short)N->getZExtValue()); 180}]>; 181 182def HI16 : SDNodeXForm<imm, [{ 183 // Transformation function: shift the immediate value down into the low bits. 184 return getI32Imm((unsigned)N->getZExtValue() >> 16); 185}]>; 186 187def HA16 : SDNodeXForm<imm, [{ 188 // Transformation function: shift the immediate value down into the low bits. 189 signed int Val = N->getZExtValue(); 190 return getI32Imm((Val - (signed short)Val) >> 16); 191}]>; 192def MB : SDNodeXForm<imm, [{ 193 // Transformation function: get the start bit of a mask 194 unsigned mb = 0, me; 195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 196 return getI32Imm(mb); 197}]>; 198 199def ME : SDNodeXForm<imm, [{ 200 // Transformation function: get the end bit of a mask 201 unsigned mb, me = 0; 202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 203 return getI32Imm(me); 204}]>; 205def maskimm32 : PatLeaf<(imm), [{ 206 // maskImm predicate - True if immediate is a run of ones. 207 unsigned mb, me; 208 if (N->getValueType(0) == MVT::i32) 209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 210 else 211 return false; 212}]>; 213 214def immSExt16 : PatLeaf<(imm), [{ 215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 216 // field. Used by instructions like 'addi'. 217 if (N->getValueType(0) == MVT::i32) 218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 219 else 220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 221}]>; 222def immZExt16 : PatLeaf<(imm), [{ 223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 224 // field. Used by instructions like 'ori'. 225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 226}], LO16>; 227 228// imm16Shifted* - These match immediates where the low 16-bits are zero. There 229// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 230// identical in 32-bit mode, but in 64-bit mode, they return true if the 231// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 232// clear). 233def imm16ShiftedZExt : PatLeaf<(imm), [{ 234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 235 // immediate are set. Used by instructions like 'xoris'. 236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 237}], HI16>; 238 239def imm16ShiftedSExt : PatLeaf<(imm), [{ 240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 241 // immediate are set. Used by instructions like 'addis'. Identical to 242 // imm16ShiftedZExt in 32-bit mode. 243 if (N->getZExtValue() & 0xFFFF) return false; 244 if (N->getValueType(0) == MVT::i32) 245 return true; 246 // For 64-bit, make sure it is sext right. 247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 248}], HI16>; 249 250 251//===----------------------------------------------------------------------===// 252// PowerPC Flag Definitions. 253 254class isPPC64 { bit PPC64 = 1; } 255class isDOT { 256 list<Register> Defs = [CR0]; 257 bit RC = 1; 258} 259 260class RegConstraint<string C> { 261 string Constraints = C; 262} 263class NoEncode<string E> { 264 string DisableEncoding = E; 265} 266 267 268//===----------------------------------------------------------------------===// 269// PowerPC Operand Definitions. 270 271def s5imm : Operand<i32> { 272 let PrintMethod = "printS5ImmOperand"; 273} 274def u5imm : Operand<i32> { 275 let PrintMethod = "printU5ImmOperand"; 276} 277def u6imm : Operand<i32> { 278 let PrintMethod = "printU6ImmOperand"; 279} 280def s16imm : Operand<i32> { 281 let PrintMethod = "printS16ImmOperand"; 282} 283def u16imm : Operand<i32> { 284 let PrintMethod = "printU16ImmOperand"; 285} 286def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 287 let PrintMethod = "printS16X4ImmOperand"; 288} 289def target : Operand<OtherVT> { 290 let PrintMethod = "printBranchOperand"; 291} 292def calltarget : Operand<iPTR> { 293 let PrintMethod = "printCallOperand"; 294} 295def aaddr : Operand<iPTR> { 296 let PrintMethod = "printAbsAddrOperand"; 297} 298def piclabel: Operand<iPTR> { 299 let PrintMethod = "printPICLabel"; 300} 301def symbolHi: Operand<i32> { 302 let PrintMethod = "printSymbolHi"; 303} 304def symbolLo: Operand<i32> { 305 let PrintMethod = "printSymbolLo"; 306} 307def crbitm: Operand<i8> { 308 let PrintMethod = "printcrbitm"; 309} 310// Address operands 311def memri : Operand<iPTR> { 312 let PrintMethod = "printMemRegImm"; 313 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 314} 315def memrr : Operand<iPTR> { 316 let PrintMethod = "printMemRegReg"; 317 let MIOperandInfo = (ops ptr_rc, ptr_rc); 318} 319def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 320 let PrintMethod = "printMemRegImmShifted"; 321 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 322} 323def tocentry : Operand<iPTR> { 324 let PrintMethod = "printTOCEntryLabel"; 325 let MIOperandInfo = (ops i32imm:$imm); 326} 327 328// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 329// that doesn't matter. 330def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 331 (ops (i32 20), (i32 zero_reg))> { 332 let PrintMethod = "printPredicateOperand"; 333} 334 335// Define PowerPC specific addressing mode. 336def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 337def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 338def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 339def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 340 341/// This is just the offset part of iaddr, used for preinc. 342def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 343 344//===----------------------------------------------------------------------===// 345// PowerPC Instruction Predicate Definitions. 346def FPContractions : Predicate<"!NoExcessFPPrecision">; 347def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 348def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 349 350 351//===----------------------------------------------------------------------===// 352// PowerPC Instruction Definitions. 353 354// Pseudo-instructions: 355 356let hasCtrlDep = 1 in { 357let Defs = [R1], Uses = [R1] in { 358def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), 359 "${:comment} ADJCALLSTACKDOWN", 360 [(callseq_start timm:$amt)]>; 361def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 362 "${:comment} ADJCALLSTACKUP", 363 [(callseq_end timm:$amt1, timm:$amt2)]>; 364} 365 366def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 367 "UPDATE_VRSAVE $rD, $rS", []>; 368} 369 370let Defs = [R1], Uses = [R1] in 371def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), 372 "${:comment} DYNALLOC $result, $negsize, $fpsi", 373 [(set GPRC:$result, 374 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 375 376// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 377// instruction selection into a branch sequence. 378let usesCustomInserter = 1, // Expanded after instruction selection. 379 PPC970_Single = 1 in { 380 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 381 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 382 []>; 383 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 384 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 385 []>; 386 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 387 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 388 []>; 389 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 390 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 391 []>; 392 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 393 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 394 []>; 395} 396 397// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 398// scavenge a register for it. 399def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), 400 "${:comment} SPILL_CR $cond $F", []>; 401 402let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 403 let isReturn = 1, Uses = [LR, RM] in 404 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 405 "b${p:cc}lr ${p:reg}", BrB, 406 [(retflag)]>; 407 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 408 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 409} 410 411let Defs = [LR] in 412 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 413 PPC970_Unit_BRU; 414 415let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 416 let isBarrier = 1 in { 417 def B : IForm<18, 0, 0, (outs), (ins target:$dst), 418 "b $dst", BrB, 419 [(br bb:$dst)]>; 420 } 421 422 // BCC represents an arbitrary conditional branch on a predicate. 423 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 424 // a two-value operand where a dag node expects two operands. :( 425 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), 426 "b${cond:cc} ${cond:reg}, $dst" 427 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 428} 429 430// Darwin ABI Calls. 431let isCall = 1, PPC970_Unit = 7, 432 // All calls clobber the non-callee saved registers... 433 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 434 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 435 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 436 LR,CTR, 437 CR0,CR1,CR5,CR6,CR7,CARRY] in { 438 // Convenient aliases for call instructions 439 let Uses = [RM] in { 440 def BL_Darwin : IForm<18, 0, 1, 441 (outs), (ins calltarget:$func, variable_ops), 442 "bl $func", BrB, []>; // See Pat patterns below. 443 def BLA_Darwin : IForm<18, 1, 1, 444 (outs), (ins aaddr:$func, variable_ops), 445 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 446 } 447 let Uses = [CTR, RM] in { 448 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 449 (outs), (ins variable_ops), 450 "bctrl", BrB, 451 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 452 } 453} 454 455// SVR4 ABI Calls. 456let isCall = 1, PPC970_Unit = 7, 457 // All calls clobber the non-callee saved registers... 458 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 459 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 460 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 461 LR,CTR, 462 CR0,CR1,CR5,CR6,CR7,CARRY] in { 463 // Convenient aliases for call instructions 464 let Uses = [RM] in { 465 def BL_SVR4 : IForm<18, 0, 1, 466 (outs), (ins calltarget:$func, variable_ops), 467 "bl $func", BrB, []>; // See Pat patterns below. 468 def BLA_SVR4 : IForm<18, 1, 1, 469 (outs), (ins aaddr:$func, variable_ops), 470 "bla $func", BrB, 471 [(PPCcall_SVR4 (i32 imm:$func))]>; 472 } 473 let Uses = [CTR, RM] in { 474 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 475 (outs), (ins variable_ops), 476 "bctrl", BrB, 477 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 478 } 479} 480 481 482let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 483def TCRETURNdi :Pseudo< (outs), 484 (ins calltarget:$dst, i32imm:$offset, variable_ops), 485 "#TC_RETURNd $dst $offset", 486 []>; 487 488 489let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 490def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 491 "#TC_RETURNa $func $offset", 492 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 493 494let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 495def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops), 496 "#TC_RETURNr $dst $offset", 497 []>; 498 499 500let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 501 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 502def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 503 Requires<[In32BitMode]>; 504 505 506 507let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 508 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 509def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 510 "b $dst", BrB, 511 []>; 512 513 514let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 515 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 516def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 517 "ba $dst", BrB, 518 []>; 519 520 521// DCB* instructions. 522def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 523 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 524 PPC970_DGroup_Single; 525def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 526 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 527 PPC970_DGroup_Single; 528def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 529 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 530 PPC970_DGroup_Single; 531def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 532 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 533 PPC970_DGroup_Single; 534def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 535 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 536 PPC970_DGroup_Single; 537def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 538 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 539 PPC970_DGroup_Single; 540def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 541 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 542 PPC970_DGroup_Single; 543def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 544 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 545 PPC970_DGroup_Single; 546 547// Atomic operations 548let usesCustomInserter = 1 in { 549 let Uses = [CR0] in { 550 def ATOMIC_LOAD_ADD_I8 : Pseudo< 551 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 552 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!", 553 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 554 def ATOMIC_LOAD_SUB_I8 : Pseudo< 555 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 556 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!", 557 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 558 def ATOMIC_LOAD_AND_I8 : Pseudo< 559 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 560 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!", 561 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 562 def ATOMIC_LOAD_OR_I8 : Pseudo< 563 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 564 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!", 565 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 566 def ATOMIC_LOAD_XOR_I8 : Pseudo< 567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 568 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!", 569 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 570 def ATOMIC_LOAD_NAND_I8 : Pseudo< 571 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 572 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!", 573 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 574 def ATOMIC_LOAD_ADD_I16 : Pseudo< 575 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 576 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!", 577 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 578 def ATOMIC_LOAD_SUB_I16 : Pseudo< 579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 580 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!", 581 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 582 def ATOMIC_LOAD_AND_I16 : Pseudo< 583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 584 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!", 585 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 586 def ATOMIC_LOAD_OR_I16 : Pseudo< 587 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 588 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!", 589 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 590 def ATOMIC_LOAD_XOR_I16 : Pseudo< 591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 592 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!", 593 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 594 def ATOMIC_LOAD_NAND_I16 : Pseudo< 595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 596 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!", 597 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 598 def ATOMIC_LOAD_ADD_I32 : Pseudo< 599 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 600 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!", 601 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 602 def ATOMIC_LOAD_SUB_I32 : Pseudo< 603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 604 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!", 605 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 606 def ATOMIC_LOAD_AND_I32 : Pseudo< 607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 608 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!", 609 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 610 def ATOMIC_LOAD_OR_I32 : Pseudo< 611 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 612 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!", 613 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 614 def ATOMIC_LOAD_XOR_I32 : Pseudo< 615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 616 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!", 617 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 618 def ATOMIC_LOAD_NAND_I32 : Pseudo< 619 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 620 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!", 621 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 622 623 def ATOMIC_CMP_SWAP_I8 : Pseudo< 624 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 625 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!", 626 [(set GPRC:$dst, 627 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 628 def ATOMIC_CMP_SWAP_I16 : Pseudo< 629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 630 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!", 631 [(set GPRC:$dst, 632 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 633 def ATOMIC_CMP_SWAP_I32 : Pseudo< 634 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 635 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!", 636 [(set GPRC:$dst, 637 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 638 639 def ATOMIC_SWAP_I8 : Pseudo< 640 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 641 "${:comment} ATOMIC_SWAP_I8 PSEUDO!", 642 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 643 def ATOMIC_SWAP_I16 : Pseudo< 644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 645 "${:comment} ATOMIC_SWAP_I16 PSEUDO!", 646 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 647 def ATOMIC_SWAP_I32 : Pseudo< 648 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 649 "${:comment} ATOMIC_SWAP_I32 PSEUDO!", 650 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 651 } 652} 653 654// Instructions to support atomic operations 655def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 656 "lwarx $rD, $src", LdStLWARX, 657 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 658 659let Defs = [CR0] in 660def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 661 "stwcx. $rS, $dst", LdStSTWCX, 662 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 663 isDOT; 664 665let isBarrier = 1, hasCtrlDep = 1 in 666def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>; 667 668//===----------------------------------------------------------------------===// 669// PPC32 Load Instructions. 670// 671 672// Unindexed (r+i) Loads. 673let canFoldAsLoad = 1, PPC970_Unit = 2 in { 674def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 675 "lbz $rD, $src", LdStGeneral, 676 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 677def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 678 "lha $rD, $src", LdStLHA, 679 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 680 PPC970_DGroup_Cracked; 681def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 682 "lhz $rD, $src", LdStGeneral, 683 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 684def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 685 "lwz $rD, $src", LdStGeneral, 686 [(set GPRC:$rD, (load iaddr:$src))]>; 687 688def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 689 "lfs $rD, $src", LdStLFDU, 690 [(set F4RC:$rD, (load iaddr:$src))]>; 691def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 692 "lfd $rD, $src", LdStLFD, 693 [(set F8RC:$rD, (load iaddr:$src))]>; 694 695 696// Unindexed (r+i) Loads with Update (preinc). 697let mayLoad = 1 in { 698def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 699 "lbzu $rD, $addr", LdStGeneral, 700 []>, RegConstraint<"$addr.reg = $ea_result">, 701 NoEncode<"$ea_result">; 702 703def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 704 "lhau $rD, $addr", LdStGeneral, 705 []>, RegConstraint<"$addr.reg = $ea_result">, 706 NoEncode<"$ea_result">; 707 708def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 709 "lhzu $rD, $addr", LdStGeneral, 710 []>, RegConstraint<"$addr.reg = $ea_result">, 711 NoEncode<"$ea_result">; 712 713def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 714 "lwzu $rD, $addr", LdStGeneral, 715 []>, RegConstraint<"$addr.reg = $ea_result">, 716 NoEncode<"$ea_result">; 717 718def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 719 "lfs $rD, $addr", LdStLFDU, 720 []>, RegConstraint<"$addr.reg = $ea_result">, 721 NoEncode<"$ea_result">; 722 723def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 724 "lfd $rD, $addr", LdStLFD, 725 []>, RegConstraint<"$addr.reg = $ea_result">, 726 NoEncode<"$ea_result">; 727} 728} 729 730// Indexed (r+r) Loads. 731// 732let canFoldAsLoad = 1, PPC970_Unit = 2 in { 733def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 734 "lbzx $rD, $src", LdStGeneral, 735 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 736def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 737 "lhax $rD, $src", LdStLHA, 738 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 739 PPC970_DGroup_Cracked; 740def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 741 "lhzx $rD, $src", LdStGeneral, 742 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 743def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 744 "lwzx $rD, $src", LdStGeneral, 745 [(set GPRC:$rD, (load xaddr:$src))]>; 746 747 748def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 749 "lhbrx $rD, $src", LdStGeneral, 750 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 751def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 752 "lwbrx $rD, $src", LdStGeneral, 753 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 754 755def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 756 "lfsx $frD, $src", LdStLFDU, 757 [(set F4RC:$frD, (load xaddr:$src))]>; 758def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 759 "lfdx $frD, $src", LdStLFDU, 760 [(set F8RC:$frD, (load xaddr:$src))]>; 761} 762 763//===----------------------------------------------------------------------===// 764// PPC32 Store Instructions. 765// 766 767// Unindexed (r+i) Stores. 768let PPC970_Unit = 2 in { 769def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 770 "stb $rS, $src", LdStGeneral, 771 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 772def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 773 "sth $rS, $src", LdStGeneral, 774 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 775def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 776 "stw $rS, $src", LdStGeneral, 777 [(store GPRC:$rS, iaddr:$src)]>; 778def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 779 "stfs $rS, $dst", LdStUX, 780 [(store F4RC:$rS, iaddr:$dst)]>; 781def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 782 "stfd $rS, $dst", LdStUX, 783 [(store F8RC:$rS, iaddr:$dst)]>; 784} 785 786// Unindexed (r+i) Stores with Update (preinc). 787let PPC970_Unit = 2 in { 788def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 789 symbolLo:$ptroff, ptr_rc:$ptrreg), 790 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 791 [(set ptr_rc:$ea_res, 792 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 793 iaddroff:$ptroff))]>, 794 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 795def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 796 symbolLo:$ptroff, ptr_rc:$ptrreg), 797 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 798 [(set ptr_rc:$ea_res, 799 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 800 iaddroff:$ptroff))]>, 801 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 802def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 803 symbolLo:$ptroff, ptr_rc:$ptrreg), 804 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 805 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 806 iaddroff:$ptroff))]>, 807 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 808def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 809 symbolLo:$ptroff, ptr_rc:$ptrreg), 810 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 811 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 812 iaddroff:$ptroff))]>, 813 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 814def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 815 symbolLo:$ptroff, ptr_rc:$ptrreg), 816 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 817 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 818 iaddroff:$ptroff))]>, 819 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 820} 821 822 823// Indexed (r+r) Stores. 824// 825let PPC970_Unit = 2 in { 826def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 827 "stbx $rS, $dst", LdStGeneral, 828 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 829 PPC970_DGroup_Cracked; 830def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 831 "sthx $rS, $dst", LdStGeneral, 832 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 833 PPC970_DGroup_Cracked; 834def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 835 "stwx $rS, $dst", LdStGeneral, 836 [(store GPRC:$rS, xaddr:$dst)]>, 837 PPC970_DGroup_Cracked; 838 839let mayStore = 1 in { 840def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), 841 "stwux $rS, $rA, $rB", LdStGeneral, 842 []>; 843} 844def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 845 "sthbrx $rS, $dst", LdStGeneral, 846 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 847 PPC970_DGroup_Cracked; 848def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 849 "stwbrx $rS, $dst", LdStGeneral, 850 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 851 PPC970_DGroup_Cracked; 852 853def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 854 "stfiwx $frS, $dst", LdStUX, 855 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 856 857def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 858 "stfsx $frS, $dst", LdStUX, 859 [(store F4RC:$frS, xaddr:$dst)]>; 860def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 861 "stfdx $frS, $dst", LdStUX, 862 [(store F8RC:$frS, xaddr:$dst)]>; 863} 864 865let isBarrier = 1 in 866def SYNC : XForm_24_sync<31, 598, (outs), (ins), 867 "sync", LdStSync, 868 [(int_ppc_sync)]>; 869 870//===----------------------------------------------------------------------===// 871// PPC32 Arithmetic Instructions. 872// 873 874let PPC970_Unit = 1 in { // FXU Operations. 875def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 876 "addi $rD, $rA, $imm", IntGeneral, 877 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 878let Defs = [CARRY] in { 879def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 880 "addic $rD, $rA, $imm", IntGeneral, 881 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 882 PPC970_DGroup_Cracked; 883def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 884 "addic. $rD, $rA, $imm", IntGeneral, 885 []>; 886} 887def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 888 "addis $rD, $rA, $imm", IntGeneral, 889 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 890def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 891 "la $rD, $sym($rA)", IntGeneral, 892 [(set GPRC:$rD, (add GPRC:$rA, 893 (PPClo tglobaladdr:$sym, 0)))]>; 894def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 895 "mulli $rD, $rA, $imm", IntMulLI, 896 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 897let Defs = [CARRY] in { 898def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 899 "subfic $rD, $rA, $imm", IntGeneral, 900 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 901} 902 903let isReMaterializable = 1 in { 904 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 905 "li $rD, $imm", IntGeneral, 906 [(set GPRC:$rD, immSExt16:$imm)]>; 907 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 908 "lis $rD, $imm", IntGeneral, 909 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 910} 911} 912 913let PPC970_Unit = 1 in { // FXU Operations. 914def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 915 "andi. $dst, $src1, $src2", IntGeneral, 916 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 917 isDOT; 918def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 919 "andis. $dst, $src1, $src2", IntGeneral, 920 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 921 isDOT; 922def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 923 "ori $dst, $src1, $src2", IntGeneral, 924 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 925def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 926 "oris $dst, $src1, $src2", IntGeneral, 927 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 928def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 929 "xori $dst, $src1, $src2", IntGeneral, 930 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 931def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 932 "xoris $dst, $src1, $src2", IntGeneral, 933 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 934def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, 935 []>; 936def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 937 "cmpwi $crD, $rA, $imm", IntCompare>; 938def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 939 "cmplwi $dst, $src1, $src2", IntCompare>; 940} 941 942 943let PPC970_Unit = 1 in { // FXU Operations. 944def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 945 "nand $rA, $rS, $rB", IntGeneral, 946 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 947def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 948 "and $rA, $rS, $rB", IntGeneral, 949 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 950def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 951 "andc $rA, $rS, $rB", IntGeneral, 952 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 953def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 954 "or $rA, $rS, $rB", IntGeneral, 955 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 956def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 957 "nor $rA, $rS, $rB", IntGeneral, 958 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 959def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 960 "orc $rA, $rS, $rB", IntGeneral, 961 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 962def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 963 "eqv $rA, $rS, $rB", IntGeneral, 964 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 965def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 966 "xor $rA, $rS, $rB", IntGeneral, 967 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 968def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 969 "slw $rA, $rS, $rB", IntGeneral, 970 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 971def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 972 "srw $rA, $rS, $rB", IntGeneral, 973 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 974let Defs = [CARRY] in { 975def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 976 "sraw $rA, $rS, $rB", IntShift, 977 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 978} 979} 980 981let PPC970_Unit = 1 in { // FXU Operations. 982let Defs = [CARRY] in { 983def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 984 "srawi $rA, $rS, $SH", IntShift, 985 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 986} 987def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 988 "cntlzw $rA, $rS", IntGeneral, 989 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 990def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 991 "extsb $rA, $rS", IntGeneral, 992 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 993def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 994 "extsh $rA, $rS", IntGeneral, 995 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 996 997def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 998 "cmpw $crD, $rA, $rB", IntCompare>; 999def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1000 "cmplw $crD, $rA, $rB", IntCompare>; 1001} 1002let PPC970_Unit = 3 in { // FPU Operations. 1003//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1004// "fcmpo $crD, $fA, $fB", FPCompare>; 1005def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1006 "fcmpu $crD, $fA, $fB", FPCompare>; 1007def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1008 "fcmpu $crD, $fA, $fB", FPCompare>; 1009 1010let Uses = [RM] in { 1011 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1012 "fctiwz $frD, $frB", FPGeneral, 1013 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 1014 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1015 "frsp $frD, $frB", FPGeneral, 1016 [(set F4RC:$frD, (fround F8RC:$frB))]>; 1017 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1018 "fsqrt $frD, $frB", FPSqrt, 1019 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1020 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1021 "fsqrts $frD, $frB", FPSqrt, 1022 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1023 } 1024} 1025 1026/// FMR is split into 2 versions, one for 4/8 byte FP, and one for extending. 1027/// 1028/// Note that these are defined as pseudo-ops on the PPC970 because they are 1029/// often coalesced away and we don't want the dispatch group builder to think 1030/// that they will fill slots (which could cause the load of a LSU reject to 1031/// sneak into a d-group with a store). 1032def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1033 "fmr $frD, $frB", FPGeneral, 1034 []>, // (set F4RC:$frD, F4RC:$frB) 1035 PPC970_Unit_Pseudo; 1036def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), 1037 "fmr $frD, $frB", FPGeneral, 1038 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 1039 PPC970_Unit_Pseudo; 1040 1041let PPC970_Unit = 3 in { // FPU Operations. 1042// These are artificially split into two different forms, for 4/8 byte FP. 1043def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1044 "fabs $frD, $frB", FPGeneral, 1045 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1046def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1047 "fabs $frD, $frB", FPGeneral, 1048 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1049def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1050 "fnabs $frD, $frB", FPGeneral, 1051 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1052def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1053 "fnabs $frD, $frB", FPGeneral, 1054 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1055def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1056 "fneg $frD, $frB", FPGeneral, 1057 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1058def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1059 "fneg $frD, $frB", FPGeneral, 1060 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1061} 1062 1063 1064// XL-Form instructions. condition register logical ops. 1065// 1066def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1067 "mcrf $BF, $BFA", BrMCR>, 1068 PPC970_DGroup_First, PPC970_Unit_CRU; 1069 1070def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1071 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1072 "creqv $CRD, $CRA, $CRB", BrCR, 1073 []>; 1074 1075def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1076 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1077 "cror $CRD, $CRA, $CRB", BrCR, 1078 []>; 1079 1080def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1081 "creqv $dst, $dst, $dst", BrCR, 1082 []>; 1083 1084// XFX-Form instructions. Instructions that deal with SPRs. 1085// 1086let Uses = [CTR] in { 1087def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1088 "mfctr $rT", SprMFSPR>, 1089 PPC970_DGroup_First, PPC970_Unit_FXU; 1090} 1091let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1092def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1093 "mtctr $rS", SprMTSPR>, 1094 PPC970_DGroup_First, PPC970_Unit_FXU; 1095} 1096 1097let Defs = [LR] in { 1098def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1099 "mtlr $rS", SprMTSPR>, 1100 PPC970_DGroup_First, PPC970_Unit_FXU; 1101} 1102let Uses = [LR] in { 1103def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1104 "mflr $rT", SprMFSPR>, 1105 PPC970_DGroup_First, PPC970_Unit_FXU; 1106} 1107 1108// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1109// a GPR on the PPC970. As such, copies in and out have the same performance 1110// characteristics as an OR instruction. 1111def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1112 "mtspr 256, $rS", IntGeneral>, 1113 PPC970_DGroup_Single, PPC970_Unit_FXU; 1114def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1115 "mfspr $rT, 256", IntGeneral>, 1116 PPC970_DGroup_First, PPC970_Unit_FXU; 1117 1118def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), 1119 "mtcrf $FXM, $rS", BrMCRX>, 1120 PPC970_MicroCode, PPC970_Unit_CRU; 1121// FIXME: this Uses all the CR registers. Marking it as such is 1122// necessary for DeadMachineInstructionElim to do the right thing. 1123// However, marking it also exposes PR 2964, and causes crashes in 1124// the Local RA because it doesn't like this sequence: 1125// vreg = MCRF CR0 1126// MFCR <kill of whatever preg got assigned to vreg> 1127// For now DeadMachineInstructionElim is turned off, so don't do the marking. 1128def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>, 1129 PPC970_MicroCode, PPC970_Unit_CRU; 1130def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1131 "mfcr $rT, $FXM", SprMFCR>, 1132 PPC970_DGroup_First, PPC970_Unit_CRU; 1133 1134// Instructions to manipulate FPSCR. Only long double handling uses these. 1135// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1136 1137let Uses = [RM], Defs = [RM] in { 1138 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1139 "mtfsb0 $FM", IntMTFSB0, 1140 [(PPCmtfsb0 (i32 imm:$FM))]>, 1141 PPC970_DGroup_Single, PPC970_Unit_FPU; 1142 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1143 "mtfsb1 $FM", IntMTFSB0, 1144 [(PPCmtfsb1 (i32 imm:$FM))]>, 1145 PPC970_DGroup_Single, PPC970_Unit_FPU; 1146 // MTFSF does not actually produce an FP result. We pretend it copies 1147 // input reg B to the output. If we didn't do this it would look like the 1148 // instruction had no outputs (because we aren't modelling the FPSCR) and 1149 // it would be deleted. 1150 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1151 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1152 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1153 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1154 F8RC:$rT, F8RC:$FRB))]>, 1155 PPC970_DGroup_Single, PPC970_Unit_FPU; 1156} 1157let Uses = [RM] in { 1158 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1159 "mffs $rT", IntMFFS, 1160 [(set F8RC:$rT, (PPCmffs))]>, 1161 PPC970_DGroup_Single, PPC970_Unit_FPU; 1162 def FADDrtz: AForm_2<63, 21, 1163 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1164 "fadd $FRT, $FRA, $FRB", FPGeneral, 1165 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1166 PPC970_DGroup_Single, PPC970_Unit_FPU; 1167} 1168 1169 1170let PPC970_Unit = 1 in { // FXU Operations. 1171 1172// XO-Form instructions. Arithmetic instructions that can set overflow bit 1173// 1174def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1175 "add $rT, $rA, $rB", IntGeneral, 1176 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1177let Defs = [CARRY] in { 1178def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1179 "addc $rT, $rA, $rB", IntGeneral, 1180 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1181 PPC970_DGroup_Cracked; 1182} 1183def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1184 "divw $rT, $rA, $rB", IntDivW, 1185 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1186 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1187def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1188 "divwu $rT, $rA, $rB", IntDivW, 1189 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1190 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1191def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1192 "mulhw $rT, $rA, $rB", IntMulHW, 1193 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1194def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1195 "mulhwu $rT, $rA, $rB", IntMulHWU, 1196 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1197def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1198 "mullw $rT, $rA, $rB", IntMulHW, 1199 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1200def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1201 "subf $rT, $rA, $rB", IntGeneral, 1202 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1203let Defs = [CARRY] in { 1204def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1205 "subfc $rT, $rA, $rB", IntGeneral, 1206 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1207 PPC970_DGroup_Cracked; 1208} 1209def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1210 "neg $rT, $rA", IntGeneral, 1211 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1212let Uses = [CARRY], Defs = [CARRY] in { 1213def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1214 "adde $rT, $rA, $rB", IntGeneral, 1215 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1216def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1217 "addme $rT, $rA", IntGeneral, 1218 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1219def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1220 "addze $rT, $rA", IntGeneral, 1221 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1222def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1223 "subfe $rT, $rA, $rB", IntGeneral, 1224 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1225def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1226 "subfme $rT, $rA", IntGeneral, 1227 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1228def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1229 "subfze $rT, $rA", IntGeneral, 1230 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1231} 1232} 1233 1234// A-Form instructions. Most of the instructions executed in the FPU are of 1235// this type. 1236// 1237let PPC970_Unit = 3 in { // FPU Operations. 1238let Uses = [RM] in { 1239 def FMADD : AForm_1<63, 29, 1240 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1241 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1242 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1243 F8RC:$FRB))]>, 1244 Requires<[FPContractions]>; 1245 def FMADDS : AForm_1<59, 29, 1246 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1247 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1248 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1249 F4RC:$FRB))]>, 1250 Requires<[FPContractions]>; 1251 def FMSUB : AForm_1<63, 28, 1252 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1253 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1254 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1255 F8RC:$FRB))]>, 1256 Requires<[FPContractions]>; 1257 def FMSUBS : AForm_1<59, 28, 1258 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1259 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1260 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1261 F4RC:$FRB))]>, 1262 Requires<[FPContractions]>; 1263 def FNMADD : AForm_1<63, 31, 1264 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1265 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1266 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1267 F8RC:$FRB)))]>, 1268 Requires<[FPContractions]>; 1269 def FNMADDS : AForm_1<59, 31, 1270 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1271 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1272 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1273 F4RC:$FRB)))]>, 1274 Requires<[FPContractions]>; 1275 def FNMSUB : AForm_1<63, 30, 1276 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1277 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1278 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1279 F8RC:$FRB)))]>, 1280 Requires<[FPContractions]>; 1281 def FNMSUBS : AForm_1<59, 30, 1282 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1283 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1284 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1285 F4RC:$FRB)))]>, 1286 Requires<[FPContractions]>; 1287} 1288// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1289// having 4 of these, force the comparison to always be an 8-byte double (code 1290// should use an FMRSD if the input comparison value really wants to be a float) 1291// and 4/8 byte forms for the result and operand type.. 1292def FSELD : AForm_1<63, 23, 1293 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1294 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1295 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1296def FSELS : AForm_1<63, 23, 1297 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1298 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1299 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1300let Uses = [RM] in { 1301 def FADD : AForm_2<63, 21, 1302 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1303 "fadd $FRT, $FRA, $FRB", FPGeneral, 1304 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1305 def FADDS : AForm_2<59, 21, 1306 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1307 "fadds $FRT, $FRA, $FRB", FPGeneral, 1308 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1309 def FDIV : AForm_2<63, 18, 1310 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1311 "fdiv $FRT, $FRA, $FRB", FPDivD, 1312 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1313 def FDIVS : AForm_2<59, 18, 1314 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1315 "fdivs $FRT, $FRA, $FRB", FPDivS, 1316 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1317 def FMUL : AForm_3<63, 25, 1318 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1319 "fmul $FRT, $FRA, $FRB", FPFused, 1320 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1321 def FMULS : AForm_3<59, 25, 1322 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1323 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1324 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1325 def FSUB : AForm_2<63, 20, 1326 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1327 "fsub $FRT, $FRA, $FRB", FPGeneral, 1328 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1329 def FSUBS : AForm_2<59, 20, 1330 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1331 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1332 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1333 } 1334} 1335 1336let PPC970_Unit = 1 in { // FXU Operations. 1337// M-Form instructions. rotate and mask instructions. 1338// 1339let isCommutable = 1 in { 1340// RLWIMI can be commuted if the rotate amount is zero. 1341def RLWIMI : MForm_2<20, 1342 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1343 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1344 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1345 NoEncode<"$rSi">; 1346} 1347def RLWINM : MForm_2<21, 1348 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1349 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1350 []>; 1351def RLWINMo : MForm_2<21, 1352 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1353 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1354 []>, isDOT, PPC970_DGroup_Cracked; 1355def RLWNM : MForm_2<23, 1356 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1357 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1358 []>; 1359} 1360 1361 1362//===----------------------------------------------------------------------===// 1363// PowerPC Instruction Patterns 1364// 1365 1366// Arbitrary immediate support. Implement in terms of LIS/ORI. 1367def : Pat<(i32 imm:$imm), 1368 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1369 1370// Implement the 'not' operation with the NOR instruction. 1371def NOT : Pat<(not GPRC:$in), 1372 (NOR GPRC:$in, GPRC:$in)>; 1373 1374// ADD an arbitrary immediate. 1375def : Pat<(add GPRC:$in, imm:$imm), 1376 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1377// OR an arbitrary immediate. 1378def : Pat<(or GPRC:$in, imm:$imm), 1379 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1380// XOR an arbitrary immediate. 1381def : Pat<(xor GPRC:$in, imm:$imm), 1382 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1383// SUBFIC 1384def : Pat<(sub immSExt16:$imm, GPRC:$in), 1385 (SUBFIC GPRC:$in, imm:$imm)>; 1386 1387// SHL/SRL 1388def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1389 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1390def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1391 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1392 1393// ROTL 1394def : Pat<(rotl GPRC:$in, GPRC:$sh), 1395 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1396def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1397 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1398 1399// RLWNM 1400def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1401 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1402 1403// Calls 1404def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1405 (BL_Darwin tglobaladdr:$dst)>; 1406def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1407 (BL_Darwin texternalsym:$dst)>; 1408def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1409 (BL_SVR4 tglobaladdr:$dst)>; 1410def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1411 (BL_SVR4 texternalsym:$dst)>; 1412 1413 1414def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1415 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1416 1417def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1418 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1419 1420def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1421 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1422 1423 1424 1425// Hi and Lo for Darwin Global Addresses. 1426def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1427def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1428def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1429def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1430def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1431def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1432def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1433def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1434def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1435 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1436def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1437 (ADDIS GPRC:$in, tconstpool:$g)>; 1438def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1439 (ADDIS GPRC:$in, tjumptable:$g)>; 1440def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1441 (ADDIS GPRC:$in, tblockaddress:$g)>; 1442 1443// Fused negative multiply subtract, alternate pattern 1444def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1445 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1446 Requires<[FPContractions]>; 1447def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1448 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1449 Requires<[FPContractions]>; 1450 1451// Standard shifts. These are represented separately from the real shifts above 1452// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1453// amounts. 1454def : Pat<(sra GPRC:$rS, GPRC:$rB), 1455 (SRAW GPRC:$rS, GPRC:$rB)>; 1456def : Pat<(srl GPRC:$rS, GPRC:$rB), 1457 (SRW GPRC:$rS, GPRC:$rB)>; 1458def : Pat<(shl GPRC:$rS, GPRC:$rB), 1459 (SLW GPRC:$rS, GPRC:$rB)>; 1460 1461def : Pat<(zextloadi1 iaddr:$src), 1462 (LBZ iaddr:$src)>; 1463def : Pat<(zextloadi1 xaddr:$src), 1464 (LBZX xaddr:$src)>; 1465def : Pat<(extloadi1 iaddr:$src), 1466 (LBZ iaddr:$src)>; 1467def : Pat<(extloadi1 xaddr:$src), 1468 (LBZX xaddr:$src)>; 1469def : Pat<(extloadi8 iaddr:$src), 1470 (LBZ iaddr:$src)>; 1471def : Pat<(extloadi8 xaddr:$src), 1472 (LBZX xaddr:$src)>; 1473def : Pat<(extloadi16 iaddr:$src), 1474 (LHZ iaddr:$src)>; 1475def : Pat<(extloadi16 xaddr:$src), 1476 (LHZX xaddr:$src)>; 1477def : Pat<(extloadf32 iaddr:$src), 1478 (FMRSD (LFS iaddr:$src))>; 1479def : Pat<(extloadf32 xaddr:$src), 1480 (FMRSD (LFSX xaddr:$src))>; 1481 1482// Memory barriers 1483def : Pat<(membarrier (i32 imm /*ll*/), 1484 (i32 imm /*ls*/), 1485 (i32 imm /*sl*/), 1486 (i32 imm /*ss*/), 1487 (i32 imm /*device*/)), 1488 (SYNC)>; 1489 1490include "PPCInstrAltivec.td" 1491include "PPCInstr64Bit.td" 1492