PPCInstrInfo.td revision 195340
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 3, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 4, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56//===----------------------------------------------------------------------===// 57// PowerPC specific DAG Nodes. 58// 59 60def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 61def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 62def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 63def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 64 [SDNPHasChain, SDNPMayStore]>; 65 66// This sequence is used for long double->int conversions. It changes the 67// bits in the FPSCR which is not modelled. 68def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 69 [SDNPOutFlag]>; 70def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 71 [SDNPInFlag, SDNPOutFlag]>; 72def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInFlag, SDNPOutFlag]>; 74def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 75 [SDNPInFlag, SDNPOutFlag]>; 76def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 77 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 78 SDTCisVT<3, f64>]>, 79 [SDNPInFlag]>; 80 81def PPCfsel : SDNode<"PPCISD::FSEL", 82 // Type constraint for fsel. 83 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 84 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 85 86def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 87def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 88def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 89def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 90 91def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 92 93// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 94// amounts. These nodes are generated by the multi-precision shift code. 95def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 96def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 97def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 98 99def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 100def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 101 [SDNPHasChain, SDNPMayStore]>; 102 103// These are target-independent nodes, but have target-specific formats. 104def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 105 [SDNPHasChain, SDNPOutFlag]>; 106def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 107 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 108 109def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 110def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 111 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 112def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 114def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 115 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 116def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 118 119def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 120 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 121 122def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 123 [SDNPHasChain, SDNPOptInFlag]>; 124 125def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 126 [SDNPHasChain, SDNPOptInFlag]>; 127 128def PPCtailcall : SDNode<"PPCISD::TAILCALL", SDT_PPCCall, 129 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; 130 131def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 132def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 133 134def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 135 [SDNPHasChain, SDNPOptInFlag]>; 136 137def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 138 [SDNPHasChain, SDNPMayLoad]>; 139def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 140 [SDNPHasChain, SDNPMayStore]>; 141 142// Instructions to support atomic operations 143def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 144 [SDNPHasChain, SDNPMayLoad]>; 145def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 146 [SDNPHasChain, SDNPMayStore]>; 147 148// Instructions to support dynamic alloca. 149def SDTDynOp : SDTypeProfile<1, 2, []>; 150def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 151 152//===----------------------------------------------------------------------===// 153// PowerPC specific transformation functions and pattern fragments. 154// 155 156def SHL32 : SDNodeXForm<imm, [{ 157 // Transformation function: 31 - imm 158 return getI32Imm(31 - N->getZExtValue()); 159}]>; 160 161def SRL32 : SDNodeXForm<imm, [{ 162 // Transformation function: 32 - imm 163 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 164}]>; 165 166def LO16 : SDNodeXForm<imm, [{ 167 // Transformation function: get the low 16 bits. 168 return getI32Imm((unsigned short)N->getZExtValue()); 169}]>; 170 171def HI16 : SDNodeXForm<imm, [{ 172 // Transformation function: shift the immediate value down into the low bits. 173 return getI32Imm((unsigned)N->getZExtValue() >> 16); 174}]>; 175 176def HA16 : SDNodeXForm<imm, [{ 177 // Transformation function: shift the immediate value down into the low bits. 178 signed int Val = N->getZExtValue(); 179 return getI32Imm((Val - (signed short)Val) >> 16); 180}]>; 181def MB : SDNodeXForm<imm, [{ 182 // Transformation function: get the start bit of a mask 183 unsigned mb = 0, me; 184 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 185 return getI32Imm(mb); 186}]>; 187 188def ME : SDNodeXForm<imm, [{ 189 // Transformation function: get the end bit of a mask 190 unsigned mb, me = 0; 191 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 192 return getI32Imm(me); 193}]>; 194def maskimm32 : PatLeaf<(imm), [{ 195 // maskImm predicate - True if immediate is a run of ones. 196 unsigned mb, me; 197 if (N->getValueType(0) == MVT::i32) 198 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 199 else 200 return false; 201}]>; 202 203def immSExt16 : PatLeaf<(imm), [{ 204 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 205 // field. Used by instructions like 'addi'. 206 if (N->getValueType(0) == MVT::i32) 207 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 208 else 209 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 210}]>; 211def immZExt16 : PatLeaf<(imm), [{ 212 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 213 // field. Used by instructions like 'ori'. 214 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 215}], LO16>; 216 217// imm16Shifted* - These match immediates where the low 16-bits are zero. There 218// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 219// identical in 32-bit mode, but in 64-bit mode, they return true if the 220// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 221// clear). 222def imm16ShiftedZExt : PatLeaf<(imm), [{ 223 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 224 // immediate are set. Used by instructions like 'xoris'. 225 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 226}], HI16>; 227 228def imm16ShiftedSExt : PatLeaf<(imm), [{ 229 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 230 // immediate are set. Used by instructions like 'addis'. Identical to 231 // imm16ShiftedZExt in 32-bit mode. 232 if (N->getZExtValue() & 0xFFFF) return false; 233 if (N->getValueType(0) == MVT::i32) 234 return true; 235 // For 64-bit, make sure it is sext right. 236 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 237}], HI16>; 238 239 240//===----------------------------------------------------------------------===// 241// PowerPC Flag Definitions. 242 243class isPPC64 { bit PPC64 = 1; } 244class isDOT { 245 list<Register> Defs = [CR0]; 246 bit RC = 1; 247} 248 249class RegConstraint<string C> { 250 string Constraints = C; 251} 252class NoEncode<string E> { 253 string DisableEncoding = E; 254} 255 256 257//===----------------------------------------------------------------------===// 258// PowerPC Operand Definitions. 259 260def s5imm : Operand<i32> { 261 let PrintMethod = "printS5ImmOperand"; 262} 263def u5imm : Operand<i32> { 264 let PrintMethod = "printU5ImmOperand"; 265} 266def u6imm : Operand<i32> { 267 let PrintMethod = "printU6ImmOperand"; 268} 269def s16imm : Operand<i32> { 270 let PrintMethod = "printS16ImmOperand"; 271} 272def u16imm : Operand<i32> { 273 let PrintMethod = "printU16ImmOperand"; 274} 275def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 276 let PrintMethod = "printS16X4ImmOperand"; 277} 278def target : Operand<OtherVT> { 279 let PrintMethod = "printBranchOperand"; 280} 281def calltarget : Operand<iPTR> { 282 let PrintMethod = "printCallOperand"; 283} 284def aaddr : Operand<iPTR> { 285 let PrintMethod = "printAbsAddrOperand"; 286} 287def piclabel: Operand<iPTR> { 288 let PrintMethod = "printPICLabel"; 289} 290def symbolHi: Operand<i32> { 291 let PrintMethod = "printSymbolHi"; 292} 293def symbolLo: Operand<i32> { 294 let PrintMethod = "printSymbolLo"; 295} 296def crbitm: Operand<i8> { 297 let PrintMethod = "printcrbitm"; 298} 299// Address operands 300def memri : Operand<iPTR> { 301 let PrintMethod = "printMemRegImm"; 302 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 303} 304def memrr : Operand<iPTR> { 305 let PrintMethod = "printMemRegReg"; 306 let MIOperandInfo = (ops ptr_rc, ptr_rc); 307} 308def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 309 let PrintMethod = "printMemRegImmShifted"; 310 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 311} 312 313// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 314// that doesn't matter. 315def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 316 (ops (i32 20), (i32 zero_reg))> { 317 let PrintMethod = "printPredicateOperand"; 318} 319 320// Define PowerPC specific addressing mode. 321def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 322def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 323def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 324def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 325 326/// This is just the offset part of iaddr, used for preinc. 327def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 328 329//===----------------------------------------------------------------------===// 330// PowerPC Instruction Predicate Definitions. 331def FPContractions : Predicate<"!NoExcessFPPrecision">; 332def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 333def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 334 335 336//===----------------------------------------------------------------------===// 337// PowerPC Instruction Definitions. 338 339// Pseudo-instructions: 340 341let hasCtrlDep = 1 in { 342let Defs = [R1], Uses = [R1] in { 343def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), 344 "${:comment} ADJCALLSTACKDOWN", 345 [(callseq_start timm:$amt)]>; 346def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 347 "${:comment} ADJCALLSTACKUP", 348 [(callseq_end timm:$amt1, timm:$amt2)]>; 349} 350 351def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 352 "UPDATE_VRSAVE $rD, $rS", []>; 353} 354 355let Defs = [R1], Uses = [R1] in 356def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), 357 "${:comment} DYNALLOC $result, $negsize, $fpsi", 358 [(set GPRC:$result, 359 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 360 361// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 362// scheduler into a branch sequence. 363let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 364 PPC970_Single = 1 in { 365 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 366 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 367 []>; 368 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 369 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 370 []>; 371 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 372 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 373 []>; 374 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 375 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 376 []>; 377 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 378 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 379 []>; 380} 381 382// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 383// scavenge a register for it. 384def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), 385 "${:comment} SPILL_CR $cond $F", []>; 386 387let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 388 let isReturn = 1, Uses = [LR, RM] in 389 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 390 "b${p:cc}lr ${p:reg}", BrB, 391 [(retflag)]>; 392 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 393 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 394} 395 396let Defs = [LR] in 397 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 398 PPC970_Unit_BRU; 399 400let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 401 let isBarrier = 1 in { 402 def B : IForm<18, 0, 0, (outs), (ins target:$dst), 403 "b $dst", BrB, 404 [(br bb:$dst)]>; 405 } 406 407 // BCC represents an arbitrary conditional branch on a predicate. 408 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 409 // a two-value operand where a dag node expects two operands. :( 410 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), 411 "b${cond:cc} ${cond:reg}, $dst" 412 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 413} 414 415// Darwin ABI Calls. 416let isCall = 1, PPC970_Unit = 7, 417 // All calls clobber the non-callee saved registers... 418 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 419 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 420 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 421 LR,CTR, 422 CR0,CR1,CR5,CR6,CR7, 423 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ, 424 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in { 425 // Convenient aliases for call instructions 426 let Uses = [RM] in { 427 def BL_Darwin : IForm<18, 0, 1, 428 (outs), (ins calltarget:$func, variable_ops), 429 "bl $func", BrB, []>; // See Pat patterns below. 430 def BLA_Darwin : IForm<18, 1, 1, 431 (outs), (ins aaddr:$func, variable_ops), 432 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 433 } 434 let Uses = [CTR, RM] in { 435 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 436 (outs), (ins variable_ops), 437 "bctrl", BrB, 438 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 439 } 440} 441 442// SVR4 ABI Calls. 443let isCall = 1, PPC970_Unit = 7, 444 // All calls clobber the non-callee saved registers... 445 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 446 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 447 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 448 LR,CTR, 449 CR0,CR1,CR5,CR6,CR7, 450 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ, 451 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in { 452 // Convenient aliases for call instructions 453 let Uses = [RM] in { 454 def BL_SVR4 : IForm<18, 0, 1, 455 (outs), (ins calltarget:$func, variable_ops), 456 "bl $func", BrB, []>; // See Pat patterns below. 457 def BLA_SVR4 : IForm<18, 1, 1, 458 (outs), (ins aaddr:$func, variable_ops), 459 "bla $func", BrB, 460 [(PPCcall_SVR4 (i32 imm:$func))]>; 461 } 462 let Uses = [CTR, RM] in { 463 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 464 (outs), (ins variable_ops), 465 "bctrl", BrB, 466 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 467 } 468} 469 470 471let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 472def TCRETURNdi :Pseudo< (outs), 473 (ins calltarget:$dst, i32imm:$offset, variable_ops), 474 "#TC_RETURNd $dst $offset", 475 []>; 476 477 478let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 479def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 480 "#TC_RETURNa $func $offset", 481 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 482 483let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 484def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops), 485 "#TC_RETURNr $dst $offset", 486 []>; 487 488 489let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 490 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 491def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 492 Requires<[In32BitMode]>; 493 494 495 496let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 497 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 498def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 499 "b $dst", BrB, 500 []>; 501 502 503let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 504 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 505def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 506 "ba $dst", BrB, 507 []>; 508 509 510// DCB* instructions. 511def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 512 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 513 PPC970_DGroup_Single; 514def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 515 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 516 PPC970_DGroup_Single; 517def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 518 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 519 PPC970_DGroup_Single; 520def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 521 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 522 PPC970_DGroup_Single; 523def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 524 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 525 PPC970_DGroup_Single; 526def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 527 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 528 PPC970_DGroup_Single; 529def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 530 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 531 PPC970_DGroup_Single; 532def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 533 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 534 PPC970_DGroup_Single; 535 536// Atomic operations 537let usesCustomDAGSchedInserter = 1 in { 538 let Uses = [CR0] in { 539 def ATOMIC_LOAD_ADD_I8 : Pseudo< 540 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 541 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!", 542 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 543 def ATOMIC_LOAD_SUB_I8 : Pseudo< 544 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 545 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!", 546 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 547 def ATOMIC_LOAD_AND_I8 : Pseudo< 548 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 549 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!", 550 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 551 def ATOMIC_LOAD_OR_I8 : Pseudo< 552 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 553 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!", 554 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 555 def ATOMIC_LOAD_XOR_I8 : Pseudo< 556 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 557 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!", 558 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 559 def ATOMIC_LOAD_NAND_I8 : Pseudo< 560 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 561 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!", 562 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 563 def ATOMIC_LOAD_ADD_I16 : Pseudo< 564 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 565 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!", 566 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 567 def ATOMIC_LOAD_SUB_I16 : Pseudo< 568 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 569 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!", 570 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 571 def ATOMIC_LOAD_AND_I16 : Pseudo< 572 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 573 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!", 574 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 575 def ATOMIC_LOAD_OR_I16 : Pseudo< 576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 577 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!", 578 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 579 def ATOMIC_LOAD_XOR_I16 : Pseudo< 580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 581 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!", 582 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 583 def ATOMIC_LOAD_NAND_I16 : Pseudo< 584 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 585 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!", 586 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 587 def ATOMIC_LOAD_ADD_I32 : Pseudo< 588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 589 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!", 590 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 591 def ATOMIC_LOAD_SUB_I32 : Pseudo< 592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 593 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!", 594 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 595 def ATOMIC_LOAD_AND_I32 : Pseudo< 596 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 597 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!", 598 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 599 def ATOMIC_LOAD_OR_I32 : Pseudo< 600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 601 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!", 602 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 603 def ATOMIC_LOAD_XOR_I32 : Pseudo< 604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 605 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!", 606 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 607 def ATOMIC_LOAD_NAND_I32 : Pseudo< 608 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 609 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!", 610 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 611 612 def ATOMIC_CMP_SWAP_I8 : Pseudo< 613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 614 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!", 615 [(set GPRC:$dst, 616 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 617 def ATOMIC_CMP_SWAP_I16 : Pseudo< 618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 619 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!", 620 [(set GPRC:$dst, 621 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 622 def ATOMIC_CMP_SWAP_I32 : Pseudo< 623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 624 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!", 625 [(set GPRC:$dst, 626 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 627 628 def ATOMIC_SWAP_I8 : Pseudo< 629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 630 "${:comment} ATOMIC_SWAP_I8 PSEUDO!", 631 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 632 def ATOMIC_SWAP_I16 : Pseudo< 633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 634 "${:comment} ATOMIC_SWAP_I16 PSEUDO!", 635 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 636 def ATOMIC_SWAP_I32 : Pseudo< 637 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 638 "${:comment} ATOMIC_SWAP_I32 PSEUDO!", 639 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 640 } 641} 642 643// Instructions to support atomic operations 644def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 645 "lwarx $rD, $src", LdStLWARX, 646 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 647 648let Defs = [CR0] in 649def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 650 "stwcx. $rS, $dst", LdStSTWCX, 651 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 652 isDOT; 653 654let isBarrier = 1, hasCtrlDep = 1 in 655def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>; 656 657//===----------------------------------------------------------------------===// 658// PPC32 Load Instructions. 659// 660 661// Unindexed (r+i) Loads. 662let canFoldAsLoad = 1, PPC970_Unit = 2 in { 663def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 664 "lbz $rD, $src", LdStGeneral, 665 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 666def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 667 "lha $rD, $src", LdStLHA, 668 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 669 PPC970_DGroup_Cracked; 670def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 671 "lhz $rD, $src", LdStGeneral, 672 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 673def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 674 "lwz $rD, $src", LdStGeneral, 675 [(set GPRC:$rD, (load iaddr:$src))]>; 676 677def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 678 "lfs $rD, $src", LdStLFDU, 679 [(set F4RC:$rD, (load iaddr:$src))]>; 680def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 681 "lfd $rD, $src", LdStLFD, 682 [(set F8RC:$rD, (load iaddr:$src))]>; 683 684 685// Unindexed (r+i) Loads with Update (preinc). 686let mayLoad = 1 in { 687def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 688 "lbzu $rD, $addr", LdStGeneral, 689 []>, RegConstraint<"$addr.reg = $ea_result">, 690 NoEncode<"$ea_result">; 691 692def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 693 "lhau $rD, $addr", LdStGeneral, 694 []>, RegConstraint<"$addr.reg = $ea_result">, 695 NoEncode<"$ea_result">; 696 697def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 698 "lhzu $rD, $addr", LdStGeneral, 699 []>, RegConstraint<"$addr.reg = $ea_result">, 700 NoEncode<"$ea_result">; 701 702def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 703 "lwzu $rD, $addr", LdStGeneral, 704 []>, RegConstraint<"$addr.reg = $ea_result">, 705 NoEncode<"$ea_result">; 706 707def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 708 "lfs $rD, $addr", LdStLFDU, 709 []>, RegConstraint<"$addr.reg = $ea_result">, 710 NoEncode<"$ea_result">; 711 712def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 713 "lfd $rD, $addr", LdStLFD, 714 []>, RegConstraint<"$addr.reg = $ea_result">, 715 NoEncode<"$ea_result">; 716} 717} 718 719// Indexed (r+r) Loads. 720// 721let canFoldAsLoad = 1, PPC970_Unit = 2 in { 722def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 723 "lbzx $rD, $src", LdStGeneral, 724 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 725def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 726 "lhax $rD, $src", LdStLHA, 727 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 728 PPC970_DGroup_Cracked; 729def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 730 "lhzx $rD, $src", LdStGeneral, 731 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 732def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 733 "lwzx $rD, $src", LdStGeneral, 734 [(set GPRC:$rD, (load xaddr:$src))]>; 735 736 737def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 738 "lhbrx $rD, $src", LdStGeneral, 739 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>; 740def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 741 "lwbrx $rD, $src", LdStGeneral, 742 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>; 743 744def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 745 "lfsx $frD, $src", LdStLFDU, 746 [(set F4RC:$frD, (load xaddr:$src))]>; 747def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 748 "lfdx $frD, $src", LdStLFDU, 749 [(set F8RC:$frD, (load xaddr:$src))]>; 750} 751 752//===----------------------------------------------------------------------===// 753// PPC32 Store Instructions. 754// 755 756// Unindexed (r+i) Stores. 757let PPC970_Unit = 2 in { 758def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 759 "stb $rS, $src", LdStGeneral, 760 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 761def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 762 "sth $rS, $src", LdStGeneral, 763 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 764def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 765 "stw $rS, $src", LdStGeneral, 766 [(store GPRC:$rS, iaddr:$src)]>; 767def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 768 "stfs $rS, $dst", LdStUX, 769 [(store F4RC:$rS, iaddr:$dst)]>; 770def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 771 "stfd $rS, $dst", LdStUX, 772 [(store F8RC:$rS, iaddr:$dst)]>; 773} 774 775// Unindexed (r+i) Stores with Update (preinc). 776let PPC970_Unit = 2 in { 777def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 778 symbolLo:$ptroff, ptr_rc:$ptrreg), 779 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 780 [(set ptr_rc:$ea_res, 781 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 782 iaddroff:$ptroff))]>, 783 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 784def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 785 symbolLo:$ptroff, ptr_rc:$ptrreg), 786 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 787 [(set ptr_rc:$ea_res, 788 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 789 iaddroff:$ptroff))]>, 790 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 791def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 792 symbolLo:$ptroff, ptr_rc:$ptrreg), 793 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 794 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 795 iaddroff:$ptroff))]>, 796 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 797def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 798 symbolLo:$ptroff, ptr_rc:$ptrreg), 799 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 800 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 801 iaddroff:$ptroff))]>, 802 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 803def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 804 symbolLo:$ptroff, ptr_rc:$ptrreg), 805 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 806 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 807 iaddroff:$ptroff))]>, 808 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 809} 810 811 812// Indexed (r+r) Stores. 813// 814let PPC970_Unit = 2 in { 815def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 816 "stbx $rS, $dst", LdStGeneral, 817 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 818 PPC970_DGroup_Cracked; 819def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 820 "sthx $rS, $dst", LdStGeneral, 821 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 822 PPC970_DGroup_Cracked; 823def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 824 "stwx $rS, $dst", LdStGeneral, 825 [(store GPRC:$rS, xaddr:$dst)]>, 826 PPC970_DGroup_Cracked; 827 828let mayStore = 1 in { 829def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), 830 "stwux $rS, $rA, $rB", LdStGeneral, 831 []>; 832} 833def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 834 "sthbrx $rS, $dst", LdStGeneral, 835 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, 836 PPC970_DGroup_Cracked; 837def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 838 "stwbrx $rS, $dst", LdStGeneral, 839 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>, 840 PPC970_DGroup_Cracked; 841 842def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 843 "stfiwx $frS, $dst", LdStUX, 844 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 845 846def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 847 "stfsx $frS, $dst", LdStUX, 848 [(store F4RC:$frS, xaddr:$dst)]>; 849def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 850 "stfdx $frS, $dst", LdStUX, 851 [(store F8RC:$frS, xaddr:$dst)]>; 852} 853 854let isBarrier = 1 in 855def SYNC : XForm_24_sync<31, 598, (outs), (ins), 856 "sync", LdStSync, 857 [(int_ppc_sync)]>; 858 859//===----------------------------------------------------------------------===// 860// PPC32 Arithmetic Instructions. 861// 862 863let PPC970_Unit = 1 in { // FXU Operations. 864def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 865 "addi $rD, $rA, $imm", IntGeneral, 866 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 867def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 868 "addic $rD, $rA, $imm", IntGeneral, 869 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 870 PPC970_DGroup_Cracked; 871def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 872 "addic. $rD, $rA, $imm", IntGeneral, 873 []>; 874def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 875 "addis $rD, $rA, $imm", IntGeneral, 876 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 877def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 878 "la $rD, $sym($rA)", IntGeneral, 879 [(set GPRC:$rD, (add GPRC:$rA, 880 (PPClo tglobaladdr:$sym, 0)))]>; 881def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 882 "mulli $rD, $rA, $imm", IntMulLI, 883 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 884def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 885 "subfic $rD, $rA, $imm", IntGeneral, 886 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 887 888let isReMaterializable = 1 in { 889 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 890 "li $rD, $imm", IntGeneral, 891 [(set GPRC:$rD, immSExt16:$imm)]>; 892 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 893 "lis $rD, $imm", IntGeneral, 894 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 895} 896} 897 898let PPC970_Unit = 1 in { // FXU Operations. 899def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 900 "andi. $dst, $src1, $src2", IntGeneral, 901 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 902 isDOT; 903def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 904 "andis. $dst, $src1, $src2", IntGeneral, 905 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 906 isDOT; 907def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 908 "ori $dst, $src1, $src2", IntGeneral, 909 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 910def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 911 "oris $dst, $src1, $src2", IntGeneral, 912 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 913def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 914 "xori $dst, $src1, $src2", IntGeneral, 915 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 916def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 917 "xoris $dst, $src1, $src2", IntGeneral, 918 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 919def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, 920 []>; 921def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 922 "cmpwi $crD, $rA, $imm", IntCompare>; 923def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 924 "cmplwi $dst, $src1, $src2", IntCompare>; 925} 926 927 928let PPC970_Unit = 1 in { // FXU Operations. 929def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 930 "nand $rA, $rS, $rB", IntGeneral, 931 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 932def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 933 "and $rA, $rS, $rB", IntGeneral, 934 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 935def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 936 "andc $rA, $rS, $rB", IntGeneral, 937 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 938def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 939 "or $rA, $rS, $rB", IntGeneral, 940 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 941def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 942 "nor $rA, $rS, $rB", IntGeneral, 943 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 944def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 945 "orc $rA, $rS, $rB", IntGeneral, 946 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 947def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 948 "eqv $rA, $rS, $rB", IntGeneral, 949 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 950def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 951 "xor $rA, $rS, $rB", IntGeneral, 952 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 953def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 954 "slw $rA, $rS, $rB", IntGeneral, 955 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 956def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 957 "srw $rA, $rS, $rB", IntGeneral, 958 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 959def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 960 "sraw $rA, $rS, $rB", IntShift, 961 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 962} 963 964let PPC970_Unit = 1 in { // FXU Operations. 965def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 966 "srawi $rA, $rS, $SH", IntShift, 967 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 968def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 969 "cntlzw $rA, $rS", IntGeneral, 970 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 971def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 972 "extsb $rA, $rS", IntGeneral, 973 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 974def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 975 "extsh $rA, $rS", IntGeneral, 976 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 977 978def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 979 "cmpw $crD, $rA, $rB", IntCompare>; 980def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 981 "cmplw $crD, $rA, $rB", IntCompare>; 982} 983let PPC970_Unit = 3 in { // FPU Operations. 984//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 985// "fcmpo $crD, $fA, $fB", FPCompare>; 986def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 987 "fcmpu $crD, $fA, $fB", FPCompare>; 988def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 989 "fcmpu $crD, $fA, $fB", FPCompare>; 990 991let Uses = [RM] in { 992 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 993 "fctiwz $frD, $frB", FPGeneral, 994 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 995 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 996 "frsp $frD, $frB", FPGeneral, 997 [(set F4RC:$frD, (fround F8RC:$frB))]>; 998 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 999 "fsqrt $frD, $frB", FPSqrt, 1000 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1001 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1002 "fsqrts $frD, $frB", FPSqrt, 1003 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1004 } 1005} 1006 1007/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 1008/// 1009/// Note that these are defined as pseudo-ops on the PPC970 because they are 1010/// often coalesced away and we don't want the dispatch group builder to think 1011/// that they will fill slots (which could cause the load of a LSU reject to 1012/// sneak into a d-group with a store). 1013def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1014 "fmr $frD, $frB", FPGeneral, 1015 []>, // (set F4RC:$frD, F4RC:$frB) 1016 PPC970_Unit_Pseudo; 1017def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB), 1018 "fmr $frD, $frB", FPGeneral, 1019 []>, // (set F8RC:$frD, F8RC:$frB) 1020 PPC970_Unit_Pseudo; 1021def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), 1022 "fmr $frD, $frB", FPGeneral, 1023 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 1024 PPC970_Unit_Pseudo; 1025 1026let PPC970_Unit = 3 in { // FPU Operations. 1027// These are artificially split into two different forms, for 4/8 byte FP. 1028def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1029 "fabs $frD, $frB", FPGeneral, 1030 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1031def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1032 "fabs $frD, $frB", FPGeneral, 1033 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1034def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1035 "fnabs $frD, $frB", FPGeneral, 1036 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1037def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1038 "fnabs $frD, $frB", FPGeneral, 1039 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1040def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1041 "fneg $frD, $frB", FPGeneral, 1042 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1043def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1044 "fneg $frD, $frB", FPGeneral, 1045 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1046} 1047 1048 1049// XL-Form instructions. condition register logical ops. 1050// 1051def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1052 "mcrf $BF, $BFA", BrMCR>, 1053 PPC970_DGroup_First, PPC970_Unit_CRU; 1054 1055def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1056 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1057 "creqv $CRD, $CRA, $CRB", BrCR, 1058 []>; 1059 1060def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1061 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1062 "cror $CRD, $CRA, $CRB", BrCR, 1063 []>; 1064 1065def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1066 "creqv $dst, $dst, $dst", BrCR, 1067 []>; 1068 1069// XFX-Form instructions. Instructions that deal with SPRs. 1070// 1071let Uses = [CTR] in { 1072def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1073 "mfctr $rT", SprMFSPR>, 1074 PPC970_DGroup_First, PPC970_Unit_FXU; 1075} 1076let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1077def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1078 "mtctr $rS", SprMTSPR>, 1079 PPC970_DGroup_First, PPC970_Unit_FXU; 1080} 1081 1082let Defs = [LR] in { 1083def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1084 "mtlr $rS", SprMTSPR>, 1085 PPC970_DGroup_First, PPC970_Unit_FXU; 1086} 1087let Uses = [LR] in { 1088def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1089 "mflr $rT", SprMFSPR>, 1090 PPC970_DGroup_First, PPC970_Unit_FXU; 1091} 1092 1093// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1094// a GPR on the PPC970. As such, copies in and out have the same performance 1095// characteristics as an OR instruction. 1096def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1097 "mtspr 256, $rS", IntGeneral>, 1098 PPC970_DGroup_Single, PPC970_Unit_FXU; 1099def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1100 "mfspr $rT, 256", IntGeneral>, 1101 PPC970_DGroup_First, PPC970_Unit_FXU; 1102 1103def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), 1104 "mtcrf $FXM, $rS", BrMCRX>, 1105 PPC970_MicroCode, PPC970_Unit_CRU; 1106// FIXME: this Uses all the CR registers. Marking it as such is 1107// necessary for DeadMachineInstructionElim to do the right thing. 1108// However, marking it also exposes PR 2964, and causes crashes in 1109// the Local RA because it doesn't like this sequence: 1110// vreg = MCRF CR0 1111// MFCR <kill of whatever preg got assigned to vreg> 1112// For now DeadMachineInstructionElim is turned off, so don't do the marking. 1113def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>, 1114 PPC970_MicroCode, PPC970_Unit_CRU; 1115def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1116 "mfcr $rT, $FXM", SprMFCR>, 1117 PPC970_DGroup_First, PPC970_Unit_CRU; 1118 1119// Instructions to manipulate FPSCR. Only long double handling uses these. 1120// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1121 1122let Uses = [RM], Defs = [RM] in { 1123 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1124 "mtfsb0 $FM", IntMTFSB0, 1125 [(PPCmtfsb0 (i32 imm:$FM))]>, 1126 PPC970_DGroup_Single, PPC970_Unit_FPU; 1127 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1128 "mtfsb1 $FM", IntMTFSB0, 1129 [(PPCmtfsb1 (i32 imm:$FM))]>, 1130 PPC970_DGroup_Single, PPC970_Unit_FPU; 1131 // MTFSF does not actually produce an FP result. We pretend it copies 1132 // input reg B to the output. If we didn't do this it would look like the 1133 // instruction had no outputs (because we aren't modelling the FPSCR) and 1134 // it would be deleted. 1135 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1136 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1137 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1138 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1139 F8RC:$rT, F8RC:$FRB))]>, 1140 PPC970_DGroup_Single, PPC970_Unit_FPU; 1141} 1142let Uses = [RM] in { 1143 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1144 "mffs $rT", IntMFFS, 1145 [(set F8RC:$rT, (PPCmffs))]>, 1146 PPC970_DGroup_Single, PPC970_Unit_FPU; 1147 def FADDrtz: AForm_2<63, 21, 1148 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1149 "fadd $FRT, $FRA, $FRB", FPGeneral, 1150 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1151 PPC970_DGroup_Single, PPC970_Unit_FPU; 1152} 1153 1154 1155let PPC970_Unit = 1 in { // FXU Operations. 1156 1157// XO-Form instructions. Arithmetic instructions that can set overflow bit 1158// 1159def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1160 "add $rT, $rA, $rB", IntGeneral, 1161 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1162def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1163 "addc $rT, $rA, $rB", IntGeneral, 1164 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1165 PPC970_DGroup_Cracked; 1166def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1167 "adde $rT, $rA, $rB", IntGeneral, 1168 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1169def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1170 "divw $rT, $rA, $rB", IntDivW, 1171 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1172 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1173def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1174 "divwu $rT, $rA, $rB", IntDivW, 1175 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1176 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1177def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1178 "mulhw $rT, $rA, $rB", IntMulHW, 1179 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1180def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1181 "mulhwu $rT, $rA, $rB", IntMulHWU, 1182 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1183def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1184 "mullw $rT, $rA, $rB", IntMulHW, 1185 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1186def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1187 "subf $rT, $rA, $rB", IntGeneral, 1188 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1189def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1190 "subfc $rT, $rA, $rB", IntGeneral, 1191 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1192 PPC970_DGroup_Cracked; 1193def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1194 "subfe $rT, $rA, $rB", IntGeneral, 1195 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1196def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1197 "addme $rT, $rA", IntGeneral, 1198 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 1199def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1200 "addze $rT, $rA", IntGeneral, 1201 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1202def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1203 "neg $rT, $rA", IntGeneral, 1204 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1205def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1206 "subfme $rT, $rA", IntGeneral, 1207 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 1208def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1209 "subfze $rT, $rA", IntGeneral, 1210 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1211} 1212 1213// A-Form instructions. Most of the instructions executed in the FPU are of 1214// this type. 1215// 1216let PPC970_Unit = 3 in { // FPU Operations. 1217let Uses = [RM] in { 1218 def FMADD : AForm_1<63, 29, 1219 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1220 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1221 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1222 F8RC:$FRB))]>, 1223 Requires<[FPContractions]>; 1224 def FMADDS : AForm_1<59, 29, 1225 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1226 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1227 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1228 F4RC:$FRB))]>, 1229 Requires<[FPContractions]>; 1230 def FMSUB : AForm_1<63, 28, 1231 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1232 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1233 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1234 F8RC:$FRB))]>, 1235 Requires<[FPContractions]>; 1236 def FMSUBS : AForm_1<59, 28, 1237 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1238 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1239 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1240 F4RC:$FRB))]>, 1241 Requires<[FPContractions]>; 1242 def FNMADD : AForm_1<63, 31, 1243 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1244 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1245 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1246 F8RC:$FRB)))]>, 1247 Requires<[FPContractions]>; 1248 def FNMADDS : AForm_1<59, 31, 1249 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1250 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1251 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1252 F4RC:$FRB)))]>, 1253 Requires<[FPContractions]>; 1254 def FNMSUB : AForm_1<63, 30, 1255 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1256 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1257 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1258 F8RC:$FRB)))]>, 1259 Requires<[FPContractions]>; 1260 def FNMSUBS : AForm_1<59, 30, 1261 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1262 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1263 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1264 F4RC:$FRB)))]>, 1265 Requires<[FPContractions]>; 1266} 1267// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1268// having 4 of these, force the comparison to always be an 8-byte double (code 1269// should use an FMRSD if the input comparison value really wants to be a float) 1270// and 4/8 byte forms for the result and operand type.. 1271def FSELD : AForm_1<63, 23, 1272 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1273 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1274 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1275def FSELS : AForm_1<63, 23, 1276 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1277 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1278 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1279let Uses = [RM] in { 1280 def FADD : AForm_2<63, 21, 1281 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1282 "fadd $FRT, $FRA, $FRB", FPGeneral, 1283 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1284 def FADDS : AForm_2<59, 21, 1285 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1286 "fadds $FRT, $FRA, $FRB", FPGeneral, 1287 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1288 def FDIV : AForm_2<63, 18, 1289 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1290 "fdiv $FRT, $FRA, $FRB", FPDivD, 1291 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1292 def FDIVS : AForm_2<59, 18, 1293 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1294 "fdivs $FRT, $FRA, $FRB", FPDivS, 1295 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1296 def FMUL : AForm_3<63, 25, 1297 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1298 "fmul $FRT, $FRA, $FRB", FPFused, 1299 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1300 def FMULS : AForm_3<59, 25, 1301 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1302 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1303 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1304 def FSUB : AForm_2<63, 20, 1305 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1306 "fsub $FRT, $FRA, $FRB", FPGeneral, 1307 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1308 def FSUBS : AForm_2<59, 20, 1309 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1310 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1311 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1312 } 1313} 1314 1315let PPC970_Unit = 1 in { // FXU Operations. 1316// M-Form instructions. rotate and mask instructions. 1317// 1318let isCommutable = 1 in { 1319// RLWIMI can be commuted if the rotate amount is zero. 1320def RLWIMI : MForm_2<20, 1321 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1322 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1323 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1324 NoEncode<"$rSi">; 1325} 1326def RLWINM : MForm_2<21, 1327 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1328 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1329 []>; 1330def RLWINMo : MForm_2<21, 1331 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1332 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1333 []>, isDOT, PPC970_DGroup_Cracked; 1334def RLWNM : MForm_2<23, 1335 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1336 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1337 []>; 1338} 1339 1340 1341//===----------------------------------------------------------------------===// 1342// DWARF Pseudo Instructions 1343// 1344 1345def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), 1346 "${:comment} .loc $file, $line, $col", 1347 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 1348 (i32 imm:$file))]>; 1349 1350//===----------------------------------------------------------------------===// 1351// PowerPC Instruction Patterns 1352// 1353 1354// Arbitrary immediate support. Implement in terms of LIS/ORI. 1355def : Pat<(i32 imm:$imm), 1356 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1357 1358// Implement the 'not' operation with the NOR instruction. 1359def NOT : Pat<(not GPRC:$in), 1360 (NOR GPRC:$in, GPRC:$in)>; 1361 1362// ADD an arbitrary immediate. 1363def : Pat<(add GPRC:$in, imm:$imm), 1364 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1365// OR an arbitrary immediate. 1366def : Pat<(or GPRC:$in, imm:$imm), 1367 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1368// XOR an arbitrary immediate. 1369def : Pat<(xor GPRC:$in, imm:$imm), 1370 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1371// SUBFIC 1372def : Pat<(sub immSExt16:$imm, GPRC:$in), 1373 (SUBFIC GPRC:$in, imm:$imm)>; 1374 1375// SHL/SRL 1376def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1377 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1378def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1379 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1380 1381// ROTL 1382def : Pat<(rotl GPRC:$in, GPRC:$sh), 1383 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1384def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1385 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1386 1387// RLWNM 1388def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1389 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1390 1391// Calls 1392def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1393 (BL_Darwin tglobaladdr:$dst)>; 1394def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1395 (BL_Darwin texternalsym:$dst)>; 1396def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1397 (BL_SVR4 tglobaladdr:$dst)>; 1398def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1399 (BL_SVR4 texternalsym:$dst)>; 1400 1401 1402def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1403 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1404 1405def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1406 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1407 1408def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1409 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1410 1411 1412 1413// Hi and Lo for Darwin Global Addresses. 1414def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1415def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1416def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1417def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1418def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1419def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1420def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1421 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1422def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1423 (ADDIS GPRC:$in, tconstpool:$g)>; 1424def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1425 (ADDIS GPRC:$in, tjumptable:$g)>; 1426 1427// Fused negative multiply subtract, alternate pattern 1428def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1429 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1430 Requires<[FPContractions]>; 1431def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1432 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1433 Requires<[FPContractions]>; 1434 1435// Standard shifts. These are represented separately from the real shifts above 1436// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1437// amounts. 1438def : Pat<(sra GPRC:$rS, GPRC:$rB), 1439 (SRAW GPRC:$rS, GPRC:$rB)>; 1440def : Pat<(srl GPRC:$rS, GPRC:$rB), 1441 (SRW GPRC:$rS, GPRC:$rB)>; 1442def : Pat<(shl GPRC:$rS, GPRC:$rB), 1443 (SLW GPRC:$rS, GPRC:$rB)>; 1444 1445def : Pat<(zextloadi1 iaddr:$src), 1446 (LBZ iaddr:$src)>; 1447def : Pat<(zextloadi1 xaddr:$src), 1448 (LBZX xaddr:$src)>; 1449def : Pat<(extloadi1 iaddr:$src), 1450 (LBZ iaddr:$src)>; 1451def : Pat<(extloadi1 xaddr:$src), 1452 (LBZX xaddr:$src)>; 1453def : Pat<(extloadi8 iaddr:$src), 1454 (LBZ iaddr:$src)>; 1455def : Pat<(extloadi8 xaddr:$src), 1456 (LBZX xaddr:$src)>; 1457def : Pat<(extloadi16 iaddr:$src), 1458 (LHZ iaddr:$src)>; 1459def : Pat<(extloadi16 xaddr:$src), 1460 (LHZX xaddr:$src)>; 1461def : Pat<(extloadf32 iaddr:$src), 1462 (FMRSD (LFS iaddr:$src))>; 1463def : Pat<(extloadf32 xaddr:$src), 1464 (FMRSD (LFSX xaddr:$src))>; 1465 1466// Memory barriers 1467def : Pat<(membarrier (i32 imm:$ll), 1468 (i32 imm:$ls), 1469 (i32 imm:$sl), 1470 (i32 imm:$ss), 1471 (i32 imm:$device)), 1472 (SYNC)>; 1473 1474include "PPCInstrAltivec.td" 1475include "PPCInstr64Bit.td" 1476