1249259Sdim//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// Subclass of MipsTargetLowering specialized for mips32/64. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdim#ifndef MipsSEISELLOWERING_H 15249259Sdim#define MipsSEISELLOWERING_H 16249259Sdim 17249259Sdim#include "MipsISelLowering.h" 18249259Sdim#include "MipsRegisterInfo.h" 19249259Sdim 20249259Sdimnamespace llvm { 21249259Sdim class MipsSETargetLowering : public MipsTargetLowering { 22249259Sdim public: 23249259Sdim explicit MipsSETargetLowering(MipsTargetMachine &TM); 24249259Sdim 25263508Sdim /// \brief Enable MSA support for the given integer type and Register 26263508Sdim /// class. 27263508Sdim void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 28263508Sdim /// \brief Enable MSA support for the given floating-point type and 29263508Sdim /// Register class. 30263508Sdim void addMSAFloatType(MVT::SimpleValueType Ty, 31263508Sdim const TargetRegisterClass *RC); 32263508Sdim 33249259Sdim virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 34249259Sdim 35249259Sdim virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 36249259Sdim 37249259Sdim virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 38249259Sdim 39249259Sdim virtual MachineBasicBlock * 40249259Sdim EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 41249259Sdim 42251662Sdim virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 43251662Sdim EVT VT) const { 44251662Sdim return false; 45251662Sdim } 46251662Sdim 47249259Sdim virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 48249259Sdim if (VT == MVT::Untyped) 49263508Sdim return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass : 50263508Sdim &Mips::ACC64RegClass; 51249259Sdim 52249259Sdim return TargetLowering::getRepRegClassFor(VT); 53249259Sdim } 54249259Sdim 55249259Sdim private: 56249259Sdim virtual bool 57249259Sdim isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 58249259Sdim unsigned NextStackOffset, 59249259Sdim const MipsFunctionInfo& FI) const; 60249259Sdim 61249259Sdim virtual void 62249259Sdim getOpndList(SmallVectorImpl<SDValue> &Ops, 63249259Sdim std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 64249259Sdim bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 65249259Sdim CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; 66249259Sdim 67263508Sdim SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 68263508Sdim SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 69263508Sdim 70249259Sdim SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 71249259Sdim SelectionDAG &DAG) const; 72249259Sdim 73251662Sdim SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 74251662Sdim SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 75263508Sdim SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 76263508Sdim SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 77263508Sdim SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 78263508Sdim /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions 79263508Sdim /// depending on the indices in the shuffle. 80263508Sdim SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 81251662Sdim 82249259Sdim MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 83249259Sdim MachineBasicBlock *BB) const; 84263508Sdim MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, 85263508Sdim MachineBasicBlock *BB, 86263508Sdim unsigned BranchOp) const; 87263508Sdim /// \brief Emit the COPY_FW pseudo instruction 88263508Sdim MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, 89263508Sdim MachineBasicBlock *BB) const; 90263508Sdim /// \brief Emit the COPY_FD pseudo instruction 91263508Sdim MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, 92263508Sdim MachineBasicBlock *BB) const; 93263508Sdim /// \brief Emit the INSERT_FW pseudo instruction 94263508Sdim MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 95263508Sdim MachineBasicBlock *BB) const; 96263508Sdim /// \brief Emit the INSERT_FD pseudo instruction 97263508Sdim MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 98263508Sdim MachineBasicBlock *BB) const; 99263508Sdim /// \brief Emit the FILL_FW pseudo instruction 100263508Sdim MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 101263508Sdim MachineBasicBlock *BB) const; 102263508Sdim /// \brief Emit the FILL_FD pseudo instruction 103263508Sdim MachineBasicBlock *emitFILL_FD(MachineInstr *MI, 104263508Sdim MachineBasicBlock *BB) const; 105263508Sdim /// \brief Emit the FEXP2_W_1 pseudo instructions. 106263508Sdim MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, 107263508Sdim MachineBasicBlock *BB) const; 108263508Sdim /// \brief Emit the FEXP2_D_1 pseudo instructions. 109263508Sdim MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, 110263508Sdim MachineBasicBlock *BB) const; 111249259Sdim }; 112249259Sdim} 113249259Sdim 114249259Sdim#endif // MipsSEISELLOWERING_H 115