1234353Sdim//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10223017Sdim// This file describes the Mips FPU instruction set. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed// Floating Point Instructions 16193323Sed// ------------------------ 17193323Sed// * 64bit fp: 18193323Sed// - 32 64-bit registers (default mode) 19193323Sed// - 16 even 32-bit registers (32-bit compatible mode) for 20193323Sed// single and double access. 21193323Sed// * 32bit fp: 22193323Sed// - 16 even 32-bit registers - single and double (aliased) 23193323Sed// - 32 32-bit registers (within single-only mode) 24193323Sed//===----------------------------------------------------------------------===// 25193323Sed 26193323Sed// Floating Point Compare and Branch 27263508Sdimdef SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28263508Sdim SDTCisVT<1, i32>, 29263508Sdim SDTCisVT<2, OtherVT>]>; 30221345Sdimdef SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31226633Sdim SDTCisVT<2, i32>]>; 32263508Sdimdef SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33263508Sdim SDTCisSameAs<1, 3>]>; 34263508Sdimdef SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35221345Sdimdef SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36221345Sdim SDTCisVT<1, i32>, 37221345Sdim SDTCisSameAs<1, 2>]>; 38221345Sdimdef SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39221345Sdim SDTCisVT<1, f64>, 40226633Sdim SDTCisVT<2, i32>]>; 41193323Sed 42221345Sdimdef MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 43221345Sdimdef MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 44221345Sdimdef MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 45221345Sdimdef MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 46221345Sdim [SDNPHasChain, SDNPOptInGlue]>; 47263508Sdimdef MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 48221345Sdimdef MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 49221345Sdimdef MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 50221345Sdim SDT_MipsExtractElementF64>; 51193323Sed 52193323Sed// Operand for printing out a condition code. 53234982Sdimlet PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 54193323Sed def condcode : Operand<i32>; 55193323Sed 56193323Sed//===----------------------------------------------------------------------===// 57193323Sed// Feature predicates. 58193323Sed//===----------------------------------------------------------------------===// 59193323Sed 60239462Sdimdef IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 61239462Sdim AssemblerPredicate<"FeatureFP64Bit">; 62239462Sdimdef NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 63239462Sdim AssemblerPredicate<"!FeatureFP64Bit">; 64239462Sdimdef IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 65239462Sdim AssemblerPredicate<"FeatureSingleFloat">; 66239462Sdimdef IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 67239462Sdim AssemblerPredicate<"!FeatureSingleFloat">; 68193323Sed 69234353Sdim// FP immediate patterns. 70234353Sdimdef fpimm0 : PatLeaf<(fpimm), [{ 71234353Sdim return N->isExactlyValue(+0.0); 72234353Sdim}]>; 73234353Sdim 74234353Sdimdef fpimm0neg : PatLeaf<(fpimm), [{ 75234353Sdim return N->isExactlyValue(-0.0); 76234353Sdim}]>; 77234353Sdim 78193323Sed//===----------------------------------------------------------------------===// 79193323Sed// Instruction Class Templates 80193323Sed// 81221345Sdim// A set of multiclasses is used to address the register usage. 82193323Sed// 83193323Sed// S32 - single precision in 16 32bit even fp registers 84193323Sed// single precision in 32 32bit fp registers in SingleOnly mode 85193323Sed// S64 - single precision in 32 64bit fp registers (In64BitMode) 86193323Sed// D32 - double precision in 16 32bit even fp registers 87193323Sed// D64 - double precision in 32 64bit fp registers (In64BitMode) 88193323Sed// 89193323Sed// Only S32 and D32 are supported right now. 90193323Sed//===----------------------------------------------------------------------===// 91193323Sed 92263508Sdimclass ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 93249423Sdim SDPatternOperator OpNode= null_frag> : 94249423Sdim InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 95249423Sdim !strconcat(opstr, "\t$fd, $fs, $ft"), 96249423Sdim [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 97249423Sdim let isCommutable = IsComm; 98249423Sdim} 99193323Sed 100249423Sdimmulticlass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 101249423Sdim SDPatternOperator OpNode = null_frag> { 102263508Sdim def _D32 : ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 103249423Sdim Requires<[NotFP64bit, HasStdEnc]>; 104263508Sdim def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, 105249423Sdim Requires<[IsFP64bit, HasStdEnc]> { 106249423Sdim string DecoderNamespace = "Mips64"; 107249423Sdim } 108234982Sdim} 109234353Sdim 110263508Sdimclass ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 111249423Sdim InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 112249423Sdim InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 113249423Sdim [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>, 114249423Sdim NeverHasSideEffects; 115249423Sdim 116249423Sdimmulticlass ABSS_M<string opstr, InstrItinClass Itin, 117249423Sdim SDPatternOperator OpNode= null_frag> { 118263508Sdim def _D32 : ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 119249423Sdim Requires<[NotFP64bit, HasStdEnc]>; 120263508Sdim def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 121249423Sdim Requires<[IsFP64bit, HasStdEnc]> { 122249423Sdim string DecoderNamespace = "Mips64"; 123249423Sdim } 124234353Sdim} 125234353Sdim 126249423Sdimmulticlass ROUND_M<string opstr, InstrItinClass Itin> { 127263508Sdim def _D32 : ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 128249423Sdim Requires<[NotFP64bit, HasStdEnc]>; 129263508Sdim def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 130249423Sdim Requires<[IsFP64bit, HasStdEnc]> { 131234982Sdim let DecoderNamespace = "Mips64"; 132234982Sdim } 133193323Sed} 134193323Sed 135263508Sdimclass MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 136249423Sdim InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 137249423Sdim InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 138249423Sdim [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 139249423Sdim 140263508Sdimclass MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 141249423Sdim InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 142249423Sdim InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 143249423Sdim [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 144249423Sdim 145263508Sdimclass LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 146263508Sdim SDPatternOperator OpNode= null_frag> : 147263508Sdim InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 148249423Sdim [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { 149249423Sdim let DecoderMethod = "DecodeFMem"; 150263508Sdim let mayLoad = 1; 151226633Sdim} 152193323Sed 153263508Sdimclass SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 154263508Sdim SDPatternOperator OpNode= null_frag> : 155263508Sdim InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 156249423Sdim [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { 157249423Sdim let DecoderMethod = "DecodeFMem"; 158263508Sdim let mayStore = 1; 159193323Sed} 160193323Sed 161263508Sdimclass MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 162249423Sdim SDPatternOperator OpNode = null_frag> : 163249423Sdim InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 164249423Sdim !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 165249423Sdim [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 166249423Sdim 167263508Sdimclass NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 168249423Sdim SDPatternOperator OpNode = null_frag> : 169249423Sdim InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 170249423Sdim !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 171249423Sdim [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 172249423Sdim Itin, FrmFR>; 173249423Sdim 174263508Sdimclass LWXC1_FT<string opstr, RegisterOperand DRC, 175249423Sdim InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 176263508Sdim InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 177249423Sdim !strconcat(opstr, "\t$fd, ${index}(${base})"), 178263508Sdim [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, FrmFI> { 179249423Sdim let AddedComplexity = 20; 180193323Sed} 181249423Sdim 182263508Sdimclass SWXC1_FT<string opstr, RegisterOperand DRC, 183249423Sdim InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 184263508Sdim InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 185249423Sdim !strconcat(opstr, "\t$fs, ${index}(${base})"), 186263508Sdim [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, FrmFI> { 187249423Sdim let AddedComplexity = 20; 188234982Sdim} 189193323Sed 190249423Sdimclass BC1F_FT<string opstr, InstrItinClass Itin, 191249423Sdim SDPatternOperator Op = null_frag> : 192263508Sdim InstSE<(outs), (ins FCCRegsOpnd:$fcc, brtarget:$offset), 193263508Sdim !strconcat(opstr, "\t$fcc, $offset"), 194263508Sdim [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI> { 195249423Sdim let isBranch = 1; 196249423Sdim let isTerminator = 1; 197249423Sdim let hasDelaySlot = 1; 198249423Sdim let Defs = [AT]; 199249423Sdim} 200234353Sdim 201249423Sdimclass CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 202249423Sdim SDPatternOperator OpNode = null_frag> : 203249423Sdim InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 204249423Sdim !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 205249423Sdim [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 206263508Sdim let Defs = [FCC0]; 207263508Sdim let isCodeGenOnly = 1; 208249423Sdim} 209234353Sdim 210263508Sdimclass C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> : 211263508Sdim InstSE<(outs), (ins RC:$fs, RC:$ft), 212263508Sdim !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp, 213263508Sdim FrmFR>; 214263508Sdim 215263508Sdimmulticlass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> { 216263508Sdim def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>; 217263508Sdim def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>; 218263508Sdim def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>; 219263508Sdim def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>; 220263508Sdim def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>; 221263508Sdim def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>; 222263508Sdim def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>; 223263508Sdim def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>; 224263508Sdim def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>; 225263508Sdim def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>; 226263508Sdim def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>; 227263508Sdim def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>; 228263508Sdim def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>; 229263508Sdim def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>; 230263508Sdim def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>; 231263508Sdim def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>; 232263508Sdim} 233263508Sdim 234263508Sdimdefm S : C_COND_M<"s", FGR32Opnd, 16>; 235263508Sdimdefm D32 : C_COND_M<"d", AFGR64Opnd, 17>, 236263508Sdim Requires<[NotFP64bit, HasStdEnc]>; 237263508Sdimlet DecoderNamespace = "Mips64" in 238263508Sdimdefm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>; 239263508Sdim 240193323Sed//===----------------------------------------------------------------------===// 241193323Sed// Floating Point Instructions 242193323Sed//===----------------------------------------------------------------------===// 243263508Sdimdef ROUND_W_S : ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 244263508Sdim ABSS_FM<0xc, 16>; 245263508Sdimdef TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 246263508Sdim ABSS_FM<0xd, 16>; 247263508Sdimdef CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 248263508Sdim ABSS_FM<0xe, 16>; 249263508Sdimdef FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 250263508Sdim ABSS_FM<0xf, 16>; 251263508Sdimdef CVT_W_S : ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 252263508Sdim ABSS_FM<0x24, 16>; 253193323Sed 254249423Sdimdefm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 255249423Sdimdefm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 256249423Sdimdefm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 257249423Sdimdefm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 258249423Sdimdefm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>; 259193323Sed 260249423Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 261263508Sdim def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 262263508Sdim ABSS_FM<0x8, 16>; 263263508Sdim def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 264249423Sdim ABSS_FM<0x8, 17>; 265263508Sdim def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 266263508Sdim ABSS_FM<0x9, 16>; 267263508Sdim def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 268249423Sdim ABSS_FM<0x9, 17>; 269263508Sdim def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 270263508Sdim ABSS_FM<0xa, 16>; 271263508Sdim def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 272263508Sdim ABSS_FM<0xa, 17>; 273263508Sdim def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 274263508Sdim ABSS_FM<0xb, 16>; 275263508Sdim def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 276249423Sdim ABSS_FM<0xb, 17>; 277226633Sdim} 278193323Sed 279263508Sdimdef CVT_S_W : ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>, 280263508Sdim ABSS_FM<0x20, 20>; 281263508Sdimdef CVT_L_S : ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 282263508Sdim ABSS_FM<0x25, 16>; 283263508Sdimdef CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 284263508Sdim ABSS_FM<0x25, 17>; 285249423Sdim 286249423Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 287263508Sdim def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>, 288263508Sdim ABSS_FM<0x20, 17>; 289263508Sdim def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>, 290263508Sdim ABSS_FM<0x21, 20>; 291263508Sdim def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>, 292263508Sdim ABSS_FM<0x21, 16>; 293226633Sdim} 294193323Sed 295249423Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 296263508Sdim def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>, 297263508Sdim ABSS_FM<0x20, 17>; 298263508Sdim def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>, 299263508Sdim ABSS_FM<0x20, 21>; 300263508Sdim def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>, 301263508Sdim ABSS_FM<0x21, 20>; 302263508Sdim def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 303263508Sdim ABSS_FM<0x21, 16>; 304263508Sdim def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>, 305263508Sdim ABSS_FM<0x21, 21>; 306234353Sdim} 307193323Sed 308263508Sdimlet isPseudo = 1, isCodeGenOnly = 1 in { 309263508Sdim def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>; 310263508Sdim def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>; 311263508Sdim def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 312263508Sdim def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>; 313263508Sdim def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 314263508Sdim} 315263508Sdim 316249423Sdimlet Predicates = [NoNaNsFPMath, HasStdEnc] in { 317263508Sdim def FABS_S : ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>, 318263508Sdim ABSS_FM<0x5, 16>; 319263508Sdim def FNEG_S : ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>, 320263508Sdim ABSS_FM<0x7, 16>; 321249423Sdim defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 322249423Sdim defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 323249423Sdim} 324249423Sdim 325263508Sdimdef FSQRT_S : ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle, 326263508Sdim fsqrt>, ABSS_FM<0x4, 16>; 327249423Sdimdefm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; 328249423Sdim 329193323Sed// The odd-numbered registers are only referenced when doing loads, 330193323Sed// stores, and moves between floating-point and integer registers. 331221345Sdim// When defining instructions, we reference all 32-bit registers, 332193323Sed// regardless of register aliasing. 333228379Sdim 334228379Sdim/// Move Control Registers From/To CPU Registers 335263508Sdimdef CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>; 336263508Sdimdef CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>; 337263508Sdimdef MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>, 338263508Sdim MFC1_FM<0>; 339263508Sdimdef MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>, 340263508Sdim MFC1_FM<4>; 341263508Sdimdef MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>, 342263508Sdim MFC1_FM<3>; 343263508Sdimdef MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>, 344263508Sdim MFC1_FM<7>; 345263508Sdimdef DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1, 346263508Sdim bitconvert>, MFC1_FM<1>; 347263508Sdimdef DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1, 348263508Sdim bitconvert>, MFC1_FM<5>; 349193323Sed 350263508Sdimdef FMOV_S : ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>, 351263508Sdim ABSS_FM<0x6, 16>; 352263508Sdimdef FMOV_D32 : ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>, 353263508Sdim ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>; 354263508Sdimdef FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>, 355263508Sdim ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> { 356263508Sdim let DecoderNamespace = "Mips64"; 357234982Sdim} 358203954Srdivacky 359193323Sed/// Floating Point Memory Instructions 360263508Sdimlet Predicates = [HasStdEnc] in { 361263508Sdim def LWC1 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM<0x31>; 362263508Sdim def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>; 363226633Sdim} 364193323Sed 365263508Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 366263508Sdim def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 367263508Sdim def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 368193323Sed} 369193323Sed 370263508Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 371263508Sdim def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 372263508Sdim def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 373234353Sdim} 374234353Sdim 375263508Sdim/// Cop2 Memory Instructions 376263508Sdimlet Predicates = [HasStdEnc] in { 377263508Sdim def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; 378263508Sdim def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; 379263508Sdim def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>; 380263508Sdim def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>; 381234353Sdim} 382234353Sdim 383234353Sdim// Indexed loads and stores. 384249423Sdimlet Predicates = [HasFPIdx, HasStdEnc] in { 385263508Sdim def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>; 386263508Sdim def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>, SWXC1_FM<8>; 387234353Sdim} 388234353Sdim 389263508Sdimlet Predicates = [HasFPIdx, NotFP64bit, HasStdEnc] in { 390263508Sdim def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, IIFLoad, load>, LWXC1_FM<1>; 391263508Sdim def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, IIFStore, store>, SWXC1_FM<9>; 392234353Sdim} 393234353Sdim 394263508Sdimlet Predicates = [HasFPIdx, IsFP64bit, HasStdEnc], 395263508Sdim DecoderNamespace="Mips64" in { 396263508Sdim def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, IIFLoad, load>, LWXC1_FM<1>; 397263508Sdim def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, IIFStore, store>, SWXC1_FM<9>; 398234353Sdim} 399234353Sdim 400239462Sdim// Load/store doubleword indexed unaligned. 401263508Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 402263508Sdim def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>, LWXC1_FM<0x5>; 403263508Sdim def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, SWXC1_FM<0xd>; 404239462Sdim} 405239462Sdim 406263508Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in { 407263508Sdim def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, IIFLoad>, LWXC1_FM<0x5>; 408263508Sdim def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, IIFStore>, SWXC1_FM<0xd>; 409239462Sdim} 410239462Sdim 411193323Sed/// Floating-point Aritmetic 412263508Sdimdef FADD_S : ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>, 413263508Sdim ADDS_FM<0x00, 16>; 414263508Sdimdefm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 415263508Sdimdef FDIV_S : ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, 416263508Sdim ADDS_FM<0x03, 16>; 417263508Sdimdefm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 418263508Sdimdef FMUL_S : ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>, 419263508Sdim ADDS_FM<0x02, 16>; 420263508Sdimdefm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 421263508Sdimdef FSUB_S : ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>, 422263508Sdim ADDS_FM<0x01, 16>; 423263508Sdimdefm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 424193323Sed 425249423Sdimlet Predicates = [HasMips32r2, HasStdEnc] in { 426263508Sdim def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>, 427263508Sdim MADDS_FM<4, 0>; 428263508Sdim def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>, 429263508Sdim MADDS_FM<5, 0>; 430234353Sdim} 431234353Sdim 432249423Sdimlet Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 433263508Sdim def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>, 434263508Sdim MADDS_FM<6, 0>; 435263508Sdim def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>, 436263508Sdim MADDS_FM<7, 0>; 437234353Sdim} 438234353Sdim 439249423Sdimlet Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 440263508Sdim def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>, 441263508Sdim MADDS_FM<4, 1>; 442263508Sdim def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>, 443263508Sdim MADDS_FM<5, 1>; 444234353Sdim} 445234353Sdim 446249423Sdimlet Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 447263508Sdim def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>, 448249423Sdim MADDS_FM<6, 1>; 449263508Sdim def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>, 450249423Sdim MADDS_FM<7, 1>; 451234353Sdim} 452234353Sdim 453249423Sdimlet Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 454263508Sdim def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>, 455263508Sdim MADDS_FM<4, 1>; 456263508Sdim def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>, 457263508Sdim MADDS_FM<5, 1>; 458234353Sdim} 459234353Sdim 460249423Sdimlet Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 461239462Sdim isCodeGenOnly=1 in { 462263508Sdim def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>, 463249423Sdim MADDS_FM<6, 1>; 464263508Sdim def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>, 465249423Sdim MADDS_FM<7, 1>; 466234353Sdim} 467234353Sdim 468193323Sed//===----------------------------------------------------------------------===// 469193323Sed// Floating Point Branch Codes 470193323Sed//===----------------------------------------------------------------------===// 471221345Sdim// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 472193323Sed// They must be kept in synch. 473193323Seddef MIPS_BRANCH_F : PatLeaf<(i32 0)>; 474193323Seddef MIPS_BRANCH_T : PatLeaf<(i32 1)>; 475193323Sed 476249423Sdimdef BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 477249423Sdimdef BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 478263508Sdim 479193323Sed//===----------------------------------------------------------------------===// 480193323Sed// Floating Point Flag Conditions 481193323Sed//===----------------------------------------------------------------------===// 482221345Sdim// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 483193323Sed// They must be kept in synch. 484193323Seddef MIPS_FCOND_F : PatLeaf<(i32 0)>; 485193323Seddef MIPS_FCOND_UN : PatLeaf<(i32 1)>; 486221345Sdimdef MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 487193323Seddef MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 488193323Seddef MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 489193323Seddef MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 490193323Seddef MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 491193323Seddef MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 492193323Seddef MIPS_FCOND_SF : PatLeaf<(i32 8)>; 493193323Seddef MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 494193323Seddef MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 495193323Seddef MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 496193323Seddef MIPS_FCOND_LT : PatLeaf<(i32 12)>; 497193323Seddef MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 498193323Seddef MIPS_FCOND_LE : PatLeaf<(i32 14)>; 499193323Seddef MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 500193323Sed 501193323Sed/// Floating Point Compare 502249423Sdimdef FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 503249423Sdimdef FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 504249423Sdim Requires<[NotFP64bit, HasStdEnc]>; 505249423Sdimlet DecoderNamespace = "Mips64" in 506249423Sdimdef FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 507249423Sdim Requires<[IsFP64bit, HasStdEnc]>; 508193323Sed 509193323Sed//===----------------------------------------------------------------------===// 510221345Sdim// Floating Point Pseudo-Instructions 511221345Sdim//===----------------------------------------------------------------------===// 512221345Sdim 513221345Sdim// This pseudo instr gets expanded into 2 mtc1 instrs after register 514221345Sdim// allocation. 515263508Sdimclass BuildPairF64Base<RegisterOperand RO> : 516263508Sdim PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 517263508Sdim [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; 518221345Sdim 519263508Sdimdef BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, 520263508Sdim Requires<[NotFP64bit, HasStdEnc]>; 521263508Sdimdef BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, 522263508Sdim Requires<[IsFP64bit, HasStdEnc]>; 523263508Sdim 524221345Sdim// This pseudo instr gets expanded into 2 mfc1 instrs after register 525221345Sdim// allocation. 526221345Sdim// if n is 0, lower part of src is extracted. 527221345Sdim// if n is 1, higher part of src is extracted. 528263508Sdimclass ExtractElementF64Base<RegisterOperand RO> : 529263508Sdim PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 530263508Sdim [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; 531221345Sdim 532263508Sdimdef ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, 533263508Sdim Requires<[NotFP64bit, HasStdEnc]>; 534263508Sdimdef ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, 535263508Sdim Requires<[IsFP64bit, HasStdEnc]>; 536263508Sdim 537221345Sdim//===----------------------------------------------------------------------===// 538263508Sdim// InstAliases. 539263508Sdim//===----------------------------------------------------------------------===// 540263508Sdimdef : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>; 541263508Sdimdef : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>; 542263508Sdim 543263508Sdim//===----------------------------------------------------------------------===// 544193323Sed// Floating Point Patterns 545193323Sed//===----------------------------------------------------------------------===// 546239462Sdimdef : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 547239462Sdimdef : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 548193323Sed 549263508Sdimdef : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 550263508Sdim (PseudoCVT_S_W GPR32Opnd:$src)>; 551263508Sdimdef : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 552263508Sdim (TRUNC_W_S FGR32Opnd:$src)>; 553193323Sed 554249423Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 555263508Sdim def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 556263508Sdim (PseudoCVT_D32_W GPR32Opnd:$src)>; 557263508Sdim def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 558263508Sdim (TRUNC_W_D32 AFGR64Opnd:$src)>; 559263508Sdim def : MipsPat<(f32 (fround AFGR64Opnd:$src)), 560263508Sdim (CVT_S_D32 AFGR64Opnd:$src)>; 561263508Sdim def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 562263508Sdim (CVT_D32_S FGR32Opnd:$src)>; 563193323Sed} 564193323Sed 565249423Sdimlet Predicates = [IsFP64bit, HasStdEnc] in { 566239462Sdim def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 567239462Sdim def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 568234353Sdim 569263508Sdim def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 570263508Sdim (PseudoCVT_D64_W GPR32Opnd:$src)>; 571263508Sdim def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 572263508Sdim (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>; 573263508Sdim def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 574263508Sdim (PseudoCVT_D64_L GPR64Opnd:$src)>; 575234353Sdim 576263508Sdim def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 577263508Sdim (TRUNC_W_D64 FGR64Opnd:$src)>; 578263508Sdim def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 579263508Sdim (TRUNC_L_S FGR32Opnd:$src)>; 580263508Sdim def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 581263508Sdim (TRUNC_L_D64 FGR64Opnd:$src)>; 582234353Sdim 583263508Sdim def : MipsPat<(f32 (fround FGR64Opnd:$src)), 584263508Sdim (CVT_S_D64 FGR64Opnd:$src)>; 585263508Sdim def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 586263508Sdim (CVT_D64_S FGR32Opnd:$src)>; 587234353Sdim} 588249423Sdim 589249423Sdim// Patterns for loads/stores with a reg+imm operand. 590249423Sdimlet AddedComplexity = 40 in { 591263508Sdim let Predicates = [HasStdEnc] in { 592249423Sdim def : LoadRegImmPat<LWC1, f32, load>; 593249423Sdim def : StoreRegImmPat<SWC1, f32>; 594249423Sdim } 595249423Sdim 596263508Sdim let Predicates = [IsFP64bit, HasStdEnc] in { 597249423Sdim def : LoadRegImmPat<LDC164, f64, load>; 598249423Sdim def : StoreRegImmPat<SDC164, f64>; 599249423Sdim } 600249423Sdim 601263508Sdim let Predicates = [NotFP64bit, HasStdEnc] in { 602249423Sdim def : LoadRegImmPat<LDC1, f64, load>; 603249423Sdim def : StoreRegImmPat<SDC1, f64>; 604249423Sdim } 605249423Sdim} 606