1226633Sdim//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10226633Sdim// This file provides Mips specific target descriptions. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14226633Sdim#ifndef MIPSMCTARGETDESC_H 15226633Sdim#define MIPSMCTARGETDESC_H 16224133Sdim 17234353Sdim#include "llvm/Support/DataTypes.h" 18234353Sdim 19224133Sdimnamespace llvm { 20226633Sdimclass MCAsmBackend; 21226633Sdimclass MCCodeEmitter; 22226633Sdimclass MCContext; 23234353Sdimclass MCInstrInfo; 24234353Sdimclass MCObjectWriter; 25239462Sdimclass MCRegisterInfo; 26224133Sdimclass MCSubtargetInfo; 27226633Sdimclass StringRef; 28224133Sdimclass Target; 29234353Sdimclass raw_ostream; 30224133Sdim 31224133Sdimextern Target TheMipsTarget; 32224133Sdimextern Target TheMipselTarget; 33226633Sdimextern Target TheMips64Target; 34226633Sdimextern Target TheMips64elTarget; 35224133Sdim 36234353SdimMCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 37239462Sdim const MCRegisterInfo &MRI, 38234353Sdim const MCSubtargetInfo &STI, 39234353Sdim MCContext &Ctx); 40234353SdimMCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 41239462Sdim const MCRegisterInfo &MRI, 42234353Sdim const MCSubtargetInfo &STI, 43234353Sdim MCContext &Ctx); 44226633Sdim 45263508SdimMCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, 46263508Sdim StringRef TT, StringRef CPU); 47263508SdimMCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, 48263508Sdim StringRef TT, StringRef CPU); 49263508SdimMCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, 50263508Sdim StringRef TT, StringRef CPU); 51263508SdimMCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, 52263508Sdim StringRef TT, StringRef CPU); 53234353Sdim 54234353SdimMCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, 55234353Sdim uint8_t OSABI, 56234353Sdim bool IsLittleEndian, 57234353Sdim bool Is64Bit); 58224133Sdim} // End llvm namespace 59224133Sdim 60224133Sdim// Defines symbolic names for Mips registers. This defines a mapping from 61224133Sdim// register name to register number. 62224133Sdim#define GET_REGINFO_ENUM 63224133Sdim#include "MipsGenRegisterInfo.inc" 64224133Sdim 65224133Sdim// Defines symbolic names for the Mips instructions. 66224133Sdim#define GET_INSTRINFO_ENUM 67224133Sdim#include "MipsGenInstrInfo.inc" 68224133Sdim 69224133Sdim#define GET_SUBTARGETINFO_ENUM 70224133Sdim#include "MipsGenSubtargetInfo.inc" 71224133Sdim 72224133Sdim#endif 73