MSP430ISelLowering.cpp revision 208599 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  // Even if we have only 1 bit shift here, we can perform
81  // shifts of the whole bitwidth 1 bit per step.
82  setShiftAmountType(MVT::i8);
83
84  setStackPointerRegisterToSaveRestore(MSP430::SPW);
85  setBooleanContents(ZeroOrOneBooleanContent);
86  setSchedulingPreference(Sched::Latency);
87
88  // We have post-incremented loads / stores.
89  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
91
92  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
95  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
96  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
97
98  // We don't have any truncstores
99  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
100
101  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
102  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
103  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
104  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
105  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
106  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
107  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
108  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
109  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
110  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
111  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
112  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
113  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
114  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
115  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
116  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
117  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
118  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
119  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
120  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
121  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
122  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
123  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
124  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
125  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
127
128  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
129  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
130  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
131  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
132  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
133  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
134
135  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
140  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
141
142  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
143
144  // FIXME: Implement efficiently multiplication by a constant
145  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
146  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
147  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
150  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
151  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
152  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
153  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
154  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
155
156  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
160  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
161  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
162  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
165  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
166  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
167  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
168
169  // Libcalls names.
170  if (HWMultMode == HWMultIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173  } else if (HWMultMode == HWMultNoIntr) {
174    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
175    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176  }
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
180                                             SelectionDAG &DAG) const {
181  switch (Op.getOpcode()) {
182  case ISD::SHL: // FALLTHROUGH
183  case ISD::SRL:
184  case ISD::SRA:              return LowerShifts(Op, DAG);
185  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
186  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
187  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
188  case ISD::SETCC:            return LowerSETCC(Op, DAG);
189  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
190  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
191  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
192  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
193  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
194  default:
195    llvm_unreachable("unimplemented operand");
196    return SDValue();
197  }
198}
199
200/// getFunctionAlignment - Return the Log2 alignment of this function.
201unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
202  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
203}
204
205//===----------------------------------------------------------------------===//
206//                       MSP430 Inline Assembly Support
207//===----------------------------------------------------------------------===//
208
209/// getConstraintType - Given a constraint letter, return the type of
210/// constraint it is for this target.
211TargetLowering::ConstraintType
212MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
213  if (Constraint.size() == 1) {
214    switch (Constraint[0]) {
215    case 'r':
216      return C_RegisterClass;
217    default:
218      break;
219    }
220  }
221  return TargetLowering::getConstraintType(Constraint);
222}
223
224std::pair<unsigned, const TargetRegisterClass*>
225MSP430TargetLowering::
226getRegForInlineAsmConstraint(const std::string &Constraint,
227                             EVT VT) const {
228  if (Constraint.size() == 1) {
229    // GCC Constraint Letters
230    switch (Constraint[0]) {
231    default: break;
232    case 'r':   // GENERAL_REGS
233      if (VT == MVT::i8)
234        return std::make_pair(0U, MSP430::GR8RegisterClass);
235
236      return std::make_pair(0U, MSP430::GR16RegisterClass);
237    }
238  }
239
240  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
241}
242
243//===----------------------------------------------------------------------===//
244//                      Calling Convention Implementation
245//===----------------------------------------------------------------------===//
246
247#include "MSP430GenCallingConv.inc"
248
249SDValue
250MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
251                                           CallingConv::ID CallConv,
252                                           bool isVarArg,
253                                           const SmallVectorImpl<ISD::InputArg>
254                                             &Ins,
255                                           DebugLoc dl,
256                                           SelectionDAG &DAG,
257                                           SmallVectorImpl<SDValue> &InVals)
258                                             const {
259
260  switch (CallConv) {
261  default:
262    llvm_unreachable("Unsupported calling convention");
263  case CallingConv::C:
264  case CallingConv::Fast:
265    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
266  case CallingConv::MSP430_INTR:
267   if (Ins.empty())
268     return Chain;
269   else {
270    report_fatal_error("ISRs cannot have arguments");
271    return SDValue();
272   }
273  }
274}
275
276SDValue
277MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
278                                CallingConv::ID CallConv, bool isVarArg,
279                                bool &isTailCall,
280                                const SmallVectorImpl<ISD::OutputArg> &Outs,
281                                const SmallVectorImpl<ISD::InputArg> &Ins,
282                                DebugLoc dl, SelectionDAG &DAG,
283                                SmallVectorImpl<SDValue> &InVals) const {
284  // MSP430 target does not yet support tail call optimization.
285  isTailCall = false;
286
287  switch (CallConv) {
288  default:
289    llvm_unreachable("Unsupported calling convention");
290  case CallingConv::Fast:
291  case CallingConv::C:
292    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
293                          Outs, Ins, dl, DAG, InVals);
294  case CallingConv::MSP430_INTR:
295    report_fatal_error("ISRs cannot be called directly");
296    return SDValue();
297  }
298}
299
300/// LowerCCCArguments - transform physical registers into virtual registers and
301/// generate load operations for arguments places on the stack.
302// FIXME: struct return stuff
303// FIXME: varargs
304SDValue
305MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
306                                        CallingConv::ID CallConv,
307                                        bool isVarArg,
308                                        const SmallVectorImpl<ISD::InputArg>
309                                          &Ins,
310                                        DebugLoc dl,
311                                        SelectionDAG &DAG,
312                                        SmallVectorImpl<SDValue> &InVals)
313                                          const {
314  MachineFunction &MF = DAG.getMachineFunction();
315  MachineFrameInfo *MFI = MF.getFrameInfo();
316  MachineRegisterInfo &RegInfo = MF.getRegInfo();
317
318  // Assign locations to all of the incoming arguments.
319  SmallVector<CCValAssign, 16> ArgLocs;
320  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
321                 ArgLocs, *DAG.getContext());
322  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
323
324  assert(!isVarArg && "Varargs not supported yet");
325
326  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
327    CCValAssign &VA = ArgLocs[i];
328    if (VA.isRegLoc()) {
329      // Arguments passed in registers
330      EVT RegVT = VA.getLocVT();
331      switch (RegVT.getSimpleVT().SimpleTy) {
332      default:
333        {
334#ifndef NDEBUG
335          errs() << "LowerFormalArguments Unhandled argument type: "
336               << RegVT.getSimpleVT().SimpleTy << "\n";
337#endif
338          llvm_unreachable(0);
339        }
340      case MVT::i16:
341        unsigned VReg =
342          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
343        RegInfo.addLiveIn(VA.getLocReg(), VReg);
344        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
345
346        // If this is an 8-bit value, it is really passed promoted to 16
347        // bits. Insert an assert[sz]ext to capture this, then truncate to the
348        // right size.
349        if (VA.getLocInfo() == CCValAssign::SExt)
350          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
351                                 DAG.getValueType(VA.getValVT()));
352        else if (VA.getLocInfo() == CCValAssign::ZExt)
353          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
354                                 DAG.getValueType(VA.getValVT()));
355
356        if (VA.getLocInfo() != CCValAssign::Full)
357          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
358
359        InVals.push_back(ArgValue);
360      }
361    } else {
362      // Sanity check
363      assert(VA.isMemLoc());
364      // Load the argument to a virtual register
365      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
366      if (ObjSize > 2) {
367        errs() << "LowerFormalArguments Unhandled argument type: "
368             << VA.getLocVT().getSimpleVT().SimpleTy
369             << "\n";
370      }
371      // Create the frame index object for this incoming parameter...
372      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
373
374      // Create the SelectionDAG nodes corresponding to a load
375      //from this parameter
376      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
377      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
378                                   PseudoSourceValue::getFixedStack(FI), 0,
379                                   false, false, 0));
380    }
381  }
382
383  return Chain;
384}
385
386SDValue
387MSP430TargetLowering::LowerReturn(SDValue Chain,
388                                  CallingConv::ID CallConv, bool isVarArg,
389                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
390                                  DebugLoc dl, SelectionDAG &DAG) const {
391
392  // CCValAssign - represent the assignment of the return value to a location
393  SmallVector<CCValAssign, 16> RVLocs;
394
395  // ISRs cannot return any value.
396  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
397    report_fatal_error("ISRs cannot return any value");
398    return SDValue();
399  }
400
401  // CCState - Info about the registers and stack slot.
402  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
403                 RVLocs, *DAG.getContext());
404
405  // Analize return values.
406  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
407
408  // If this is the first return lowered for this function, add the regs to the
409  // liveout set for the function.
410  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
411    for (unsigned i = 0; i != RVLocs.size(); ++i)
412      if (RVLocs[i].isRegLoc())
413        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
414  }
415
416  SDValue Flag;
417
418  // Copy the result values into the output registers.
419  for (unsigned i = 0; i != RVLocs.size(); ++i) {
420    CCValAssign &VA = RVLocs[i];
421    assert(VA.isRegLoc() && "Can only return in registers!");
422
423    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
424                             Outs[i].Val, Flag);
425
426    // Guarantee that all emitted copies are stuck together,
427    // avoiding something bad.
428    Flag = Chain.getValue(1);
429  }
430
431  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
432                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
433
434  if (Flag.getNode())
435    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
436
437  // Return Void
438  return DAG.getNode(Opc, dl, MVT::Other, Chain);
439}
440
441/// LowerCCCCallTo - functions arguments are copied from virtual regs to
442/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
443/// TODO: sret.
444SDValue
445MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
446                                     CallingConv::ID CallConv, bool isVarArg,
447                                     bool isTailCall,
448                                     const SmallVectorImpl<ISD::OutputArg>
449                                       &Outs,
450                                     const SmallVectorImpl<ISD::InputArg> &Ins,
451                                     DebugLoc dl, SelectionDAG &DAG,
452                                     SmallVectorImpl<SDValue> &InVals) const {
453  // Analyze operands of the call, assigning locations to each operand.
454  SmallVector<CCValAssign, 16> ArgLocs;
455  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
456                 ArgLocs, *DAG.getContext());
457
458  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
459
460  // Get a count of how many bytes are to be pushed on the stack.
461  unsigned NumBytes = CCInfo.getNextStackOffset();
462
463  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
464                                                      getPointerTy(), true));
465
466  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
467  SmallVector<SDValue, 12> MemOpChains;
468  SDValue StackPtr;
469
470  // Walk the register/memloc assignments, inserting copies/loads.
471  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
472    CCValAssign &VA = ArgLocs[i];
473
474    SDValue Arg = Outs[i].Val;
475
476    // Promote the value if needed.
477    switch (VA.getLocInfo()) {
478      default: llvm_unreachable("Unknown loc info!");
479      case CCValAssign::Full: break;
480      case CCValAssign::SExt:
481        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
482        break;
483      case CCValAssign::ZExt:
484        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
485        break;
486      case CCValAssign::AExt:
487        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
488        break;
489    }
490
491    // Arguments that can be passed on register must be kept at RegsToPass
492    // vector
493    if (VA.isRegLoc()) {
494      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
495    } else {
496      assert(VA.isMemLoc());
497
498      if (StackPtr.getNode() == 0)
499        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
500
501      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
502                                   StackPtr,
503                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
504
505
506      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
507                                         PseudoSourceValue::getStack(),
508                                         VA.getLocMemOffset(), false, false, 0));
509    }
510  }
511
512  // Transform all store nodes into one single node because all store nodes are
513  // independent of each other.
514  if (!MemOpChains.empty())
515    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
516                        &MemOpChains[0], MemOpChains.size());
517
518  // Build a sequence of copy-to-reg nodes chained together with token chain and
519  // flag operands which copy the outgoing args into registers.  The InFlag in
520  // necessary since all emited instructions must be stuck together.
521  SDValue InFlag;
522  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
523    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
524                             RegsToPass[i].second, InFlag);
525    InFlag = Chain.getValue(1);
526  }
527
528  // If the callee is a GlobalAddress node (quite common, every direct call is)
529  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
530  // Likewise ExternalSymbol -> TargetExternalSymbol.
531  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
532    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
533  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
534    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
535
536  // Returns a chain & a flag for retval copy to use.
537  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
538  SmallVector<SDValue, 8> Ops;
539  Ops.push_back(Chain);
540  Ops.push_back(Callee);
541
542  // Add argument registers to the end of the list so that they are
543  // known live into the call.
544  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
545    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
546                                  RegsToPass[i].second.getValueType()));
547
548  if (InFlag.getNode())
549    Ops.push_back(InFlag);
550
551  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
552  InFlag = Chain.getValue(1);
553
554  // Create the CALLSEQ_END node.
555  Chain = DAG.getCALLSEQ_END(Chain,
556                             DAG.getConstant(NumBytes, getPointerTy(), true),
557                             DAG.getConstant(0, getPointerTy(), true),
558                             InFlag);
559  InFlag = Chain.getValue(1);
560
561  // Handle result values, copying them out of physregs into vregs that we
562  // return.
563  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
564                         DAG, InVals);
565}
566
567/// LowerCallResult - Lower the result values of a call into the
568/// appropriate copies out of appropriate physical registers.
569///
570SDValue
571MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
572                                      CallingConv::ID CallConv, bool isVarArg,
573                                      const SmallVectorImpl<ISD::InputArg> &Ins,
574                                      DebugLoc dl, SelectionDAG &DAG,
575                                      SmallVectorImpl<SDValue> &InVals) const {
576
577  // Assign locations to each value returned by this call.
578  SmallVector<CCValAssign, 16> RVLocs;
579  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
580                 RVLocs, *DAG.getContext());
581
582  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
583
584  // Copy all of the result registers out of their specified physreg.
585  for (unsigned i = 0; i != RVLocs.size(); ++i) {
586    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
587                               RVLocs[i].getValVT(), InFlag).getValue(1);
588    InFlag = Chain.getValue(2);
589    InVals.push_back(Chain.getValue(0));
590  }
591
592  return Chain;
593}
594
595SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
596                                          SelectionDAG &DAG) const {
597  unsigned Opc = Op.getOpcode();
598  SDNode* N = Op.getNode();
599  EVT VT = Op.getValueType();
600  DebugLoc dl = N->getDebugLoc();
601
602  // Expand non-constant shifts to loops:
603  if (!isa<ConstantSDNode>(N->getOperand(1)))
604    switch (Opc) {
605    default:
606      assert(0 && "Invalid shift opcode!");
607    case ISD::SHL:
608      return DAG.getNode(MSP430ISD::SHL, dl,
609                         VT, N->getOperand(0), N->getOperand(1));
610    case ISD::SRA:
611      return DAG.getNode(MSP430ISD::SRA, dl,
612                         VT, N->getOperand(0), N->getOperand(1));
613    case ISD::SRL:
614      return DAG.getNode(MSP430ISD::SRL, dl,
615                         VT, N->getOperand(0), N->getOperand(1));
616    }
617
618  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
619
620  // Expand the stuff into sequence of shifts.
621  // FIXME: for some shift amounts this might be done better!
622  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
623  SDValue Victim = N->getOperand(0);
624
625  if (Opc == ISD::SRL && ShiftAmount) {
626    // Emit a special goodness here:
627    // srl A, 1 => clrc; rrc A
628    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
629    ShiftAmount -= 1;
630  }
631
632  while (ShiftAmount--)
633    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
634                         dl, VT, Victim);
635
636  return Victim;
637}
638
639SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
640                                                 SelectionDAG &DAG) const {
641  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
642  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
643
644  // Create the TargetGlobalAddress node, folding in the constant offset.
645  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
646  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
647                     getPointerTy(), Result);
648}
649
650SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
651                                                  SelectionDAG &DAG) const {
652  DebugLoc dl = Op.getDebugLoc();
653  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
654  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
655
656  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
657}
658
659SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
660                                                SelectionDAG &DAG) const {
661  DebugLoc dl = Op.getDebugLoc();
662  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
663  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
664
665  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
666}
667
668static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
669                       ISD::CondCode CC,
670                       DebugLoc dl, SelectionDAG &DAG) {
671  // FIXME: Handle bittests someday
672  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
673
674  // FIXME: Handle jump negative someday
675  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
676  switch (CC) {
677  default: llvm_unreachable("Invalid integer condition!");
678  case ISD::SETEQ:
679    TCC = MSP430CC::COND_E;     // aka COND_Z
680    // Minor optimization: if LHS is a constant, swap operands, then the
681    // constant can be folded into comparison.
682    if (LHS.getOpcode() == ISD::Constant)
683      std::swap(LHS, RHS);
684    break;
685  case ISD::SETNE:
686    TCC = MSP430CC::COND_NE;    // aka COND_NZ
687    // Minor optimization: if LHS is a constant, swap operands, then the
688    // constant can be folded into comparison.
689    if (LHS.getOpcode() == ISD::Constant)
690      std::swap(LHS, RHS);
691    break;
692  case ISD::SETULE:
693    std::swap(LHS, RHS);        // FALLTHROUGH
694  case ISD::SETUGE:
695    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
696    // fold constant into instruction.
697    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
698      LHS = RHS;
699      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
700      TCC = MSP430CC::COND_LO;
701      break;
702    }
703    TCC = MSP430CC::COND_HS;    // aka COND_C
704    break;
705  case ISD::SETUGT:
706    std::swap(LHS, RHS);        // FALLTHROUGH
707  case ISD::SETULT:
708    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
709    // fold constant into instruction.
710    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
711      LHS = RHS;
712      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
713      TCC = MSP430CC::COND_HS;
714      break;
715    }
716    TCC = MSP430CC::COND_LO;    // aka COND_NC
717    break;
718  case ISD::SETLE:
719    std::swap(LHS, RHS);        // FALLTHROUGH
720  case ISD::SETGE:
721    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
722    // fold constant into instruction.
723    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
724      LHS = RHS;
725      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
726      TCC = MSP430CC::COND_L;
727      break;
728    }
729    TCC = MSP430CC::COND_GE;
730    break;
731  case ISD::SETGT:
732    std::swap(LHS, RHS);        // FALLTHROUGH
733  case ISD::SETLT:
734    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
735    // fold constant into instruction.
736    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
737      LHS = RHS;
738      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
739      TCC = MSP430CC::COND_GE;
740      break;
741    }
742    TCC = MSP430CC::COND_L;
743    break;
744  }
745
746  TargetCC = DAG.getConstant(TCC, MVT::i8);
747  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
748}
749
750
751SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
752  SDValue Chain = Op.getOperand(0);
753  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
754  SDValue LHS   = Op.getOperand(2);
755  SDValue RHS   = Op.getOperand(3);
756  SDValue Dest  = Op.getOperand(4);
757  DebugLoc dl   = Op.getDebugLoc();
758
759  SDValue TargetCC;
760  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
761
762  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
763                     Chain, Dest, TargetCC, Flag);
764}
765
766SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
767  SDValue LHS   = Op.getOperand(0);
768  SDValue RHS   = Op.getOperand(1);
769  DebugLoc dl   = Op.getDebugLoc();
770
771  // If we are doing an AND and testing against zero, then the CMP
772  // will not be generated.  The AND (or BIT) will generate the condition codes,
773  // but they are different from CMP.
774  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
775  // lowering & isel wouldn't diverge.
776  bool andCC = false;
777  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
778    if (RHSC->isNullValue() && LHS.hasOneUse() &&
779        (LHS.getOpcode() == ISD::AND ||
780         (LHS.getOpcode() == ISD::TRUNCATE &&
781          LHS.getOperand(0).getOpcode() == ISD::AND))) {
782      andCC = true;
783    }
784  }
785  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
786  SDValue TargetCC;
787  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
788
789  // Get the condition codes directly from the status register, if its easy.
790  // Otherwise a branch will be generated.  Note that the AND and BIT
791  // instructions generate different flags than CMP, the carry bit can be used
792  // for NE/EQ.
793  bool Invert = false;
794  bool Shift = false;
795  bool Convert = true;
796  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
797   default:
798    Convert = false;
799    break;
800   case MSP430CC::COND_HS:
801     // Res = SRW & 1, no processing is required
802     break;
803   case MSP430CC::COND_LO:
804     // Res = ~(SRW & 1)
805     Invert = true;
806     break;
807   case MSP430CC::COND_NE:
808     if (andCC) {
809       // C = ~Z, thus Res = SRW & 1, no processing is required
810     } else {
811       // Res = ~((SRW >> 1) & 1)
812       Shift = true;
813       Invert = true;
814     }
815     break;
816   case MSP430CC::COND_E:
817     Shift = true;
818     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
819     // Res = (SRW >> 1) & 1 is 1 word shorter.
820     break;
821  }
822  EVT VT = Op.getValueType();
823  SDValue One  = DAG.getConstant(1, VT);
824  if (Convert) {
825    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
826                                    MVT::i16, Flag);
827    if (Shift)
828      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
829      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
830    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
831    if (Invert)
832      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
833    return SR;
834  } else {
835    SDValue Zero = DAG.getConstant(0, VT);
836    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
837    SmallVector<SDValue, 4> Ops;
838    Ops.push_back(One);
839    Ops.push_back(Zero);
840    Ops.push_back(TargetCC);
841    Ops.push_back(Flag);
842    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
843  }
844}
845
846SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
847                                             SelectionDAG &DAG) const {
848  SDValue LHS    = Op.getOperand(0);
849  SDValue RHS    = Op.getOperand(1);
850  SDValue TrueV  = Op.getOperand(2);
851  SDValue FalseV = Op.getOperand(3);
852  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
853  DebugLoc dl    = Op.getDebugLoc();
854
855  SDValue TargetCC;
856  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
857
858  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
859  SmallVector<SDValue, 4> Ops;
860  Ops.push_back(TrueV);
861  Ops.push_back(FalseV);
862  Ops.push_back(TargetCC);
863  Ops.push_back(Flag);
864
865  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
866}
867
868SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
869                                               SelectionDAG &DAG) const {
870  SDValue Val = Op.getOperand(0);
871  EVT VT      = Op.getValueType();
872  DebugLoc dl = Op.getDebugLoc();
873
874  assert(VT == MVT::i16 && "Only support i16 for now!");
875
876  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
877                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
878                     DAG.getValueType(Val.getValueType()));
879}
880
881SDValue
882MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
883  MachineFunction &MF = DAG.getMachineFunction();
884  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
885  int ReturnAddrIndex = FuncInfo->getRAIndex();
886
887  if (ReturnAddrIndex == 0) {
888    // Set up a frame object for the return address.
889    uint64_t SlotSize = TD->getPointerSize();
890    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
891                                                           true, false);
892    FuncInfo->setRAIndex(ReturnAddrIndex);
893  }
894
895  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
896}
897
898SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
899                                              SelectionDAG &DAG) const {
900  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
901  MFI->setReturnAddressIsTaken(true);
902
903  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
904  DebugLoc dl = Op.getDebugLoc();
905
906  if (Depth > 0) {
907    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
908    SDValue Offset =
909      DAG.getConstant(TD->getPointerSize(), MVT::i16);
910    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
911                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
912                                   FrameAddr, Offset),
913                       NULL, 0, false, false, 0);
914  }
915
916  // Just load the return address.
917  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
918  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
919                     RetAddrFI, NULL, 0, false, false, 0);
920}
921
922SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
923                                             SelectionDAG &DAG) const {
924  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
925  MFI->setFrameAddressIsTaken(true);
926
927  EVT VT = Op.getValueType();
928  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
929  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
930  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
931                                         MSP430::FPW, VT);
932  while (Depth--)
933    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
934                            false, false, 0);
935  return FrameAddr;
936}
937
938/// getPostIndexedAddressParts - returns true by value, base pointer and
939/// offset pointer and addressing mode by reference if this node can be
940/// combined with a load / store to form a post-indexed load / store.
941bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
942                                                      SDValue &Base,
943                                                      SDValue &Offset,
944                                                      ISD::MemIndexedMode &AM,
945                                                      SelectionDAG &DAG) const {
946
947  LoadSDNode *LD = cast<LoadSDNode>(N);
948  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
949    return false;
950
951  EVT VT = LD->getMemoryVT();
952  if (VT != MVT::i8 && VT != MVT::i16)
953    return false;
954
955  if (Op->getOpcode() != ISD::ADD)
956    return false;
957
958  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
959    uint64_t RHSC = RHS->getZExtValue();
960    if ((VT == MVT::i16 && RHSC != 2) ||
961        (VT == MVT::i8 && RHSC != 1))
962      return false;
963
964    Base = Op->getOperand(0);
965    Offset = DAG.getConstant(RHSC, VT);
966    AM = ISD::POST_INC;
967    return true;
968  }
969
970  return false;
971}
972
973
974const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
975  switch (Opcode) {
976  default: return NULL;
977  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
978  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
979  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
980  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
981  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
982  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
983  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
984  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
985  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
986  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
987  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
988  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
989  }
990}
991
992bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
993                                          const Type *Ty2) const {
994  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
995    return false;
996
997  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
998}
999
1000bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1001  if (!VT1.isInteger() || !VT2.isInteger())
1002    return false;
1003
1004  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1005}
1006
1007bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
1008  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1009  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1010}
1011
1012bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1013  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1014  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1015}
1016
1017//===----------------------------------------------------------------------===//
1018//  Other Lowering Code
1019//===----------------------------------------------------------------------===//
1020
1021MachineBasicBlock*
1022MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1023                                     MachineBasicBlock *BB) const {
1024  MachineFunction *F = BB->getParent();
1025  MachineRegisterInfo &RI = F->getRegInfo();
1026  DebugLoc dl = MI->getDebugLoc();
1027  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1028
1029  unsigned Opc;
1030  const TargetRegisterClass * RC;
1031  switch (MI->getOpcode()) {
1032  default:
1033    assert(0 && "Invalid shift opcode!");
1034  case MSP430::Shl8:
1035   Opc = MSP430::SHL8r1;
1036   RC = MSP430::GR8RegisterClass;
1037   break;
1038  case MSP430::Shl16:
1039   Opc = MSP430::SHL16r1;
1040   RC = MSP430::GR16RegisterClass;
1041   break;
1042  case MSP430::Sra8:
1043   Opc = MSP430::SAR8r1;
1044   RC = MSP430::GR8RegisterClass;
1045   break;
1046  case MSP430::Sra16:
1047   Opc = MSP430::SAR16r1;
1048   RC = MSP430::GR16RegisterClass;
1049   break;
1050  case MSP430::Srl8:
1051   Opc = MSP430::SAR8r1c;
1052   RC = MSP430::GR8RegisterClass;
1053   break;
1054  case MSP430::Srl16:
1055   Opc = MSP430::SAR16r1c;
1056   RC = MSP430::GR16RegisterClass;
1057   break;
1058  }
1059
1060  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1061  MachineFunction::iterator I = BB;
1062  ++I;
1063
1064  // Create loop block
1065  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1066  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1067
1068  F->insert(I, LoopBB);
1069  F->insert(I, RemBB);
1070
1071  // Update machine-CFG edges by transferring all successors of the current
1072  // block to the block containing instructions after shift.
1073  RemBB->transferSuccessors(BB);
1074
1075  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1076  BB->addSuccessor(LoopBB);
1077  BB->addSuccessor(RemBB);
1078  LoopBB->addSuccessor(RemBB);
1079  LoopBB->addSuccessor(LoopBB);
1080
1081  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1082  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1083  unsigned ShiftReg = RI.createVirtualRegister(RC);
1084  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1085  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1086  unsigned SrcReg = MI->getOperand(1).getReg();
1087  unsigned DstReg = MI->getOperand(0).getReg();
1088
1089  // BB:
1090  // cmp 0, N
1091  // je RemBB
1092  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1093    .addReg(ShiftAmtSrcReg).addImm(0);
1094  BuildMI(BB, dl, TII.get(MSP430::JCC))
1095    .addMBB(RemBB)
1096    .addImm(MSP430CC::COND_E);
1097
1098  // LoopBB:
1099  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1100  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1101  // ShiftReg2 = shift ShiftReg
1102  // ShiftAmt2 = ShiftAmt - 1;
1103  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1104    .addReg(SrcReg).addMBB(BB)
1105    .addReg(ShiftReg2).addMBB(LoopBB);
1106  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1107    .addReg(ShiftAmtSrcReg).addMBB(BB)
1108    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1109  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1110    .addReg(ShiftReg);
1111  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1112    .addReg(ShiftAmtReg).addImm(1);
1113  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1114    .addMBB(LoopBB)
1115    .addImm(MSP430CC::COND_NE);
1116
1117  // RemBB:
1118  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1119  BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
1120    .addReg(SrcReg).addMBB(BB)
1121    .addReg(ShiftReg2).addMBB(LoopBB);
1122
1123  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1124  return RemBB;
1125}
1126
1127MachineBasicBlock*
1128MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1129                                                  MachineBasicBlock *BB) const {
1130  unsigned Opc = MI->getOpcode();
1131
1132  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1133      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1134      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1135    return EmitShiftInstr(MI, BB);
1136
1137  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1138  DebugLoc dl = MI->getDebugLoc();
1139
1140  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1141         "Unexpected instr type to insert");
1142
1143  // To "insert" a SELECT instruction, we actually have to insert the diamond
1144  // control-flow pattern.  The incoming instruction knows the destination vreg
1145  // to set, the condition code register to branch on, the true/false values to
1146  // select between, and a branch opcode to use.
1147  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1148  MachineFunction::iterator I = BB;
1149  ++I;
1150
1151  //  thisMBB:
1152  //  ...
1153  //   TrueVal = ...
1154  //   cmpTY ccX, r1, r2
1155  //   jCC copy1MBB
1156  //   fallthrough --> copy0MBB
1157  MachineBasicBlock *thisMBB = BB;
1158  MachineFunction *F = BB->getParent();
1159  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1160  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1161  BuildMI(BB, dl, TII.get(MSP430::JCC))
1162    .addMBB(copy1MBB)
1163    .addImm(MI->getOperand(3).getImm());
1164  F->insert(I, copy0MBB);
1165  F->insert(I, copy1MBB);
1166  // Update machine-CFG edges by transferring all successors of the current
1167  // block to the new block which will contain the Phi node for the select.
1168  copy1MBB->transferSuccessors(BB);
1169  // Next, add the true and fallthrough blocks as its successors.
1170  BB->addSuccessor(copy0MBB);
1171  BB->addSuccessor(copy1MBB);
1172
1173  //  copy0MBB:
1174  //   %FalseValue = ...
1175  //   # fallthrough to copy1MBB
1176  BB = copy0MBB;
1177
1178  // Update machine-CFG edges
1179  BB->addSuccessor(copy1MBB);
1180
1181  //  copy1MBB:
1182  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1183  //  ...
1184  BB = copy1MBB;
1185  BuildMI(BB, dl, TII.get(MSP430::PHI),
1186          MI->getOperand(0).getReg())
1187    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1188    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1189
1190  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1191  return BB;
1192}
1193