MSP430ISelLowering.cpp revision 204642 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  // Even if we have only 1 bit shift here, we can perform
81  // shifts of the whole bitwidth 1 bit per step.
82  setShiftAmountType(MVT::i8);
83
84  setStackPointerRegisterToSaveRestore(MSP430::SPW);
85  setBooleanContents(ZeroOrOneBooleanContent);
86  setSchedulingPreference(SchedulingForLatency);
87
88  // We have post-incremented loads / stores.
89  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
91
92  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
95  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
96  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
97
98  // We don't have any truncstores
99  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
100
101  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
102  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
103  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
104  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
105  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
106  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
107  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
108  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
109  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
110  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
111  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
112  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
113  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
114  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
115  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
116  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
117  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
118  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
119  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
120  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
121  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
122  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
123  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
124  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
125  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
127
128  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
129  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
130  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
131  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
132  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
133  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
134
135  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
140  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
141
142  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
143
144  // FIXME: Implement efficiently multiplication by a constant
145  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
146  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
147  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
150  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
151  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
152  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
153  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
154  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
155
156  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
160  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
161  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
162  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
165  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
166  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
167  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
168
169  // Libcalls names.
170  if (HWMultMode == HWMultIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173  } else if (HWMultMode == HWMultNoIntr) {
174    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
175    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176  }
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
180  switch (Op.getOpcode()) {
181  case ISD::SHL: // FALLTHROUGH
182  case ISD::SRL:
183  case ISD::SRA:              return LowerShifts(Op, DAG);
184  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
185  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
186  case ISD::SETCC:            return LowerSETCC(Op, DAG);
187  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
188  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
189  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
190  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
191  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
192  default:
193    llvm_unreachable("unimplemented operand");
194    return SDValue();
195  }
196}
197
198/// getFunctionAlignment - Return the Log2 alignment of this function.
199unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
200  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
201}
202
203//===----------------------------------------------------------------------===//
204//                       MSP430 Inline Assembly Support
205//===----------------------------------------------------------------------===//
206
207/// getConstraintType - Given a constraint letter, return the type of
208/// constraint it is for this target.
209TargetLowering::ConstraintType
210MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
211  if (Constraint.size() == 1) {
212    switch (Constraint[0]) {
213    case 'r':
214      return C_RegisterClass;
215    default:
216      break;
217    }
218  }
219  return TargetLowering::getConstraintType(Constraint);
220}
221
222std::pair<unsigned, const TargetRegisterClass*>
223MSP430TargetLowering::
224getRegForInlineAsmConstraint(const std::string &Constraint,
225                             EVT VT) const {
226  if (Constraint.size() == 1) {
227    // GCC Constraint Letters
228    switch (Constraint[0]) {
229    default: break;
230    case 'r':   // GENERAL_REGS
231      if (VT == MVT::i8)
232        return std::make_pair(0U, MSP430::GR8RegisterClass);
233
234      return std::make_pair(0U, MSP430::GR16RegisterClass);
235    }
236  }
237
238  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
239}
240
241//===----------------------------------------------------------------------===//
242//                      Calling Convention Implementation
243//===----------------------------------------------------------------------===//
244
245#include "MSP430GenCallingConv.inc"
246
247SDValue
248MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
249                                           CallingConv::ID CallConv,
250                                           bool isVarArg,
251                                           const SmallVectorImpl<ISD::InputArg>
252                                             &Ins,
253                                           DebugLoc dl,
254                                           SelectionDAG &DAG,
255                                           SmallVectorImpl<SDValue> &InVals) {
256
257  switch (CallConv) {
258  default:
259    llvm_unreachable("Unsupported calling convention");
260  case CallingConv::C:
261  case CallingConv::Fast:
262    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
263  case CallingConv::MSP430_INTR:
264   if (Ins.empty())
265     return Chain;
266   else {
267    llvm_report_error("ISRs cannot have arguments");
268    return SDValue();
269   }
270  }
271}
272
273SDValue
274MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
275                                CallingConv::ID CallConv, bool isVarArg,
276                                bool &isTailCall,
277                                const SmallVectorImpl<ISD::OutputArg> &Outs,
278                                const SmallVectorImpl<ISD::InputArg> &Ins,
279                                DebugLoc dl, SelectionDAG &DAG,
280                                SmallVectorImpl<SDValue> &InVals) {
281  // MSP430 target does not yet support tail call optimization.
282  isTailCall = false;
283
284  switch (CallConv) {
285  default:
286    llvm_unreachable("Unsupported calling convention");
287  case CallingConv::Fast:
288  case CallingConv::C:
289    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
290                          Outs, Ins, dl, DAG, InVals);
291  case CallingConv::MSP430_INTR:
292    llvm_report_error("ISRs cannot be called directly");
293    return SDValue();
294  }
295}
296
297/// LowerCCCArguments - transform physical registers into virtual registers and
298/// generate load operations for arguments places on the stack.
299// FIXME: struct return stuff
300// FIXME: varargs
301SDValue
302MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
303                                        CallingConv::ID CallConv,
304                                        bool isVarArg,
305                                        const SmallVectorImpl<ISD::InputArg>
306                                          &Ins,
307                                        DebugLoc dl,
308                                        SelectionDAG &DAG,
309                                        SmallVectorImpl<SDValue> &InVals) {
310  MachineFunction &MF = DAG.getMachineFunction();
311  MachineFrameInfo *MFI = MF.getFrameInfo();
312  MachineRegisterInfo &RegInfo = MF.getRegInfo();
313
314  // Assign locations to all of the incoming arguments.
315  SmallVector<CCValAssign, 16> ArgLocs;
316  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
317                 ArgLocs, *DAG.getContext());
318  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
319
320  assert(!isVarArg && "Varargs not supported yet");
321
322  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
323    CCValAssign &VA = ArgLocs[i];
324    if (VA.isRegLoc()) {
325      // Arguments passed in registers
326      EVT RegVT = VA.getLocVT();
327      switch (RegVT.getSimpleVT().SimpleTy) {
328      default:
329        {
330#ifndef NDEBUG
331          errs() << "LowerFormalArguments Unhandled argument type: "
332               << RegVT.getSimpleVT().SimpleTy << "\n";
333#endif
334          llvm_unreachable(0);
335        }
336      case MVT::i16:
337        unsigned VReg =
338          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
339        RegInfo.addLiveIn(VA.getLocReg(), VReg);
340        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
341
342        // If this is an 8-bit value, it is really passed promoted to 16
343        // bits. Insert an assert[sz]ext to capture this, then truncate to the
344        // right size.
345        if (VA.getLocInfo() == CCValAssign::SExt)
346          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
347                                 DAG.getValueType(VA.getValVT()));
348        else if (VA.getLocInfo() == CCValAssign::ZExt)
349          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
350                                 DAG.getValueType(VA.getValVT()));
351
352        if (VA.getLocInfo() != CCValAssign::Full)
353          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
354
355        InVals.push_back(ArgValue);
356      }
357    } else {
358      // Sanity check
359      assert(VA.isMemLoc());
360      // Load the argument to a virtual register
361      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
362      if (ObjSize > 2) {
363        errs() << "LowerFormalArguments Unhandled argument type: "
364             << VA.getLocVT().getSimpleVT().SimpleTy
365             << "\n";
366      }
367      // Create the frame index object for this incoming parameter...
368      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
369
370      // Create the SelectionDAG nodes corresponding to a load
371      //from this parameter
372      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
373      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
374                                   PseudoSourceValue::getFixedStack(FI), 0,
375                                   false, false, 0));
376    }
377  }
378
379  return Chain;
380}
381
382SDValue
383MSP430TargetLowering::LowerReturn(SDValue Chain,
384                                  CallingConv::ID CallConv, bool isVarArg,
385                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
386                                  DebugLoc dl, SelectionDAG &DAG) {
387
388  // CCValAssign - represent the assignment of the return value to a location
389  SmallVector<CCValAssign, 16> RVLocs;
390
391  // ISRs cannot return any value.
392  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
393    llvm_report_error("ISRs cannot return any value");
394    return SDValue();
395  }
396
397  // CCState - Info about the registers and stack slot.
398  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
399                 RVLocs, *DAG.getContext());
400
401  // Analize return values.
402  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
403
404  // If this is the first return lowered for this function, add the regs to the
405  // liveout set for the function.
406  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
407    for (unsigned i = 0; i != RVLocs.size(); ++i)
408      if (RVLocs[i].isRegLoc())
409        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
410  }
411
412  SDValue Flag;
413
414  // Copy the result values into the output registers.
415  for (unsigned i = 0; i != RVLocs.size(); ++i) {
416    CCValAssign &VA = RVLocs[i];
417    assert(VA.isRegLoc() && "Can only return in registers!");
418
419    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
420                             Outs[i].Val, Flag);
421
422    // Guarantee that all emitted copies are stuck together,
423    // avoiding something bad.
424    Flag = Chain.getValue(1);
425  }
426
427  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
428                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
429
430  if (Flag.getNode())
431    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
432
433  // Return Void
434  return DAG.getNode(Opc, dl, MVT::Other, Chain);
435}
436
437/// LowerCCCCallTo - functions arguments are copied from virtual regs to
438/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
439/// TODO: sret.
440SDValue
441MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
442                                     CallingConv::ID CallConv, bool isVarArg,
443                                     bool isTailCall,
444                                     const SmallVectorImpl<ISD::OutputArg>
445                                       &Outs,
446                                     const SmallVectorImpl<ISD::InputArg> &Ins,
447                                     DebugLoc dl, SelectionDAG &DAG,
448                                     SmallVectorImpl<SDValue> &InVals) {
449  // Analyze operands of the call, assigning locations to each operand.
450  SmallVector<CCValAssign, 16> ArgLocs;
451  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
452                 ArgLocs, *DAG.getContext());
453
454  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
455
456  // Get a count of how many bytes are to be pushed on the stack.
457  unsigned NumBytes = CCInfo.getNextStackOffset();
458
459  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
460                                                      getPointerTy(), true));
461
462  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
463  SmallVector<SDValue, 12> MemOpChains;
464  SDValue StackPtr;
465
466  // Walk the register/memloc assignments, inserting copies/loads.
467  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
468    CCValAssign &VA = ArgLocs[i];
469
470    SDValue Arg = Outs[i].Val;
471
472    // Promote the value if needed.
473    switch (VA.getLocInfo()) {
474      default: llvm_unreachable("Unknown loc info!");
475      case CCValAssign::Full: break;
476      case CCValAssign::SExt:
477        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
478        break;
479      case CCValAssign::ZExt:
480        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
481        break;
482      case CCValAssign::AExt:
483        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
484        break;
485    }
486
487    // Arguments that can be passed on register must be kept at RegsToPass
488    // vector
489    if (VA.isRegLoc()) {
490      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
491    } else {
492      assert(VA.isMemLoc());
493
494      if (StackPtr.getNode() == 0)
495        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
496
497      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
498                                   StackPtr,
499                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
500
501
502      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
503                                         PseudoSourceValue::getStack(),
504                                         VA.getLocMemOffset(), false, false, 0));
505    }
506  }
507
508  // Transform all store nodes into one single node because all store nodes are
509  // independent of each other.
510  if (!MemOpChains.empty())
511    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
512                        &MemOpChains[0], MemOpChains.size());
513
514  // Build a sequence of copy-to-reg nodes chained together with token chain and
515  // flag operands which copy the outgoing args into registers.  The InFlag in
516  // necessary since all emited instructions must be stuck together.
517  SDValue InFlag;
518  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
519    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
520                             RegsToPass[i].second, InFlag);
521    InFlag = Chain.getValue(1);
522  }
523
524  // If the callee is a GlobalAddress node (quite common, every direct call is)
525  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
526  // Likewise ExternalSymbol -> TargetExternalSymbol.
527  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
528    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
529  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
530    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
531
532  // Returns a chain & a flag for retval copy to use.
533  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
534  SmallVector<SDValue, 8> Ops;
535  Ops.push_back(Chain);
536  Ops.push_back(Callee);
537
538  // Add argument registers to the end of the list so that they are
539  // known live into the call.
540  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
541    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
542                                  RegsToPass[i].second.getValueType()));
543
544  if (InFlag.getNode())
545    Ops.push_back(InFlag);
546
547  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
548  InFlag = Chain.getValue(1);
549
550  // Create the CALLSEQ_END node.
551  Chain = DAG.getCALLSEQ_END(Chain,
552                             DAG.getConstant(NumBytes, getPointerTy(), true),
553                             DAG.getConstant(0, getPointerTy(), true),
554                             InFlag);
555  InFlag = Chain.getValue(1);
556
557  // Handle result values, copying them out of physregs into vregs that we
558  // return.
559  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
560                         DAG, InVals);
561}
562
563/// LowerCallResult - Lower the result values of a call into the
564/// appropriate copies out of appropriate physical registers.
565///
566SDValue
567MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
568                                      CallingConv::ID CallConv, bool isVarArg,
569                                      const SmallVectorImpl<ISD::InputArg> &Ins,
570                                      DebugLoc dl, SelectionDAG &DAG,
571                                      SmallVectorImpl<SDValue> &InVals) {
572
573  // Assign locations to each value returned by this call.
574  SmallVector<CCValAssign, 16> RVLocs;
575  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
576                 RVLocs, *DAG.getContext());
577
578  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
579
580  // Copy all of the result registers out of their specified physreg.
581  for (unsigned i = 0; i != RVLocs.size(); ++i) {
582    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
583                               RVLocs[i].getValVT(), InFlag).getValue(1);
584    InFlag = Chain.getValue(2);
585    InVals.push_back(Chain.getValue(0));
586  }
587
588  return Chain;
589}
590
591SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
592                                          SelectionDAG &DAG) {
593  unsigned Opc = Op.getOpcode();
594  SDNode* N = Op.getNode();
595  EVT VT = Op.getValueType();
596  DebugLoc dl = N->getDebugLoc();
597
598  // Expand non-constant shifts to loops:
599  if (!isa<ConstantSDNode>(N->getOperand(1)))
600    switch (Opc) {
601    default:
602      assert(0 && "Invalid shift opcode!");
603    case ISD::SHL:
604      return DAG.getNode(MSP430ISD::SHL, dl,
605                         VT, N->getOperand(0), N->getOperand(1));
606    case ISD::SRA:
607      return DAG.getNode(MSP430ISD::SRA, dl,
608                         VT, N->getOperand(0), N->getOperand(1));
609    case ISD::SRL:
610      return DAG.getNode(MSP430ISD::SRL, dl,
611                         VT, N->getOperand(0), N->getOperand(1));
612    }
613
614  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
615
616  // Expand the stuff into sequence of shifts.
617  // FIXME: for some shift amounts this might be done better!
618  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
619  SDValue Victim = N->getOperand(0);
620
621  if (Opc == ISD::SRL && ShiftAmount) {
622    // Emit a special goodness here:
623    // srl A, 1 => clrc; rrc A
624    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
625    ShiftAmount -= 1;
626  }
627
628  while (ShiftAmount--)
629    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
630                         dl, VT, Victim);
631
632  return Victim;
633}
634
635SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
636  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
637  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
638
639  // Create the TargetGlobalAddress node, folding in the constant offset.
640  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
641  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
642                     getPointerTy(), Result);
643}
644
645SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
646                                                  SelectionDAG &DAG) {
647  DebugLoc dl = Op.getDebugLoc();
648  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
649  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
650
651  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
652}
653
654static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
655                       ISD::CondCode CC,
656                       DebugLoc dl, SelectionDAG &DAG) {
657  // FIXME: Handle bittests someday
658  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
659
660  // FIXME: Handle jump negative someday
661  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
662  switch (CC) {
663  default: llvm_unreachable("Invalid integer condition!");
664  case ISD::SETEQ:
665    TCC = MSP430CC::COND_E;     // aka COND_Z
666    // Minor optimization: if LHS is a constant, swap operands, then the
667    // constant can be folded into comparison.
668    if (LHS.getOpcode() == ISD::Constant)
669      std::swap(LHS, RHS);
670    break;
671  case ISD::SETNE:
672    TCC = MSP430CC::COND_NE;    // aka COND_NZ
673    // Minor optimization: if LHS is a constant, swap operands, then the
674    // constant can be folded into comparison.
675    if (LHS.getOpcode() == ISD::Constant)
676      std::swap(LHS, RHS);
677    break;
678  case ISD::SETULE:
679    std::swap(LHS, RHS);        // FALLTHROUGH
680  case ISD::SETUGE:
681    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
682    // fold constant into instruction.
683    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
684      LHS = RHS;
685      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
686      TCC = MSP430CC::COND_LO;
687      break;
688    }
689    TCC = MSP430CC::COND_HS;    // aka COND_C
690    break;
691  case ISD::SETUGT:
692    std::swap(LHS, RHS);        // FALLTHROUGH
693  case ISD::SETULT:
694    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
695    // fold constant into instruction.
696    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
697      LHS = RHS;
698      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
699      TCC = MSP430CC::COND_HS;
700      break;
701    }
702    TCC = MSP430CC::COND_LO;    // aka COND_NC
703    break;
704  case ISD::SETLE:
705    std::swap(LHS, RHS);        // FALLTHROUGH
706  case ISD::SETGE:
707    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
708    // fold constant into instruction.
709    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
710      LHS = RHS;
711      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
712      TCC = MSP430CC::COND_L;
713      break;
714    }
715    TCC = MSP430CC::COND_GE;
716    break;
717  case ISD::SETGT:
718    std::swap(LHS, RHS);        // FALLTHROUGH
719  case ISD::SETLT:
720    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
721    // fold constant into instruction.
722    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
723      LHS = RHS;
724      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
725      TCC = MSP430CC::COND_GE;
726      break;
727    }
728    TCC = MSP430CC::COND_L;
729    break;
730  }
731
732  TargetCC = DAG.getConstant(TCC, MVT::i8);
733  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
734}
735
736
737SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
738  SDValue Chain = Op.getOperand(0);
739  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
740  SDValue LHS   = Op.getOperand(2);
741  SDValue RHS   = Op.getOperand(3);
742  SDValue Dest  = Op.getOperand(4);
743  DebugLoc dl   = Op.getDebugLoc();
744
745  SDValue TargetCC;
746  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
747
748  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
749                     Chain, Dest, TargetCC, Flag);
750}
751
752
753SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
754  SDValue LHS   = Op.getOperand(0);
755  SDValue RHS   = Op.getOperand(1);
756  DebugLoc dl   = Op.getDebugLoc();
757
758  // If we are doing an AND and testing against zero, then the CMP
759  // will not be generated.  The AND (or BIT) will generate the condition codes,
760  // but they are different from CMP.
761  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
762  // lowering & isel wouldn't diverge.
763  bool andCC = false;
764  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
765    if (RHSC->isNullValue() && LHS.hasOneUse() &&
766        (LHS.getOpcode() == ISD::AND ||
767         (LHS.getOpcode() == ISD::TRUNCATE &&
768          LHS.getOperand(0).getOpcode() == ISD::AND))) {
769      andCC = true;
770    }
771  }
772  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
773  SDValue TargetCC;
774  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
775
776  // Get the condition codes directly from the status register, if its easy.
777  // Otherwise a branch will be generated.  Note that the AND and BIT
778  // instructions generate different flags than CMP, the carry bit can be used
779  // for NE/EQ.
780  bool Invert = false;
781  bool Shift = false;
782  bool Convert = true;
783  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
784   default:
785    Convert = false;
786    break;
787   case MSP430CC::COND_HS:
788     // Res = SRW & 1, no processing is required
789     break;
790   case MSP430CC::COND_LO:
791     // Res = ~(SRW & 1)
792     Invert = true;
793     break;
794   case MSP430CC::COND_NE:
795     if (andCC) {
796       // C = ~Z, thus Res = SRW & 1, no processing is required
797     } else {
798       // Res = ~((SRW >> 1) & 1)
799       Shift = true;
800       Invert = true;
801     }
802     break;
803   case MSP430CC::COND_E:
804     Shift = true;
805     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
806     // Res = (SRW >> 1) & 1 is 1 word shorter.
807     break;
808  }
809  EVT VT = Op.getValueType();
810  SDValue One  = DAG.getConstant(1, VT);
811  if (Convert) {
812    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
813                                    MVT::i16, Flag);
814    if (Shift)
815      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
816      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
817    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
818    if (Invert)
819      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
820    return SR;
821  } else {
822    SDValue Zero = DAG.getConstant(0, VT);
823    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
824    SmallVector<SDValue, 4> Ops;
825    Ops.push_back(One);
826    Ops.push_back(Zero);
827    Ops.push_back(TargetCC);
828    Ops.push_back(Flag);
829    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
830  }
831}
832
833SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
834  SDValue LHS    = Op.getOperand(0);
835  SDValue RHS    = Op.getOperand(1);
836  SDValue TrueV  = Op.getOperand(2);
837  SDValue FalseV = Op.getOperand(3);
838  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
839  DebugLoc dl    = Op.getDebugLoc();
840
841  SDValue TargetCC;
842  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
843
844  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
845  SmallVector<SDValue, 4> Ops;
846  Ops.push_back(TrueV);
847  Ops.push_back(FalseV);
848  Ops.push_back(TargetCC);
849  Ops.push_back(Flag);
850
851  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
852}
853
854SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
855                                               SelectionDAG &DAG) {
856  SDValue Val = Op.getOperand(0);
857  EVT VT      = Op.getValueType();
858  DebugLoc dl = Op.getDebugLoc();
859
860  assert(VT == MVT::i16 && "Only support i16 for now!");
861
862  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
863                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
864                     DAG.getValueType(Val.getValueType()));
865}
866
867SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
868  MachineFunction &MF = DAG.getMachineFunction();
869  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
870  int ReturnAddrIndex = FuncInfo->getRAIndex();
871
872  if (ReturnAddrIndex == 0) {
873    // Set up a frame object for the return address.
874    uint64_t SlotSize = TD->getPointerSize();
875    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
876                                                           true, false);
877    FuncInfo->setRAIndex(ReturnAddrIndex);
878  }
879
880  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
881}
882
883SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
884  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
885  DebugLoc dl = Op.getDebugLoc();
886
887  if (Depth > 0) {
888    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
889    SDValue Offset =
890      DAG.getConstant(TD->getPointerSize(), MVT::i16);
891    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
892                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
893                                   FrameAddr, Offset),
894                       NULL, 0, false, false, 0);
895  }
896
897  // Just load the return address.
898  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
899  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
900                     RetAddrFI, NULL, 0, false, false, 0);
901}
902
903SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
904  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
905  MFI->setFrameAddressIsTaken(true);
906  EVT VT = Op.getValueType();
907  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
908  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
909  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
910                                         MSP430::FPW, VT);
911  while (Depth--)
912    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
913                            false, false, 0);
914  return FrameAddr;
915}
916
917/// getPostIndexedAddressParts - returns true by value, base pointer and
918/// offset pointer and addressing mode by reference if this node can be
919/// combined with a load / store to form a post-indexed load / store.
920bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
921                                                      SDValue &Base,
922                                                      SDValue &Offset,
923                                                      ISD::MemIndexedMode &AM,
924                                                      SelectionDAG &DAG) const {
925
926  LoadSDNode *LD = cast<LoadSDNode>(N);
927  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
928    return false;
929
930  EVT VT = LD->getMemoryVT();
931  if (VT != MVT::i8 && VT != MVT::i16)
932    return false;
933
934  if (Op->getOpcode() != ISD::ADD)
935    return false;
936
937  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
938    uint64_t RHSC = RHS->getZExtValue();
939    if ((VT == MVT::i16 && RHSC != 2) ||
940        (VT == MVT::i8 && RHSC != 1))
941      return false;
942
943    Base = Op->getOperand(0);
944    Offset = DAG.getConstant(RHSC, VT);
945    AM = ISD::POST_INC;
946    return true;
947  }
948
949  return false;
950}
951
952
953const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
954  switch (Opcode) {
955  default: return NULL;
956  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
957  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
958  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
959  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
960  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
961  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
962  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
963  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
964  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
965  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
966  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
967  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
968  }
969}
970
971bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
972                                          const Type *Ty2) const {
973  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
974    return false;
975
976  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
977}
978
979bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
980  if (!VT1.isInteger() || !VT2.isInteger())
981    return false;
982
983  return (VT1.getSizeInBits() > VT2.getSizeInBits());
984}
985
986bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
987  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
988  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
989}
990
991bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
992  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
993  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
994}
995
996//===----------------------------------------------------------------------===//
997//  Other Lowering Code
998//===----------------------------------------------------------------------===//
999
1000MachineBasicBlock*
1001MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1002                                     MachineBasicBlock *BB,
1003                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1004  MachineFunction *F = BB->getParent();
1005  MachineRegisterInfo &RI = F->getRegInfo();
1006  DebugLoc dl = MI->getDebugLoc();
1007  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1008
1009  unsigned Opc;
1010  const TargetRegisterClass * RC;
1011  switch (MI->getOpcode()) {
1012  default:
1013    assert(0 && "Invalid shift opcode!");
1014  case MSP430::Shl8:
1015   Opc = MSP430::SHL8r1;
1016   RC = MSP430::GR8RegisterClass;
1017   break;
1018  case MSP430::Shl16:
1019   Opc = MSP430::SHL16r1;
1020   RC = MSP430::GR16RegisterClass;
1021   break;
1022  case MSP430::Sra8:
1023   Opc = MSP430::SAR8r1;
1024   RC = MSP430::GR8RegisterClass;
1025   break;
1026  case MSP430::Sra16:
1027   Opc = MSP430::SAR16r1;
1028   RC = MSP430::GR16RegisterClass;
1029   break;
1030  case MSP430::Srl8:
1031   Opc = MSP430::SAR8r1c;
1032   RC = MSP430::GR8RegisterClass;
1033   break;
1034  case MSP430::Srl16:
1035   Opc = MSP430::SAR16r1c;
1036   RC = MSP430::GR16RegisterClass;
1037   break;
1038  }
1039
1040  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1041  MachineFunction::iterator I = BB;
1042  ++I;
1043
1044  // Create loop block
1045  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1046  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1047
1048  F->insert(I, LoopBB);
1049  F->insert(I, RemBB);
1050
1051  // Update machine-CFG edges by transferring all successors of the current
1052  // block to the block containing instructions after shift.
1053  RemBB->transferSuccessors(BB);
1054
1055  // Inform sdisel of the edge changes.
1056  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1057         SE = BB->succ_end(); SI != SE; ++SI)
1058    EM->insert(std::make_pair(*SI, RemBB));
1059
1060  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1061  BB->addSuccessor(LoopBB);
1062  BB->addSuccessor(RemBB);
1063  LoopBB->addSuccessor(RemBB);
1064  LoopBB->addSuccessor(LoopBB);
1065
1066  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1067  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1068  unsigned ShiftReg = RI.createVirtualRegister(RC);
1069  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1070  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1071  unsigned SrcReg = MI->getOperand(1).getReg();
1072  unsigned DstReg = MI->getOperand(0).getReg();
1073
1074  // BB:
1075  // cmp 0, N
1076  // je RemBB
1077  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1078    .addReg(ShiftAmtSrcReg).addImm(0);
1079  BuildMI(BB, dl, TII.get(MSP430::JCC))
1080    .addMBB(RemBB)
1081    .addImm(MSP430CC::COND_E);
1082
1083  // LoopBB:
1084  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1085  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1086  // ShiftReg2 = shift ShiftReg
1087  // ShiftAmt2 = ShiftAmt - 1;
1088  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1089    .addReg(SrcReg).addMBB(BB)
1090    .addReg(ShiftReg2).addMBB(LoopBB);
1091  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1092    .addReg(ShiftAmtSrcReg).addMBB(BB)
1093    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1094  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1095    .addReg(ShiftReg);
1096  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1097    .addReg(ShiftAmtReg).addImm(1);
1098  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1099    .addMBB(LoopBB)
1100    .addImm(MSP430CC::COND_NE);
1101
1102  // RemBB:
1103  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1104  BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
1105    .addReg(SrcReg).addMBB(BB)
1106    .addReg(ShiftReg2).addMBB(LoopBB);
1107
1108  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1109  return RemBB;
1110}
1111
1112MachineBasicBlock*
1113MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1114                                                  MachineBasicBlock *BB,
1115                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1116  unsigned Opc = MI->getOpcode();
1117
1118  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1119      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1120      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1121    return EmitShiftInstr(MI, BB, EM);
1122
1123  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1124  DebugLoc dl = MI->getDebugLoc();
1125
1126  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1127         "Unexpected instr type to insert");
1128
1129  // To "insert" a SELECT instruction, we actually have to insert the diamond
1130  // control-flow pattern.  The incoming instruction knows the destination vreg
1131  // to set, the condition code register to branch on, the true/false values to
1132  // select between, and a branch opcode to use.
1133  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1134  MachineFunction::iterator I = BB;
1135  ++I;
1136
1137  //  thisMBB:
1138  //  ...
1139  //   TrueVal = ...
1140  //   cmpTY ccX, r1, r2
1141  //   jCC copy1MBB
1142  //   fallthrough --> copy0MBB
1143  MachineBasicBlock *thisMBB = BB;
1144  MachineFunction *F = BB->getParent();
1145  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1146  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1147  BuildMI(BB, dl, TII.get(MSP430::JCC))
1148    .addMBB(copy1MBB)
1149    .addImm(MI->getOperand(3).getImm());
1150  F->insert(I, copy0MBB);
1151  F->insert(I, copy1MBB);
1152  // Inform sdisel of the edge changes.
1153  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1154         SE = BB->succ_end(); SI != SE; ++SI)
1155    EM->insert(std::make_pair(*SI, copy1MBB));
1156  // Update machine-CFG edges by transferring all successors of the current
1157  // block to the new block which will contain the Phi node for the select.
1158  copy1MBB->transferSuccessors(BB);
1159  // Next, add the true and fallthrough blocks as its successors.
1160  BB->addSuccessor(copy0MBB);
1161  BB->addSuccessor(copy1MBB);
1162
1163  //  copy0MBB:
1164  //   %FalseValue = ...
1165  //   # fallthrough to copy1MBB
1166  BB = copy0MBB;
1167
1168  // Update machine-CFG edges
1169  BB->addSuccessor(copy1MBB);
1170
1171  //  copy1MBB:
1172  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1173  //  ...
1174  BB = copy1MBB;
1175  BuildMI(BB, dl, TII.get(MSP430::PHI),
1176          MI->getOperand(0).getReg())
1177    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1178    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1179
1180  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1181  return BB;
1182}
1183