1234285Sdim//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// 10234285Sdim// This file implements the Hexagon specific subclass of TargetSubtarget. 11234285Sdim// 12234285Sdim//===----------------------------------------------------------------------===// 13234285Sdim 14234285Sdim#include "HexagonSubtarget.h" 15234285Sdim#include "Hexagon.h" 16239462Sdim#include "HexagonRegisterInfo.h" 17234285Sdim#include "llvm/Support/CommandLine.h" 18234285Sdim#include "llvm/Support/ErrorHandling.h" 19234285Sdimusing namespace llvm; 20234285Sdim 21234285Sdim#define GET_SUBTARGETINFO_CTOR 22234285Sdim#define GET_SUBTARGETINFO_TARGET_DESC 23234285Sdim#include "HexagonGenSubtargetInfo.inc" 24234285Sdim 25234285Sdimstatic cl::opt<bool> 26234285SdimEnableV3("enable-hexagon-v3", cl::Hidden, 27234285Sdim cl::desc("Enable Hexagon V3 instructions.")); 28234285Sdim 29234285Sdimstatic cl::opt<bool> 30234285SdimEnableMemOps( 31234285Sdim "enable-hexagon-memops", 32249423Sdim cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true), 33249423Sdim cl::desc( 34249423Sdim "Generate V4 MEMOP in code generation for Hexagon target")); 35234285Sdim 36239462Sdimstatic cl::opt<bool> 37249423SdimDisableMemOps( 38249423Sdim "disable-hexagon-memops", 39249423Sdim cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false), 40249423Sdim cl::desc( 41249423Sdim "Do not generate V4 MEMOP in code generation for Hexagon target")); 42249423Sdim 43249423Sdimstatic cl::opt<bool> 44239462SdimEnableIEEERndNear( 45239462Sdim "enable-hexagon-ieee-rnd-near", 46239462Sdim cl::Hidden, cl::ZeroOrMore, cl::init(false), 47239462Sdim cl::desc("Generate non-chopped conversion from fp to int.")); 48239462Sdim 49234285SdimHexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): 50234285Sdim HexagonGenSubtargetInfo(TT, CPU, FS), 51234285Sdim CPUString(CPU.str()) { 52234285Sdim 53243830Sdim // If the programmer has not specified a Hexagon version, default to -mv4. 54243830Sdim if (CPUString.empty()) 55243830Sdim CPUString = "hexagonv4"; 56243830Sdim 57243830Sdim if (CPUString == "hexagonv2") { 58243830Sdim HexagonArchVersion = V2; 59243830Sdim } else if (CPUString == "hexagonv3") { 60234285Sdim EnableV3 = true; 61243830Sdim HexagonArchVersion = V3; 62243830Sdim } else if (CPUString == "hexagonv4") { 63243830Sdim HexagonArchVersion = V4; 64243830Sdim } else if (CPUString == "hexagonv5") { 65243830Sdim HexagonArchVersion = V5; 66243830Sdim } else { 67243830Sdim llvm_unreachable("Unrecognized Hexagon processor version"); 68234285Sdim } 69234285Sdim 70243830Sdim ParseSubtargetFeatures(CPUString, FS); 71243830Sdim 72234285Sdim // Initialize scheduling itinerary for the specified CPU. 73234285Sdim InstrItins = getInstrItineraryForCPU(CPUString); 74234285Sdim 75249423Sdim // UseMemOps on by default unless disabled explicitly 76249423Sdim if (DisableMemOps) 77249423Sdim UseMemOps = false; 78249423Sdim else if (EnableMemOps) 79234285Sdim UseMemOps = true; 80234285Sdim else 81234285Sdim UseMemOps = false; 82239462Sdim 83239462Sdim if (EnableIEEERndNear) 84239462Sdim ModeIEEERndNear = true; 85239462Sdim else 86239462Sdim ModeIEEERndNear = false; 87234285Sdim} 88239462Sdim 89263508Sdim// Pin the vtable to this file. 90263508Sdimvoid HexagonSubtarget::anchor() {} 91